The logical and physical addresses

Pages and Frames

Page Table and its size

TLB : Associative cache

Multilevel Paging for large address spaces

    Eliminates the need for a single large contiguous
                 address space for the page table

   Entire Page table need not be in main memory
   at a time, a few pages that are required for the
   current context will suffice;
   and this number may be very small as compared to
   a large page table that stays in the main
   memory in its entirety

Example:  32 bit logical address space

Single level page table:
|--20 bits : #p ---| --- 12 bits: offset ---/ 
                                                          20
a single page table would require  2   
(i.e. 1M) entries 
 

Let's look at a two level page table:

|--10 bits: #p1--/--10 bits : #p2 ---/---12 bits offset --|

                                 10
first level table has 2     (i.e. 1K) entries

                                    10                                    10
The second level has 2     (i.e. 1K)  tables with 2
(i.e. 1K) entries each.

Now, for a given context, you could keep the entire
1st level page in the main memory and only the
current page from the second level  that gives us,
only 2K entries in the main memory instead of
the total of 1M entries. Keeping n pages from
the second level in the main memory gives
us a total of  (1+n) K  entries