Conference Papers

  1. Saurabh Goyal, S.S.S.P.Rao, A Novel and Simple Approach for Testing of FPGAs for Multiple Stuck-at Faults in the Logic Blocks, IINC-2005, DEC 19-21, 2005, IIT Bombay.


  2. Meeta Srivastav, S.S.S.P.Rao, Himanshu Bhatnagar, "Power Reduction Technique using Multi-vt Libraries", The 5th IEEE International Workshop on System-on-chip for Real-Time Applications, 20th to 24th July 2005, Banff Alberta, Canada, pp.363-367.


  3. Mihir Choudhury, Saurabh Agarwal, Kalyan Kumar Lakkavarapukota, S.S.S.P.Rao, "Multiple Fault testing of Logic Resources of SRAM-Based FPGAs", 18th International Conference on VLSI Design, Jan.3-7, 2005, Kolkatta, India (accepted)


  4. K.T.Oommen Tharakan, A.N.Chandorkar, S.S.S.P.Rao, Vikram Shenoy, Purushothama P, K.Chandra Sekaran, "Digital System Testing using parallel Genetic Algorithms in MPI environmet", 12th IEEE International Conference on High Performance Computing (December 2005)


  5. C.R.Freny, Vijaya Shivgand, Dr.S.S.S.P. Rao, V.B.Chandratre and Dr.S.K.Kataria, "FPGA Based IEEE 488.1 Compatible TMS 9914 Prototype, Proceedings of National Symposium on Nuclear Instrumentation 2004 (NSNI-2004) held from NSNI-2004 from Feb. 17 - 20, 2004 at Kalpakkam, Chennai, pp.303-306.


  6. Emmela Chaitanya, Prof.S.S.S.P.Rao, FPGA Implementation of Data Compression, Proceedings of National Symposium on Nuclear Instrumentation 2004 (NSNI-2004) held from NSNI-2004 from Feb. 17 - 20, 2004 at Kalpakkam, Chennai, pp.326-330.


  7. Saumya Chandra, Seetha Jayasankar and Prof.S.S.S.P.Rao, FPGA Implementation of Digital Phase Lock Loop for Clock Recovery Applications Proceedings of National Symposium on Nuclear Instrumentation 2004 (NSNI-2004) held from NSNI-2004 from Feb. 17 - 20, 2004 at Kalpakkam, Chennai, pp.331-334.


  8. Vivek Gupta, Emmela Chaitanya, Dr.S.S.S.P.Rao, V.B.Chandatre and Dr.S.K.Kataria, High Speed 8051 Compatible FPGA IP Core, Proceedings of National Symposium on Nuclear Instrumentation 2004 (NSNI-2004) held from NSNI-2004 from Feb. 17 - 20, 2004 at Kalpakkam, Chennai, pp.350-354.


  9. Usha Priyadharshini, Meeta Srivastav, Poonam Yadav, Dr.S.S.S.P.Rao, Paresh Motiwala and Dr.S.K.Kataria, S5933 PCI Matchmaker Controller Chip Compatible Soft Core Implementation on an FPGA, Proceedings of National Symposium on Nuclear Instrumentation 2004 (NSNI-2004) held from NSNI-2004 from Feb. 17 - 20, 2004 at Kalpakkam, Chennai, pp.368-372.


  10. C.R.Venugopal, S.S.S.P.Rao, S.K.Ghoshal, " Parallel Distributed File System Analytical Model & Performance Evaluation" 3rd Annual Conference on on Advance Computing at Bangalore, Dec.4-7, 1995.


  11. C.R.Venugopal, S.S.S.P.Rao, " Impact of Delays in Parallel I/O Systems An Empirical Study" Proceedings of 5th IEEE Intl. Symposium on High Performance Distributed Computing (HPDC-5), Syracuse, N.Y., Aug.6-9, 1996, pp.490-499.


  12. S.Ramesh, S.S.S.P.Rao, G.Sivakumar, P.Bhaduri "Formal Specification & Verification of Hardware Designs", Proceedings of SPIE Vol 3412, Photomask and X-Ray Mask Tech V pp 261-268, Kawasaki, Japan, 1998.


  13. C.R.Venugopal, S.S.S.P.Rao, Sachin Patkar "Priority Scheduling in in Parallel I/O Systems" 1999 Intl. Conf. on Parallel and Distributed Processing Techniques and Applications (PDPTA'99), June 28 - July 1, 1999, Las Vegas, Nevada, USA


  14. C.R.Venugopal, S.S.S.P.Rao, Sachin Patkar "Parallel I/O : Modelling and Scheduling Policies", TENCON'99, Korea.


  15. C.R.Venugopal, S.S.S.P.Rao, "Modeling & Priority Scheduling in Parallel I/O Systems", Eleventh IASTED Intl. Conf. on Parallel & Systems Distributed Computing & Systems (PDCS'99), Cambridge, MA, USA, Nov.3-6,1999


  16. K.T.Ommenn Tharakan, S.S.S.P.Rao, "Apriori Testing of Erasable Programmable Logic Devices", National Conference on Quality Engg. in Aerospace Technologies, Thiruvananthapuram, India, Nov. 2001.


  17. J K. Baswaraj,S.Deepalakshmi, S.S.S.P.Rao, B.S.Jagdish, P.S.Dhekne, H.K.Kaura", Parallel File System on a Networked Intel Workstation", The 2002 International Networked Intel Workstation Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'02), Las Vegas, USA, June 24-27, 2002, pp 1906-1911.


  18. K.T.Ommenn Tharakan, S.S.S.P.Rao, S.Ramesh, "Test Generation of a Pipelined Processor", European Space Components Conf.(ESCCON 2002) from 24th to 27th Sept. 2002,Toulouse, France, pp.353-360.


  19. Deepalakashmi, K.Baswaraj, S.S.S.P.Rao, B.S.Jagdish, D.D.Sonavane, P.S.Dhekne, H.K.Kaura, Performance Analysis of Parallel File System for I/O Load Balancing in Distributed Applications", Proceedings of The 2003 International Conference & Distributed Processing Techniques and Applications (PDPTA'03: June 23-26, 2003, Las Vegas, Nevada, USA, Vol.II, pp.713-720.


  20. Namit Chaturvedi, S.S.S.P.Rao, S.C.Patwardhan, "Programming Process Control in Embedded Systems", Proceedings of The 2003 International Conference on Embedded systems and Applications (ESA'03: June 23-26, 2003, Las Vegas Nevada, USA, pp.87-94


  21. K.Baswaraj, S.S.S.P.Rao, B.S.Jagdish, D.D.Sonavane, P.S.Dhekne, H.K.Kaura, "Parallelization by Pattern Matching", Proceedings of The 2003 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'03: June 23-26, 2003, Las Vegas, Nevada, USA, pp.1891-1895.


  22. Oommen Tharakan, A.N.Chandorkar, S.S.S.P.Rao, Annappa K.Chandrasekharan, "Development of a Genetic Algorithm Technique for VLSI Testing", The Third International Conference on Intelligent Systems Design and Applications (ISDA-03) at Oklahama State Univ., USA, August 10-12, 2003
  23. Oommen Tharakan, A.N.Chandorkar, S.S.S.P.Rao and K.Chandrasekharan, Development of a Genetic Algorithm Technique for VLSI Testing, Eleventh International Conference on Advanced Computers and Communications (ADCOM-2003), December 2003, PSG College of Technology, Coimbatore, India.(Available on CD)


  24. Oommen Tharakan, A.N.Chandorkar, S.S.S.P.Rao,and K.Chandrasekharan, Development of an abstract model for a non-volatile static random access memory, Defence Science Journal published by DESIDOC, Volume 54, April 2004, pp.183-188.


  25. Tillu, A.P., Diwan A.A., Rao, S.S.S.P., "Interconnection Network Based on finite Projective Geometries", Parallel Computing'91, 3-6 Sept.1991.


  26. Pai, Ravi R., Rao, S.S.S.P., "Over the Cell Channel Router", VLSI'91 (IFIP WG.10.5), Edinburgh, Scotland, Aug.20-22, 1991.


  27. S.M.Bhandari, S.S.S.P.Rao, " VLSI Implementation of a varsatile electronics neuron and its application", IEEE TENCON'91, Tech, for 2000 and Beyond, Aug.28-30, 1991, New-Delhi.


  28. Y.H.Vasavada, P.M.Hatkanagalekar, S.S.S.P.Rao, "Hybrid Lock", PARCOM-90 Conference from Dec.10-11,1990 at CDAC-Pune


  29. Y.H.Vasavada, P.M.Hatkanagalekar, S.S.S.P.Rao, "On Consistency Issues in Parallel Algorithms", Workshop on Parallel Processing, Feb.7-9, 1990 at BARC-Bombay


  30. G.Venkatesh, Sandeep Pagey, S.S.S.P.Rao, "A Fast Design for Fault- Tolerant Hardware Clock Synchronisation", Joint Fault-Tolerant Computing Symposium JFTCS, July 18-20, 1989, Chongqing, Sichuan,China, pp.12-17.


  31. Aamod Sane, S.Manivannan, S.S.S.P.Rao, "An O.S.Kernel for Transputers compatible with MACH", Australian Tranputer and OCCAM User Group Conference & Exhibition, 5-7 July 1989, Melbourne, Australia


  32. Aamod Sane, Rao S.S.S.P., "Design of MACH like Implementation of the UNIX Kernel", Seminar on Parallel Processing Systems & Their Applications, Dec. 9-11, 1988, Calcutta India


  33. Ravi R.Pai, Karmarkar N., Rao S.S.S.P., "A Global Router for Gate Arrays using Karmarkar's Interior Point Integer Programming Method", 26th ACM/IEEE Design Automation Conference, 1989


  34. Ravi R Pai, Rao S.S.S.P., "A Channel Router based on Efficient Heuristics", VLSI DESIGN INDIA Conference, 15 - 18 December, 1988, Bangalore, (India)


  35. Hayatnagarkar, N.K., Rao S.S.S.P, "Pairwise Interchange Iterative Placement Improvement Algorithm VLSI DESIGN INDIA Conference, 15-18 December 1988, Bangalore, (India)


  36. Bhalerao,G .A., Rao, S.S.S.P, "HD 63484 Based CAD workstation", Proceedings of the International Conference on Computer Graphics'88,15 -16 September 1988, Singapore, PP.345-358. Also appeared in CSI Communication, No.123, November 1988, pp 11-14.


  37. Hayatnagarkar, N.K., Rao S.S.S.P, "Pairwise Interchange Iterative Placement Improvement Algorithm", VLSI DESIGN INDIA Conference, 15-18 December 1988, Bangalore, (India)


  38. K.Narayanan, Pramode Kumar, S.Ramani, S.S.S.P.Rao, Y.S.Upadhye, "Concept of Data Broad-cast by Satellite", Computer Communication for Developing Countries (CCDC-87) Conference, Oct.27-30, 1987, New Delhi


  39. S.D.Sherlekar, S.S.S.P.Rao, "Research report on the VLSI Design Centre established at various institutions & other organisations in India", Presented at IFIP TC 10.4 meeting held at Fort Auguada Hotel, Goa on 12th Feb. 1988


  40. Sanjay K.Jain, S.S.S.P.Rao, "Operating System for Multiprocessor with Local memories", Annual Symposium of Personal Computers in Science & Engg., BARC, Bombay, Feb.3-5, 1988, sponsored by DAE.


  41. A.K. Sharma, S.S.S.P.Rao, "Gate Array Router", ICTC(Integrated Circuit Technology Conference, Nihe Limerick,Ireland, Sep.15-17, 1986.


  42. Sudha Kolluri, S.S.S.P. Rao, "Automative Placer for Master Slice LSI's", ICTC(Integrated Circuit Technology Conference, Nihe Limerick, Ireland, Sep.15-17,1986.


  43. G. Anil Kumar, S.S.S.P. Rao, "Interactive Graphics Editors for Gate Array Based Designs", International Conference on Modelling & Simulation, Melbourne (Australia),Oct.14-16, 1987.


  44. Harrick M.Vin, R.B. Bhode, "Microprogrammed Graphic", International Conference on Vikram Sarabhai Space Centre, Trivandrum, India.


  45. M. Raghavan, P.V. Joshi, S.S.S.P. Rao, C. Amarnath and S.Ramani, "Design of Hydraulically powered manipulator", First National Seminar on Aerospace and Related mechanisms Aug. 22-23, 1985 (CCDC-87) Conference, India.


  46. A.S. Baheti, S. Mahapatra, S.S.S.P. Rao, "New approach for design of beam steering unit of Radar", INFORMATICS 85 International Conference on Informatics, Trivandrum, India, Sep.2-4, 1985.


  47. S.S.S.P. Rao, J.M. Apte, A.N. Chandorkar, P.S. Subramaniam, "Hierarchical gate array router", Workshop on Review of State of the Art in CAD for LSI/VLSI, Chandigarh, April 5-7. 1985.


  48. S.S.S.P. Rao, A.S. Adke, A.N. Chandorkar, P.S. Subramaniam, "Placement and user interface for a gate array design system", Workshop on Review of State of the Art in in CAD for LSI/VLSI, Chandigarh April 5-7, 1985.


  49. S.S.S.P. Rao, A.C. Shelat, Ashish Khosla, "MC 6809/MC 6845 based graphics terminal", CSI-83 Proceedings, Vol.1, Computer Architecture Hardware and Systems, Jan.19-22, 1983, PP.A1.01.01-A1.01.07.


  50. S.S.S.P.Rao, V. Ramesh, "MICROLL : A hardware Description language", CSI-83 Proceedings, Vol.1, Computer Architecture Hardware and Systems, Jan. 19-22, 1983, PP.D1.01.01-d1.01.12.


  51. S.S.S.P. Rao, M.B. Durgad, A.S. Mankar, "A general purpose hybrid interface for the mini computer HP 2100 A", IMACS, 10th World congress on system simulation and Scientific computation, Aug.8-13,1982, Montreal, Canada Proceedings,Vol.5, 43-48.


  52. S.S.S.P. Rao H.G. Ratithor, "A smart instrument for electric power measurement", CSI-82 Proceedings, Vol.1, Hardware and Systems, 1982. PP.1.18-1.27.


  53. S.S.S.P.Rao, "Microprocessor and interfacing(invited paper)", CSI-82 Proceedings, (Invited paper) PP.42-51.


  54. S.S.S.P.Rao, V.K. Agarwal, "A microprocessor based tea dryer controller : An interface design", CSI-82 Proceedings, Vol.1, Hardware and Systems, 1982 PP.1.1-1.27.


  55. S.S.S.P.Rao, A.C.Shelat, "Microcomputer development support: A simulator for the M6800", Proceedings of the International confer- ence on the micro- processor applications to industrial control ICMATIC-81,Feb.14-16 1981,Jadavpur Univ. Calcutta.


  56. S.S.S.P.Rao, K. Ramesh, "EC-1030 microdiagnos- tics : Analysis and extensions," CSI-81 Proceedings, Division I(Computer Architecture Hardware and Systems)March 1-4 1981, PP.104-111.


  57. S.S.S.P.Rao, B.S.Rao, " A microprocessor based device controller for EC-1030 magnetic tape drives", CSI-81 Proceedings, Division I(Computer Architecture Hardware and Systems)March 1-4 1981, PP.112-118


  58. S.S.S.P.Rao, L.S.Radhakrishnan, "Performance monitoring of the EC-1030 system by a microprocessor based monitor", Eleventh international symposium on Mini and Micro computers MINI 80 ASILOMAR, Jan.29- Feb.1, 1980,Pacific Grove, California.


  59. S.S.S.P.Rao, Sanjay Iyer, Babuji, "Design of a 256KB semiconductor primary memory for the EC-1030", Proceedings of the CSI- 80, 15th Annual Convention of the Computer Society of India, Feb.8-11,1980.


  60. S.S.S.P.Rao, Srinivasan,S.A, "MIPEC-A microprocessor based standard I/O interface simulator for the EC-1030 peripehrals", Proceedings of the CSI- 80, 15th Annual Convention of the Computer Society of India, Feb.8-11,'80


  61. S.S.S.P.Rao, Gautam Barua, "Fault location,fault tolerance and diagnos- ability : Selected implementations on the EC-1030 processor", Proceedings of the first Internatinal Conference on Reliabi- lity and Exploitation of computer systems 'RELCOMEX 1979',Sep. 25-29 '79,Wroclaw, Poland,PP.171-180.


  62. S.S.S.P.Rao, D.A. Bhide, "A writable control store for the HP2100A", Proceedings of the Symposium on Mini and Microcomputers and automation, Roorkee (India) March 29-30,'79, PP.5.37-5.54.


  63. S.S.S.P.Rao, Gautam Barua, S.A.Srinivasan, "EC-1030 system performance evaluation by a microprocessor based monitor", Proceedings of the 5th Annual Conference on Industrial and Control Applications of Microprocessors IECI 1979, Philadelphia,Pa.


  64. S.S.S.P.Rao, Gautam Barua, "Fault tolerant techniniques : An implementation on EC-1030", Proceedings of the CSI 79 Convention