# # Copyright (C) 2009-2012 Chris McClelland # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU Lesser General Public License as published by # the Free Software Foundation, either version 3 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public License # along with this program. If not, see . # # Modified for use in CS254 Lab experiments #=============================================================================== # USB interface #=============================================================================== NET "fx2Clk_in" LOC="C10" | IOSTANDARD=LVTTL; # IFCLK NET "fx2Addr_out<0>" LOC="A14" | IOSTANDARD=LVTTL; # PA4/FIFOADR0 NET "fx2Addr_out<1>" LOC="B14" | IOSTANDARD=LVTTL; # PA5/FIFOADR1 NET "fx2Data_io<0>" LOC="A2" | IOSTANDARD=LVTTL; # PB0/FD0 NET "fx2Data_io<1>" LOC="D6" | IOSTANDARD=LVTTL; # PB1/FD1 NET "fx2Data_io<2>" LOC="C6" | IOSTANDARD=LVTTL; # PB2/FD2 NET "fx2Data_io<3>" LOC="B3" | IOSTANDARD=LVTTL; # PB3/FD3 NET "fx2Data_io<4>" LOC="A3" | IOSTANDARD=LVTTL; # PB4/FD4 NET "fx2Data_io<5>" LOC="B4" | IOSTANDARD=LVTTL; # PB5/FD5 NET "fx2Data_io<6>" LOC="A4" | IOSTANDARD=LVTTL; # PB6/FD6 NET "fx2Data_io<7>" LOC="C5" | IOSTANDARD=LVTTL; # PB7/FD7 NET "fx2Read_out" LOC="F13" | IOSTANDARD=LVTTL; # RDY0/SLRD NET "fx2OE_out" LOC="A15" | IOSTANDARD=LVTTL; # PA2/SLOE NET "fx2GotData_in" LOC="C15" | IOSTANDARD=LVTTL; # CTL2/FLAGC NET "fx2Write_out" LOC="E13" | IOSTANDARD=LVTTL; # RDY1/SLWR NET "fx2GotRoom_in" LOC="A9" | IOSTANDARD=LVTTL; # CTL1/FLAGB NET "fx2PktEnd_out" LOC="C4" | IOSTANDARD=LVTTL; # PA6/PKTEND #=============================================================================== # On-board peripheral signals #=============================================================================== NET "led_out<0>" LOC="U18" | IOSTANDARD=LVTTL; NET "led_out<1>" LOC="M14" | IOSTANDARD=LVTTL; NET "led_out<2>" LOC="N14" | IOSTANDARD=LVTTL; NET "led_out<3>" LOC="L14" | IOSTANDARD=LVTTL; NET "led_out<4>" LOC="M13" | IOSTANDARD=LVTTL; NET "led_out<5>" LOC="D4" | IOSTANDARD=LVTTL; NET "led_out<6>" LOC="P16" | IOSTANDARD=LVTTL; NET "led_out<7>" LOC="N12" | IOSTANDARD=LVTTL; # up push button for reset NET "reset" LOC = "N4"; # Bank = 3, Pin name = IO_L1P, Sch name = BTNU # left push button for start NET "start" LOC = "P4"; # Bank = 3, Pin name = IO_L2P, Sch name = BTNL # down push button for next_data_in NET "next_data_in" LOC = "P3"; # Bank = 3, Pin name = IO_L2N, Sch name = BTND # right push button for done NET "done" LOC = "F6"; # Bank = 3, Pin name = IO_L55P_M3A13, Sch name = BTNR NET "sw_in<0>" LOC="A10" | IOSTANDARD=LVTTL; # SW0 NET "sw_in<1>" LOC="D14" | IOSTANDARD=LVTTL; # SW1 NET "sw_in<2>" LOC="C14" | IOSTANDARD=LVTTL; # SW2 NET "sw_in<3>" LOC="P15" | IOSTANDARD=LVTTL; # SW3 NET "sw_in<4>" LOC="P12" | IOSTANDARD=LVTTL; # SW4 NET "sw_in<5>" LOC="R5" | IOSTANDARD=LVTTL; # SW5 NET "sw_in<6>" LOC="T5" | IOSTANDARD=LVTTL; # SW6 NET "sw_in<7>" LOC="E4" | IOSTANDARD=LVTTL; # SW7 #=============================================================================== # Timing constraint of FX2 48MHz clock "fx2Clk_in" #=============================================================================== NET "fx2Clk_in" TNM_NET = "fx2Clk_in"; TIMESPEC "TS_clk" = PERIOD "fx2Clk_in" 20 ns HIGH 50 %;