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Talks & Seminars
Title: Automated verification/synthesis of concurrent programs
Dr. Ashutosh Gupta, Tata Institute of Fundamental Research, Mumbai
Date & Time: May 9, 2017 11:00
Venue: Conference Room, C Block, 01st Floor, Dept. of CSE, Kanwal Rekhi (KReSIT) Bldg.
Abstract:
Concurrent programs are running in all of our devices. The programs are notoriously difficult to get right, because it is hard to comprehend all possible interplay among processes. For the same reason, automating the verification/synthesis of the programs is also particularly hard. Most analysis methods attempt to efficiently recognize and represent the interplay, and subsequently use it for verification/synthesis. In this talk, I will present a series of methods and tools that follow the theme and solve the problem for sub-classes for concurrent programs, e.g., mutual exclusion protocols, concurrent data structures, and programs under weak memory. The talk will also include a demo of a tool called TARA[1] that computes summaries of the interplay of processes. [1]https://github.com/ashutosh0gupta/TARA
Speaker Profile:
Information about him is available at: http://www.tcs.tifr.res.in/~agupta/
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