Talks & Seminars
Title: Architecting Persistent Memory Systems: A Performance Perspective
Mr. Arpit Joshi, University of Edinburgh
Date & Time: December 18, 2017 14:30
Venue: Conference Room, 01st Floor, C Block, Department of Computer Science and Engineering, Kanwal Rekhi (KReSIT) Building
The long stated vision of persistent memory is set to be realized with the impending release of 3D XPoint memory by Intel and Micron. Persistent memory, as the name suggests, amalgamates the persistence (non-volatility) property of storage devices (like disks) with byte-addressability and low latency of memory. These properties of persistent memory coupled with its accessibility through the processor load/store interface enable programmers to design in-memory persistent data structures. An important challenge in designing persistent memory systems is maintaining crash consistency of these in-memory data structures. Crash consistency is necessary to ensure the correct recovery of program state after a crash. Ordering and atomic durability are two primitives that can be used to design crash consistent programs. In this talk we will look at efficient implementations of ordering and atomic durability primitives. First, we will analyze an existing implementation of persist barrier (an ordering primitive) and see how it performs cache line writebacks to persistent memory in the critical path of execution. We will then look at an efficient primitive that limits and in some cases eliminates these cache line writebacks happening in the critical path. Next, we will analyze implementations of write-ahead logging (WAL) which is a commonly used approach to provide atomic durability. We will first argue that existing implementations of WAL in software are not only inefficient, because of the fine grained ordering dependencies, but also waste precious execution cycles to implement a fundamentally data movement task. We will then look at ATOM, a hardware log manager based on undo logging that performs the logging operation out of the critical path. We will see how ATOM, by enforcing ordering constraints and in some cases by performing logging at the memory controller, reduses processor stall cycles and improves performance.
Speaker Profile:
Arpit Joshi is a Research Associate in the School of Informatics at the University of Edinburgh. He is broadly interested in the field of Computer Architecture and his recent research is focussed around providing architectural support for systems with persistent (non-volatile) memory. In the past he was a Design Engineer at Intel, where he worked on the design and development of a family of server class processors. He also has a masters degree from IIT Madras, where he investigated designs for low power on-chip interconnection networks.
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