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Talks & Seminars
An Efficient Technology Mapping Algorithm Targetting Routing Congestion Under Delay Constraints
Dr. Rupesh Shelar, Intel Corporation, Hillsboro, Oregon
Date & Time: June 9, 2006 15:30
Venue: EE Conference Room
Abstract:

Routing congestion has become a serious concern in today's VLSI designs. To address the same, we propose a technology mapping algorithm that minimizes routing congestion under delay constraints. The algorithm employs a dynamic programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delay-optimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100 nm technology show that the algorithm can improve track overflows significantly as compared to conventional technology mapping while satisfying delay constraints.

Speaker Profile:

Rupesh S. Shelar received the B.E. degree in instrumentation engineering from the Marathwada University, Aurangabad, India in 1997, the M.Tech. degree in electrical engineering with specialization in microelectronics from the Indian Institute of Technology, Mumbai, India in 1999, and the Ph.D. degree in electrical engineering from the University of Minnesota, Minneapolis, USA in 2004.

From March 1999 to May 2000, he was a software engineer with Silicon Automation Systems, India. He spent the summers of 2002 and 2003 at Strategic CAD Labs, Intel researching congestion-aware logic synthesis. Since June 2004, he is a senior component design engineer in the Enterprise Microprocessor Group at Intel, where he has evaluated various noise avoidance and fixing flows for 65 nm Pentium 4 design. More recently, he is responsible for clock tree synthesis for the random logic in the next generation low power microprocessor. He is the author or co-author of 12 papers in refereed journals and conferences. His research interests include logic/physical synthesis and physical design.

Dr. Shelar has served as a reviewer for journals such as IEEE Transactions on Computer-Aided Design, IEEE Transactions on Very Large Scale Integration, ACM Transactions on Design Automation of Electronic Systems, and for various conferences.

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