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Talks & Seminars
Symmetry Reduction for STE (Symbolic Trajectory Evaluation) Model Checking
Dr. Ashish Darbari, University of Southampton
Date & Time: January 10, 2007 16:00
Venue: CFDVS Conference Room (basement of Maths Bldg)
Abstract:
Symbolic Trajectory Evaluation or STE in short, has been widely used in several large scale verification tasks. In spite of the tremendous success of STE model checking one cannot verify circuits with arbitrary large number of state holding elements. In this talk we will present a methodology of symmetry reduction for STE model checking that enables a significant reduction in the complexity of verification of several large circuit designs that have symmetry, for example SRAMs, CAMs and caches.
Speaker Profile:
Dr. Ashish Darbari works as a Post Doctoral Research Fellow at the Electronics and Computer Science Department at University of Southampton. He has recently completed his Doctorate in Computer Science at Oxford University. His recent research has been in the area of formal hardware verification. He is keenly interested in applications of formal techniques for the analysis and design of modern control systems, including digital hardware and software. In his current research is looking into reliability issues for DVS processors.
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