Talks & Seminars
Title: Temporal Logics for Verification: What is the complexity?
Prof. Kamal Lodaya, The Institute of Mathematial Sciences, Chennai
Date & Time: November 21, 2008 16:00
Venue: Conference Room, ā€˜Cā€™ Block, 01st floor, Kanwal Rekhi Bldg.
Verification of a system using model checking is an application of automata theory developed in the 1980s. Properties of the system which are to be verified are specified in a variety of temporal logics: CTL, LTL, ITL, our-TL, your-TL... Why are there so many of them? This talk surveys complexity results among different temporal logics, and then presents yet another temporal logic UITL, which we introduced with P. K. Pandya and S. S. Shah (TIFR) earlier this year.
Speaker Profile:
Details about the speark is available at http://www.imsc.res.in/~kamal/ or http://www.imsc.res.in/tcsweb/faculty/kamal.htm
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