Talks & Seminars
Title: Symbolic Simulation Based Transient Fault Injection
Dr. Ashish Darbari, University of Southampton, UK
Date & Time: March 5, 2009 16:00
Venue: Conference Room, 01st floor, ‘C’ Block, Kanwal Rekhi Building

Traditionally, fault injection has been carried out by instrumenting the RTL in a controlled manner to incorporate fault injection, and evaluating the behaviour of the faulty RTL whilst running some benchmark programs. This approach has two main limitations:

1. It relies on checking the effects of faults in the design whilst it is executing a specific binary image, and therefore the true impact of the fault is limited by the shadow of the program image.

2. The use of extra hardware for fault injection which is not needed during the fault-free running of the design.

In this talk, I will present a new methodology for transient fault injection based on symbolic simulation and model checking, that circumvents the problems outlined in (1) and (2) above. I’ll also show some of the results of using our approach on transient fault injection in a 32-bit multi-cycle RISC processor.

We exploit the specification and verification capabilities of STE to develop properties that capture transient faults in the circuit, and then verify these against a golden RTL -- one that has been formally verified by us in a fault-free scenario. The benefit of injecting faults in the properties, rather than the model, enables one to check for faults efficiently during model checking, since we have fewer symbolic variables to deal with.

Our approach can be applied generally to any faulty design, not necessarily a processor, and is an efficient method to analyse the effect of transient faults since it does not rely on costly, and yet incomplete simulation, and modification of the RTL.

Speaker Profile:
Details about the speaker is available at http://www.ecs.soton.ac.uk/people/ad06v
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