Talks & Seminars
Title: The Case for Parameter Variation Aware Processors
Dr. Smruti R. Sarangi, IBM Research Labs, Bangalore
Date & Time: August 10, 2010 14:00
Venue: Conference Room, 01st floor, ā€˜Cā€™ Block, Kanwal Rekhi Bldg.
Parameter variation in integrated circuits causes sections of a chip to be slower and more power consuming than others. "Parameter Variation" is defined as the unpredictability in transistor dimensions, supply voltage (due to IR drops), and temperature. If, to prevent any resulting timing errors we design processors for worst-case parameter values, we may lose substantial performance. An alternate approach explored in this work is to design for closer to nominal values, and provide some transistor budget to tolerate unavoidable variation induced errors. To assess this approach, this work first presents a novel framework that shows how micro-architecture techniques can trade off variation-induced errors for power and processor frequency. Then, we introduce an effective technique to maximize performance and minimize power in the presence of variation induced errors, namely High-Dimensional dynamic adaptation. For efficiency, the technique is implemented using a machine learning algorithm. The results show that our best configuration increases processor frequency by 56% on average, allowing the processor to cycle 21% faster than without variation. Processor performance increases by 40% on average, resulting in a performance that is 14% higher than without variation ā€” at only a 10.6% area cost.
Speaker Profile:
Smruti R. Sarangi is currently working in IBM Research Labs, Bangalore, in the Next Generation Systems group. Prior to this, he has briefly worked in Synopsys Research. He gradated with a Ph.D in computer architecture from UIUC (University of Illinois at Urbana-Champaign) in 2007, and with a B.Tech in CSE from IIT Kharagpur in 2002.
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