Talks & Seminars
Title: Scalable Support for Data Sharing on Multi-Core Platforms
Prof. Sandhya Dwarkadas, University of Rochester
Date & Time: April 15, 2011 11:30
Venue: Lecture Hall, B Block, Third Floor, Kanwal Rekhi Building
Technology projections indicate the possibility of 50 billion transistors on a chip in a few years, with the processor landscape being dominated by multi-core designs. Providing protected and controlled sharing across cores, while at the same time addressing performance isolation issues, remains a growing challenge. In this talk, I will describe our changes to existing coherence mechanisms in order to scale data sharing support and to improve the efficiency of fine-grain sharing. As time permits, I will also describe our work in developing mechanisms for data isolation and memory access control. Finally, I will introduce the problem of performance isolation and show how it can be effectively addressed at the operating system level.
Speaker Profile:
Sandhya Dwarkadas is currently a Professor of Computer Science at the University of Rochester, with a secondary appointment in Electrical and Computer Engineering. She received her Bachelor's from the Indian Institute of Technology, Madras, India, in 1986, and her M.S. and Ph.D. from Rice University in 1989 and 1993, respectively. Her research lies at the interface of hardware and software with a particular focus on concurrency, resulting in over 90 refereed publications that cross areas within systems. Past projects include complexity-adaptive processing (CAP), multiple clock domain (MCD) architectures, dynamically tunable clustered multithreading (DT-CMT), locality-aware dynamic load balancing in a cluster of workstation environment (LADLE), and support for shared state in distributed and clustered environments (InterWeave, Cashmere, TreadMarks). Recent projects include hardware support for transactional memory (FlexTM, RTM), on-chip cache design (DDCache, ARMCO, SPACE), and operating system-level resource management for multi-core processors. She is also co-inventor on 7 granted U.S. patents, and is currently associate editor for IEEE Computer Architecture Letters and for IEEE Micro. URL: http://www.cs.rochester.edu/u/sandhya
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