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Talks & Seminars
Title: Performance Density Exploration of Heterogeneous Multicore Architectures
Dr. Surendra Guntur, NXP Semiconductors, Netherlands
Date & Time: October 5, 2011 11:30
Venue: Lecture Hall, 03rd floor, B Block, Dept. of CSE, Kanwal Rekhi Bldg.
Abstract:
Multicore architectures provide scalable performance with a modest extra hardware design effort compared to single core processors. This talk presents a design methodology and an embedded multicore architecture focusing on boosting the performance density and reducing software design complexity. Compared to a single processor core, the multicores have already proven to be more area-and energy-efficient. However, the multicore architectures in embedded systems still compete with highly efficient function-specific hardware accelerators. Five architectural methods to boost performance density of multicores are considered - microarchitectural downscaling, asymmetric multicore architectures, multithreading, generic accelerators, and conjoining. A novel methodology to explore multicore design space is presented and the impact of the above mentioned architectural optimizations on performance density is evaluated. The methodology is based on a predictive formula computing performance of heterogeneous multicores, which allows drastic pruning of the design space for few accurate simulations. Using this design space exploration methodology for HD and QuadHD H.264 video decoding, it is estimated that the required areas of multicores in CMOS 45 nm are 2.5 mm2 and 8.6 mm2, respectively. These results suggest that heterogeneous multicores are cost-effective for embedded applications and can provide good programmability support.
Speaker Profile:
Surendra Guntur works as a senior scientist in the Modem signal processing group (formerly systems and architectures group) at NXP Semiconductors, Eindhoven, The Netherlands. His broad research interests include computer architecture, power/performance analysis and simulation, rapid prototyping and low power design of general purpose as well as domain specific processors and hardware. He received his bachelor’s degree in electronics and communication engineering from the National Institute of Engineering, Mysore, India, and masters and PhD degree from SERC, Indian Institute of Science (IISc), Bangalore, India.
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