Talks & Seminars
Title: Use of Emerging Technologies in the Design of Low Power Processor Architectures
Mr. Karthik Swaminathan, Pennsylvania State University
Date & Time: January 20, 2012 15:00
Venue: Conference Room, 01st Floor, C Block, Dept. of Computer Science & Engg., Kanwal Rekhi Building
As technology scaling results in smaller and smaller transistor sizes, the total area occupied by each core in a processor also reduces. Consequently, a larger number of cores can be fitted into a single chip. However, due to thermal constraints, the power deliverable to the chip has remained relatively constant. As a result, the gap between the number of cores that can be accommodated on a chip and the actual number of cores that can be powered continues to widen. Conventional CMOS technology based processors may not be able to operate optimally under such conditions. This talk primarily focuses on adopting emerging technologies (such as the Tunnel FET) in future processor architectures to mitigate this problem. It describes the techniques used to model a TFET-based processor and highlights its performance and power benefits over a conventional CMOS-based processor. It also explores the feasibility of using TFET-based cores in conjunction with conventional CMOS cores and examines optimal application scheduling schemes for the same. Finally, it examines methods to extract the maximum possible application performance under a fixed power constraint.
Speaker Profile:
Karthik Swaminathan is a Ph.D student with Prof. Vijay Narayanan in the Department of Computer Science and Engineering at the Pennsylvania State University. His research is primarily focused on power aware computer architectures. He is currently working on leveraging emerging device technologies in the architectural domain to improve performance, power and reliability. He graduated from the Indian Institute of Technology, Madras with a Dual Degree (Bachelors and Masters) in Electrical Engineering. He also worked for a year at IBM India Research Labs, New Delhi as a member of the High Performance Computing Group.
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