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Talks & Seminars
Title: Understanding the Correctness Requirements of Software Transactional Memory Systems
Dr. Sathya Peri, IIT Hyderabad
Date & Time: December 9, 2015 15:00
Venue: Conference Room, 01st Floor, Department of Computer Science and Engineering, Kanwal Rekhi (KReSIT) Building
Abstract:
Over the last few decades, much of the gain in software performance can be attributed to increases in CPU clock frequencies. However around 2004, 50 years of exponential improvement in the performance of sequential computers ended. Industry’s response to these changes was to introduce single-chip, parallel computers, variously known as “chip multiprocessors,” “multicore,” or “manycore” computers. In order to get a continued speedup on these processors, applications need to be able to harness the parallelism of the underlying hardware. This is commonly achieved using multi-threading. Yet writing correct and scalable multi-threaded programs is far from trivial. In multi-threaded programs sets of semantically related actions may need to execute in mutual exclusion to avoid semantic inconsistencies. Traditionally, multi-threaded programs were developed in conjunction with locks to address these issues. But programming with locks has many disadvantages such as deadlocks, priority inversion etc. and makes it difficult to build scalable software systems. Importantly, lock based software components are difficult to compose i.e. build larger software systems using simpler software components. In recent years, Software Transactional Memory (STM) has garnered significant interest as an elegant alternative for developing concurrent code. Software transactions address many of the shortcomings of lock based systems. Multi-threaded programs used with STMs address many of these challenges. In this talk, I will give an overview of of Software Transactional Memory (STMs). I will describe the correctness requirements of STM systems, describe its current state of research and some open issues.
Speaker Profile:
Dr. Sathya Peri is currently an Assistant Professor in CSE Department of IIT-Hyderabad. Prior to this, he was an Assistant Professor in the Computer Science at IIT Patna from June 2010 to May 2014. During his stay at IIT Patna, he was a recipient of DAAD Faculty fellowship; a visiting researcher at TIFR. Dr. Sathya Peri has research collaboration with Govt. Funding agencies as well as Industries. He was a recipient of NetApp Faculty Fellowship and an unrestricted research grant from Microsoft Research Bangalore. Dr. Sathya Peri received Master of Computer Science and Applications in Computer Science from Madurai Kamaraj University, India in 2001. After working as a software engineer at HCL Technologies, India for one year he joined University of Texas at Dallas as a graduate student. He obtained Masters degree and Ph.D. degrees in Computer Science from the University of Texas at Dallas in 2004 and 2007 respectively. He worked under the guidance of Prof. Neeraj Mittal in the area of monitoring distributed systems. Then he worked at INRIA, Rennes, France as a postdoc from Sept 2007 to Dec 2008 in the area of Gossip Protocols for Peer to Peer systems. From Jan 2009 to Apr 2010, he was a Postdoc at Memorial University working with Prof. Vidyasankar in the area of Software Transactional Memory.
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