Talks & Seminars
Formal modeling of System-on-Chip Communication Architectures
Vijay D'Silva,
Date & Time: October 27, 2003 16:00
Venue: Seminar Hall
Abstract: System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often have different communication protocols. The task of designing wrappers and bridges to resolve such protocol mismatches is called interface synthesis. We have developed a framework for modelling such communication architectures based on the theory of synchronous languages. We have formalised the notion of protocol compatibility which can also be used as a correctness criterion for interface synthesis algorithms. I will demonstrate how this framework can be used for modelling and checking compatibility of synchronous protocols. I will also present an interface synthesis algorithm we have derived from this framework. It applies to a much larger class of protocols than existing algorithms and can generates provably correct solutions. We have modelled and synthesised interfaces for bus architectures which are commonly used by chip designers such as the AMBA from ARM and IBM's CoreConnect.
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