Talks & Seminars
Title: Breaking the Memory Wall in Multi-Core Systems through Prefetch and Compression Engines
Dr. Biswabandan Panda, INRIA, Rennes
Date & Time: September 29, 2016 11:30
Venue: Conference Room, C Block, 01st Floor, Department of Computer Science and Engineering, Kanwal Rekhi (KReSIT) Building
Historically, the rate of improvement in memory speed is lower than the improvement in processor speed, which creates a gap between processor speed and memory speed. This inevitably leads to the “memory wall” where processor cores’ pipelines stall, waiting for memory accesses. Moreover, the advent of multi-core systems in recent years, exacerbates the memory wall as multiple applications contend with each other for shared resources such as off-chip bandwidth. This talk will cover two hardware techniques in the form of prefetch engines and cache compression engines that try to break the memory wall. Prefetch engines speculatively bring data into the cache, converting cache misses into cache hits. Cache compression engines also increase the cache hit ratio by storing more data in less bytes, increasing the effective cache capacity. The talk will provide a brief introduction on prefetch engines (especially aggressiveness engines) and cache compressors followed by a detailed description of my recent research work, such as synergistic prefetcher aggressiveness controller and dictionary sharing based cache compression.
Speaker Profile:
Biswabandan Panda is a post-doctoral researcher at the PACAP team of INRIA, Rennes. He received his Ph.D. from Indian Institute of Technology Madras, where he was a recipient of TCS Ph.D. fellowship. His area of research includes hardware prefetching, cache/DRAM Compression, and memory sub-system management for multi-core systems.
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