Serial Line IP Implementation for Linux Kernel TCP/IP Stack | ||
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The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes.
Serial transmission is commonly used with modems and for non-networked communication between computers, terminals and other devices.There are two primary forms of serial transmission: Synchronous and Asynchronous.
Asynchronous Serial Transmission
Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. Instead, the sender and receiver must agree on timing parameters in advance and special bits are added to each word which are used to synchronize the sending and receiving units.
When a word is given to the UART for Asynchronous transmissions, a bit called the "Start Bit" is added to the beginning of each word that is to be transmitted. The Start Bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter. These two clocks must be accurate enough to not have the frequency drift by more than 10% during the transmission of the remaining bits in the word. After the Start Bit, the individual bits of the word of data are sent, with the Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly the same amount of time as all of the other bits, and the receiver ``looks'' at the wire at approximately halfway through the period assigned to each bit to determine if the bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the receiver will examine the signal to determine if it is a 1 or a 0 after one second has passed, then it will wait two seconds and then examine the value of the next bit, and so on.
The sender does not know when the receiver has ``looked'' at the value of the bit. The sender only knows when the clock says to begin transmitting the next bit of the word.
When the entire data word has been sent, the transmitter may add a Parity Bit that the transmitter generates. The Parity Bit may be used by the receiver to perform simple error checking. Then at least one Stop Bit is sent by the transmitter.
When the receiver has received all of the bits in the data word, it may check for the Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is supposed to, the UART considers the entire word to be garbled and will report a Framing Error to the host processor when the data word is read. The usual cause of a Framing Error is that the sender and receiver clocks were not running at the same speed, or that the signal was interrupted.
Regardless of whether the data was received correctly or not, the UART automatically discards the Start, Parity and Stop bits. If the sender and receiver are configured identically, these bits are not passed to the host. If another word is ready for transmission, the Start Bit for the new word can be sent as soon as the Stop Bit for the previous word has been sent. Because asynchronous data is ``self synchronizing'', if there is no data to transmit, the transmission line can be idle.
Baud is a measurement of transmission speed in asynchronous communication. Traditionally, a Baud Rate represents the number of bits that are actually being sent over the media, not the amount of data that is actually moved from one DTE device to the other. The Baud count includes the overhead bits Start, Stop and Parity that are generated by the sending UART and removed by the receiving UART. This means that seven-bit words of data actually take 10 bits to be completely transmitted. Therefore, a modem capable of moving 300 bits per second from one place to another can normally only move 30 7-bit words if Parity is used and one Start and Stop bit are present.
If 8-bit data words are used and Parity bits are also used, the data rate falls to 27.27 words per second, because it now takes 11 bits to send the eight-bit words, and the modem still only sends 300 bits per second.
The base address of the UARTs and thus also of the registers are stored in the BIOS data area.
Interface Base Address IRQ
COM1 3f8h IRQ4
COM2 2f8h IRQ3
DLAB stands for Divisor Latch Access Bit. When DLAB is set to '1' via the line control register, two registers become available from which you can set your speed of communications measured in bits per second.
Baud rate is calculated as
Baud rate = Main reference frequency/(16*divisor)
The UART 8259/16459/16550 comes in a standard DIP case with 40 pins.The registers of UART are given below.
Receiver Buffer Register: It is used to store the data byte received. It's offset is 0(DLAB=0). The data in this register can be accessed by input functions.
Transmitter Hold Register: If we want to write a byte to Transmitter Hold Register, it is automatically transferred to transmitter shift register and output as a serial data stream. It's offset is 0(DLAB=0).
Interrupt Enable Register: The Interrupt Enable Register controls the interrupt request. The high order nibble register is always equal to zero. It can not be altered. The first bit of Interrupt Enable Register is for interrupting when a data byte is received. If a data byte is received at the Receiver Buffer Register an interrupt is raised. Similarly the second bit of this register is fot interrupting on Transmitter Buffer empty.
Interrupt Identification Register: With the Interrupt Identification Register, we can detirmine whether an interrupt is currently pending or not. An active interrupt is indicated by a cleare pending bit. This is especially useful when polling is used for the interface concern.
Data Format Register: The eighth bit(DLAB bit) of Data Format Register is Divisor Latch Access bit. If it is set, we can access the Divisor Latch Registers. If it is not set, we can access the receiver or transmitter register. Data Format Register is used to define a data byte. It can be done in several ways. For example it can be like 8-data bit, 1-stop bit and no parity. Other the combinations can be generated by altering the values in the Data Format Register. It's offset is 3.
Divisor Latch Registers: There are two Divisor Latch Registers: Low order Divisor Latch Register and High Order Divisor Latch Register. This Divisor Latch Registers are used to set the baud rate of the transmission. It's offset is 0 and 1(DLAB=1).
Modem Control Register: Modem Control Register supervises the UART modem control logic. The three most significant bits are not used. A reading access always returns a value zero. By setting the loop bit we can enable the feedback loop check of UART. It's offset is 4.
Modem Status Register: Using the Modem Status Register, we can detirmine the status of the RS-232 input signals. It's offset is 6.
Serialization Status Register: This register is used to detirmine whether a data byte is available in the Receiver Buffer Register or whether the Transmitter Buffer is empty. If the TXE bit is zero, then data is still present either in the Transmitter Hold Register or in the Transmitter Shift Register. If the TBE bit is set, then the Transmitter Hold Register is empty, otherwise a data byte is being held there. It's offset is 5.
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