MOV TO A REGISTER 
Gen MOV  R1, R2 moves R2 to R1
Flags are Unchanged 
------------------------------
7F   MOV A,A
78   MOV A,B             
79   MOV A,C       
7A   MOV A,D
7B   MOV A,E
7C   MOV A,H
7D   MOV A,L
7E   MOV A,M

MOV TO B REGISTER
Gen MOV  R1, R2 moves R2 to R1
Flags are Unchanged 
------------------------------
47   MOB B,A
40   MOV B,B
41   MOV B,C
42   MOV B,D
43   MOV B,E
44   MOV B,H
45   MOV B,L
46   MOV B,M

MOV TO C REGISTER
Gen MOV  R1, R2 moves R2 to R1
Flags not affected
------------------------------
4F   MOV C,A
48   MOV C,B
49   MOV C,C
4A   MOV C,D
4B   MOV C,E
4C   MOV C,H
4D   MOV C,L
4E   MOV C,M

MOV TO D REGISTER
Gen MOV  R1, R2 moves R2 to R1
Flags not afffected
------------------------------
57   MOV D,A
50   MOV D,B
51   MOV D,C
52   MOV D,D
53   MOV D,E
54   MOV D,H
55   MOV D,L
56   MOV D,M

MOV TO E REGISTER
Gen MOV  R1, R2 moves R2 to R1
Flags not affftected
------------------------------
5F   MOV E,A
58   MOV E,B
59   MOV E,C
5A   MOV E,D
5B   MOV E,E
5C   MOV E,H
5D   MOV E,L
5E   MOV E,M
MOV TO H REGISTER
Gen MOV  R1, R2 moves R2 to R1
Flags not afffected
------------------------------
67   MOV H,A
60   MOV H,B
61   MOV H,C
62   MOV H,D
63   MOV H,E
64   MOV H,H
65   MOV H,L
66   MOV H,M

MOV TO L REGISTER
Gen MOV  R1, R2 moves R2 to R1
Flags not afffected
-----------------------------
6F  MOV L,A
68   MOV L,B
69   MOV L,C
6A   MOV L,D
6B   MOV L,E
6C   MOV L,H
6D   MOV L,L
6E   MOV L,M

MOV TO MEMORY
Moves register to Memory
location pinted by HL
No Flags are affected
----------------------------
77   MOV M,A
70   MOV M,B
71   MOV M,C
72   MOV M,D
73   MOV M,E
74   MOV M,H
75   MOV M,L

MOVE IMMEDIATE
Moves the Immediate
1 byte to Register
-------------------------------
3E   MVI A,data
06   MVI B,data
0E   MVI C,data
16   MVI D,data
1E   MVI E,data
26   MVI H,data
2E   MVI L,data
36   MVI M,data

MOVE IMMEDIATE 2 BYTES
Move immediate 2 byte date
B <= HOB, C<= LOB
______________________
OPCODE|  LOB |  HOB   |
-----------------------

01   LXI  B
11   LXI  D
21   LXI  H
31   LXI  SP

LOAD/STORE INDIRECT
Load Register pair Indirect
LoadsA register with a location
pointed by the register pair
---------------------------------
0A   LDAX B
1A   LDAX D
02   STAX B
12   STAX D

LOAD/STORE DIRECT
No flags affected
Addr is a 16 bit direct address

22   SHLD addr stores HL Memory
2A   LHLD addr load HL from memory

3A   LDA  addr loads a from memory
32   STA  addr stores A in to Memory

ADD REGISTER
Adds the Reg to A register
with Cin =0
ALL flags affected
-----------------------------
87   ADD A
80   ADD B
81   ADD C
82   ADD D
83   ADD E
84   ADD H
85   ADD L
86   ADD M

ADD REGISTER WITH CARRY
add REG TO a REGISTER WITH cin=CY
-----------------------
8F   ADC A
88   ADC B
89   ADC C
8A   ADC D
8B   ADC E
8C   ADC H
8D   ADC L
8E   ADC M

SUBTRACT INSTRUCTIONS
UBtract reg from A
with borrowin =0
all flags affected
---------------------
97   SUB A
90   SUB B
91   SUB C
92   SUB D
93   SUB E
94   SUB H
95   SUB L
96   SUB M

SUBTRACT WITH BORROW
Subtract Reg from A with 
Borrow= CY All flags affected
----------------------------------
9F   SBB A
98   SBB B
99   SBB C
9A   SBB D
9B   SBB E
9C   SBB H
9D   SBB L
9E   SBB M

POINTER ARITHMETIC
ADDS  rp to HL
CY <= Cout of 16 bit addition
No other Flags are affected
-----------------------------
09   DAD B
19   DAD D
29   DAD H
39   DAD SP

INCREMENT REG
CY is not affected
OTHER Flags are affected
-------------
3C   INR A
04   INR B
0C   INR C
14   INR D
1C   INR E
24   INR H
2C   INR L
34   INR M

DECREMENT REG
CY is not affected
Other flags are afftecetd
-------------
3D   DCR A
05   DCR B
0D   DCR C
15   DCR D
1D   DCR E
25   DCR H
2D   DCR L
35   DCR M

INCREMENT POINTERS
No flags are affected
------------------
03   INX B
13   INX D
23   INX H
33   INX SP

DECREMENT POINTERS
NO flags are afftected
------------------
0B   DCX B
1B   DCX D
2B   DCX H
3B   DCX SP

ROTATE INSTRUCTIONS
-------------------
07   RLC
0F   RRC
17   RAL
1F   RAR

LOGICAL AND
-----------
A7   ANA A
A0   ANA B
A1   ANA C
A2   ANA D
A3   ANA E
A4   ANA H
A5   ANA L
A6   ANA M

LOGICAL XOR
-----------
AF   XRA A
A8   XRA B
A9   XRA C
AA   XRA D
AB   XRA E
AC   XRA H
AD   XRA L
AE   XRA M

LOGICAL OR
-----------
B7   ORA A
B0   ORA B
B1   ORA C
B2   ORA D
B3   ORA E
B4   ORA H
B5   ORA L
B6   ORA M

COMPARE (A-R)
------------
BF   CMP A
B8   CMP B
B9   CMP C
BA   CMP D
BB   CMP E
BC   CMP H
BD   CMP L
BE   CMP M

IMMEDIATE INSTRUTIONS
---------------------
C6    ADI data
CE    ACI data
D6    SUI data
DE    SBI data
E6    ANI data
EE    XRI data
F6    ORI data
FE    CPI data

JUMP INSTRUCTIONS
-----------------
C3    JMP addr
C2    JNZ addr
CA    JZ  addr
D2    JNC addr
DA    JC  addr
E2    JPO addr
EA    JPE addr
F2    JP  addr
FA    JM  addr

CALL INSTRUCTIONS
-----------------
CD    CALL addr
C4    CNZ  addr
CC    CZ   addr
D4    CNC  addr
DC    CC   addr
E4    CPO  addr
EC    CPE  addr
F4    CP   addr
FC    CM   addr

RETURN INSTRUCTIONS
-------------------
C9     RET
C0     RNZ
C8     RZ
D0     RNC
D8     RC
E0     RPO
E8     RPE
F0     RP
F8     RM

RESRART (RST) INSTRUCTIONS
--------------------------
C7     RSR 0
CF     RST 1
D7     RST 2
DF     RST 3
E7     RST 4
EF     RST 5
F7     RST 6
FF     RST 7

PUSH INSTRUCTION
----------------
C5     PUSH PC
D5     PUSH DE
E5     PUSH HL
F5     PUSH PSW

POP INSTRUCTIONS
----------------
C1     POP  BC
D1     POP  DE
E1     POP  HL
F1     POP  PSW

MISCELLENEOUS
-------------
27    DAA
2F    CMA
37    STC
3F    CMC
E3    XTHL Exchange Top of 
           stack with HL}
F9    SPHL    SP <= HL         
E9    PCHL    PC <= HL   
D3    IN  port
DB    OUT port
F3    DI
FB    EI
76    HLT
20    RIM
48    SIM
00    NOP
EB (exchange DE and HL)

ED    Not defined in 8085 so taken as NOP
DD    Not defined in 8085 so taken as NOP
