/* This file is autogenerated by tracetool, do not edit. */ #ifndef TRACE_HW_DISPLAY_GENERATED_TRACERS_H #define TRACE_HW_DISPLAY_GENERATED_TRACERS_H #include "trace/control.h" extern TraceEvent _TRACE_JAZZ_LED_READ_EVENT; extern TraceEvent _TRACE_JAZZ_LED_WRITE_EVENT; extern TraceEvent _TRACE_XENFB_MOUSE_EVENT_EVENT; extern TraceEvent _TRACE_XENFB_KEY_EVENT_EVENT; extern TraceEvent _TRACE_XENFB_INPUT_CONNECTED_EVENT; extern TraceEvent _TRACE_G364FB_READ_EVENT; extern TraceEvent _TRACE_G364FB_WRITE_EVENT; extern TraceEvent _TRACE_VMWARE_VALUE_READ_EVENT; extern TraceEvent _TRACE_VMWARE_VALUE_WRITE_EVENT; extern TraceEvent _TRACE_VMWARE_PALETTE_READ_EVENT; extern TraceEvent _TRACE_VMWARE_PALETTE_WRITE_EVENT; extern TraceEvent _TRACE_VMWARE_SCRATCH_READ_EVENT; extern TraceEvent _TRACE_VMWARE_SCRATCH_WRITE_EVENT; extern TraceEvent _TRACE_VMWARE_SETMODE_EVENT; extern TraceEvent _TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_EVENT; extern TraceEvent _TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_EVENT; extern TraceEvent _TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_EVENT; extern TraceEvent _TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_FEATURES_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_GET_EDID_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_UNREF_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_RES_FLUSH_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_CREATE_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_UPDATE_CURSOR_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_FENCE_CTRL_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_FENCE_RESP_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES_EVENT; extern TraceEvent _TRACE_VIRTIO_GPU_CMD_SUSPENDED_EVENT; extern TraceEvent _TRACE_QXL_IO_WRITE_VGA_EVENT; extern TraceEvent _TRACE_QXL_CREATE_GUEST_PRIMARY_EVENT; extern TraceEvent _TRACE_QXL_CREATE_GUEST_PRIMARY_REST_EVENT; extern TraceEvent _TRACE_QXL_DESTROY_PRIMARY_EVENT; extern TraceEvent _TRACE_QXL_ENTER_VGA_MODE_EVENT; extern TraceEvent _TRACE_QXL_EXIT_VGA_MODE_EVENT; extern TraceEvent _TRACE_QXL_HARD_RESET_EVENT; extern TraceEvent _TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_EVENT; extern TraceEvent _TRACE_QXL_INTERFACE_ATTACH_WORKER_EVENT; extern TraceEvent _TRACE_QXL_INTERFACE_GET_INIT_INFO_EVENT; extern TraceEvent _TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_EVENT; extern TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_EVENT; extern TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_EVENT; extern TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_EVENT; extern TraceEvent _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_EVENT; extern TraceEvent _TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_EVENT; extern TraceEvent _TRACE_QXL_IO_LOG_EVENT; extern TraceEvent _TRACE_QXL_IO_READ_UNEXPECTED_EVENT; extern TraceEvent _TRACE_QXL_IO_UNEXPECTED_VGA_MODE_EVENT; extern TraceEvent _TRACE_QXL_IO_WRITE_EVENT; extern TraceEvent _TRACE_QXL_MEMSLOT_ADD_GUEST_EVENT; extern TraceEvent _TRACE_QXL_POST_LOAD_EVENT; extern TraceEvent _TRACE_QXL_PRE_LOAD_EVENT; extern TraceEvent _TRACE_QXL_PRE_SAVE_EVENT; extern TraceEvent _TRACE_QXL_RESET_SURFACES_EVENT; extern TraceEvent _TRACE_QXL_RING_COMMAND_CHECK_EVENT; extern TraceEvent _TRACE_QXL_RING_COMMAND_GET_EVENT; extern TraceEvent _TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_EVENT; extern TraceEvent _TRACE_QXL_RING_CURSOR_CHECK_EVENT; extern TraceEvent _TRACE_QXL_RING_CURSOR_GET_EVENT; extern TraceEvent _TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_EVENT; extern TraceEvent _TRACE_QXL_RING_RES_PUSH_EVENT; extern TraceEvent _TRACE_QXL_RING_RES_PUSH_REST_EVENT; extern TraceEvent _TRACE_QXL_RING_RES_PUT_EVENT; extern TraceEvent _TRACE_QXL_SET_MODE_EVENT; extern TraceEvent _TRACE_QXL_SOFT_RESET_EVENT; extern TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_EVENT; extern TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACES_EVENT; extern TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_EVENT; extern TraceEvent _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_EVENT; extern TraceEvent _TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_EVENT; extern TraceEvent _TRACE_QXL_SPICE_MONITORS_CONFIG_EVENT; extern TraceEvent _TRACE_QXL_SPICE_LOADVM_COMMANDS_EVENT; extern TraceEvent _TRACE_QXL_SPICE_OOM_EVENT; extern TraceEvent _TRACE_QXL_SPICE_RESET_CURSOR_EVENT; extern TraceEvent _TRACE_QXL_SPICE_RESET_IMAGE_CACHE_EVENT; extern TraceEvent _TRACE_QXL_SPICE_RESET_MEMSLOTS_EVENT; extern TraceEvent _TRACE_QXL_SPICE_UPDATE_AREA_EVENT; extern TraceEvent _TRACE_QXL_SPICE_UPDATE_AREA_REST_EVENT; extern TraceEvent _TRACE_QXL_SURFACES_DIRTY_EVENT; extern TraceEvent _TRACE_QXL_SEND_EVENTS_EVENT; extern TraceEvent _TRACE_QXL_SEND_EVENTS_VM_STOPPED_EVENT; extern TraceEvent _TRACE_QXL_SET_GUEST_BUG_EVENT; extern TraceEvent _TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_EVENT; extern TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_EVENT; extern TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_EVENT; extern TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_EVENT; extern TraceEvent _TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_EVENT; extern TraceEvent _TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_EVENT; extern TraceEvent _TRACE_QXL_RENDER_BLIT_EVENT; extern TraceEvent _TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_EVENT; extern TraceEvent _TRACE_QXL_RENDER_UPDATE_AREA_DONE_EVENT; extern TraceEvent _TRACE_VGA_STD_READ_IO_EVENT; extern TraceEvent _TRACE_VGA_STD_WRITE_IO_EVENT; extern TraceEvent _TRACE_VGA_VBE_READ_EVENT; extern TraceEvent _TRACE_VGA_VBE_WRITE_EVENT; extern TraceEvent _TRACE_VGA_CIRRUS_READ_IO_EVENT; extern TraceEvent _TRACE_VGA_CIRRUS_WRITE_IO_EVENT; extern TraceEvent _TRACE_VGA_CIRRUS_WRITE_BLT_EVENT; extern TraceEvent _TRACE_VGA_CIRRUS_WRITE_GR_EVENT; extern TraceEvent _TRACE_VGA_CIRRUS_BITBLT_START_EVENT; extern TraceEvent _TRACE_SII9022_READ_REG_EVENT; extern TraceEvent _TRACE_SII9022_WRITE_REG_EVENT; extern TraceEvent _TRACE_SII9022_SWITCH_MODE_EVENT; extern TraceEvent _TRACE_ATI_MM_READ_EVENT; extern TraceEvent _TRACE_ATI_MM_WRITE_EVENT; extern TraceEvent _TRACE_ARTIST_REG_READ_EVENT; extern TraceEvent _TRACE_ARTIST_REG_WRITE_EVENT; extern TraceEvent _TRACE_ARTIST_VRAM_READ_EVENT; extern TraceEvent _TRACE_ARTIST_VRAM_WRITE_EVENT; extern TraceEvent _TRACE_ARTIST_FILL_WINDOW_EVENT; extern TraceEvent _TRACE_ARTIST_BLOCK_MOVE_EVENT; extern TraceEvent _TRACE_ARTIST_DRAW_LINE_EVENT; extern TraceEvent _TRACE_CG3_READ_EVENT; extern TraceEvent _TRACE_CG3_WRITE_EVENT; extern TraceEvent _TRACE_DPCD_READ_EVENT; extern TraceEvent _TRACE_DPCD_WRITE_EVENT; extern TraceEvent _TRACE_SM501_SYSTEM_CONFIG_READ_EVENT; extern TraceEvent _TRACE_SM501_SYSTEM_CONFIG_WRITE_EVENT; extern TraceEvent _TRACE_SM501_I2C_READ_EVENT; extern TraceEvent _TRACE_SM501_I2C_WRITE_EVENT; extern TraceEvent _TRACE_SM501_PALETTE_READ_EVENT; extern TraceEvent _TRACE_SM501_PALETTE_WRITE_EVENT; extern TraceEvent _TRACE_SM501_DISP_CTRL_READ_EVENT; extern TraceEvent _TRACE_SM501_DISP_CTRL_WRITE_EVENT; extern TraceEvent _TRACE_SM501_2D_ENGINE_READ_EVENT; extern TraceEvent _TRACE_SM501_2D_ENGINE_WRITE_EVENT; extern TraceEvent _TRACE_MACFB_CTRL_READ_EVENT; extern TraceEvent _TRACE_MACFB_CTRL_WRITE_EVENT; extern TraceEvent _TRACE_MACFB_SENSE_READ_EVENT; extern TraceEvent _TRACE_MACFB_SENSE_WRITE_EVENT; extern TraceEvent _TRACE_MACFB_UPDATE_MODE_EVENT; extern TraceEvent _TRACE_DM163_REDRAW_EVENT; extern TraceEvent _TRACE_DM163_DCK_EVENT; extern TraceEvent _TRACE_DM163_EN_B_EVENT; extern TraceEvent _TRACE_DM163_RST_B_EVENT; extern TraceEvent _TRACE_DM163_LAT_B_EVENT; extern TraceEvent _TRACE_DM163_SIN_EVENT; extern TraceEvent _TRACE_DM163_SELBK_EVENT; extern TraceEvent _TRACE_DM163_ACTIVATED_ROWS_EVENT; extern TraceEvent _TRACE_DM163_BITS_PPI_EVENT; extern TraceEvent _TRACE_DM163_LEDS_EVENT; extern TraceEvent _TRACE_DM163_CHANNELS_EVENT; extern TraceEvent _TRACE_DM163_REFRESH_RATE_EVENT; extern uint16_t _TRACE_JAZZ_LED_READ_DSTATE; extern uint16_t _TRACE_JAZZ_LED_WRITE_DSTATE; extern uint16_t _TRACE_XENFB_MOUSE_EVENT_DSTATE; extern uint16_t _TRACE_XENFB_KEY_EVENT_DSTATE; extern uint16_t _TRACE_XENFB_INPUT_CONNECTED_DSTATE; extern uint16_t _TRACE_G364FB_READ_DSTATE; extern uint16_t _TRACE_G364FB_WRITE_DSTATE; extern uint16_t _TRACE_VMWARE_VALUE_READ_DSTATE; extern uint16_t _TRACE_VMWARE_VALUE_WRITE_DSTATE; extern uint16_t _TRACE_VMWARE_PALETTE_READ_DSTATE; extern uint16_t _TRACE_VMWARE_PALETTE_WRITE_DSTATE; extern uint16_t _TRACE_VMWARE_SCRATCH_READ_DSTATE; extern uint16_t _TRACE_VMWARE_SCRATCH_WRITE_DSTATE; extern uint16_t _TRACE_VMWARE_SETMODE_DSTATE; extern uint16_t _TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_DSTATE; extern uint16_t _TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_DSTATE; extern uint16_t _TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_DSTATE; extern uint16_t _TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_FEATURES_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_GET_EDID_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_UNREF_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_RES_FLUSH_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_CREATE_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_UPDATE_CURSOR_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_FENCE_CTRL_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_FENCE_RESP_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES_DSTATE; extern uint16_t _TRACE_VIRTIO_GPU_CMD_SUSPENDED_DSTATE; extern uint16_t _TRACE_QXL_IO_WRITE_VGA_DSTATE; extern uint16_t _TRACE_QXL_CREATE_GUEST_PRIMARY_DSTATE; extern uint16_t _TRACE_QXL_CREATE_GUEST_PRIMARY_REST_DSTATE; extern uint16_t _TRACE_QXL_DESTROY_PRIMARY_DSTATE; extern uint16_t _TRACE_QXL_ENTER_VGA_MODE_DSTATE; extern uint16_t _TRACE_QXL_EXIT_VGA_MODE_DSTATE; extern uint16_t _TRACE_QXL_HARD_RESET_DSTATE; extern uint16_t _TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_DSTATE; extern uint16_t _TRACE_QXL_INTERFACE_ATTACH_WORKER_DSTATE; extern uint16_t _TRACE_QXL_INTERFACE_GET_INIT_INFO_DSTATE; extern uint16_t _TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_DSTATE; extern uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_DSTATE; extern uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_DSTATE; extern uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_DSTATE; extern uint16_t _TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_DSTATE; extern uint16_t _TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_DSTATE; extern uint16_t _TRACE_QXL_IO_LOG_DSTATE; extern uint16_t _TRACE_QXL_IO_READ_UNEXPECTED_DSTATE; extern uint16_t _TRACE_QXL_IO_UNEXPECTED_VGA_MODE_DSTATE; extern uint16_t _TRACE_QXL_IO_WRITE_DSTATE; extern uint16_t _TRACE_QXL_MEMSLOT_ADD_GUEST_DSTATE; extern uint16_t _TRACE_QXL_POST_LOAD_DSTATE; extern uint16_t _TRACE_QXL_PRE_LOAD_DSTATE; extern uint16_t _TRACE_QXL_PRE_SAVE_DSTATE; extern uint16_t _TRACE_QXL_RESET_SURFACES_DSTATE; extern uint16_t _TRACE_QXL_RING_COMMAND_CHECK_DSTATE; extern uint16_t _TRACE_QXL_RING_COMMAND_GET_DSTATE; extern uint16_t _TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_DSTATE; extern uint16_t _TRACE_QXL_RING_CURSOR_CHECK_DSTATE; extern uint16_t _TRACE_QXL_RING_CURSOR_GET_DSTATE; extern uint16_t _TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_DSTATE; extern uint16_t _TRACE_QXL_RING_RES_PUSH_DSTATE; extern uint16_t _TRACE_QXL_RING_RES_PUSH_REST_DSTATE; extern uint16_t _TRACE_QXL_RING_RES_PUT_DSTATE; extern uint16_t _TRACE_QXL_SET_MODE_DSTATE; extern uint16_t _TRACE_QXL_SOFT_RESET_DSTATE; extern uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_DSTATE; extern uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACES_DSTATE; extern uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_DSTATE; extern uint16_t _TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_DSTATE; extern uint16_t _TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_DSTATE; extern uint16_t _TRACE_QXL_SPICE_MONITORS_CONFIG_DSTATE; extern uint16_t _TRACE_QXL_SPICE_LOADVM_COMMANDS_DSTATE; extern uint16_t _TRACE_QXL_SPICE_OOM_DSTATE; extern uint16_t _TRACE_QXL_SPICE_RESET_CURSOR_DSTATE; extern uint16_t _TRACE_QXL_SPICE_RESET_IMAGE_CACHE_DSTATE; extern uint16_t _TRACE_QXL_SPICE_RESET_MEMSLOTS_DSTATE; extern uint16_t _TRACE_QXL_SPICE_UPDATE_AREA_DSTATE; extern uint16_t _TRACE_QXL_SPICE_UPDATE_AREA_REST_DSTATE; extern uint16_t _TRACE_QXL_SURFACES_DIRTY_DSTATE; extern uint16_t _TRACE_QXL_SEND_EVENTS_DSTATE; extern uint16_t _TRACE_QXL_SEND_EVENTS_VM_STOPPED_DSTATE; extern uint16_t _TRACE_QXL_SET_GUEST_BUG_DSTATE; extern uint16_t _TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_DSTATE; extern uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_DSTATE; extern uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_DSTATE; extern uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_DSTATE; extern uint16_t _TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_DSTATE; extern uint16_t _TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_DSTATE; extern uint16_t _TRACE_QXL_RENDER_BLIT_DSTATE; extern uint16_t _TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_DSTATE; extern uint16_t _TRACE_QXL_RENDER_UPDATE_AREA_DONE_DSTATE; extern uint16_t _TRACE_VGA_STD_READ_IO_DSTATE; extern uint16_t _TRACE_VGA_STD_WRITE_IO_DSTATE; extern uint16_t _TRACE_VGA_VBE_READ_DSTATE; extern uint16_t _TRACE_VGA_VBE_WRITE_DSTATE; extern uint16_t _TRACE_VGA_CIRRUS_READ_IO_DSTATE; extern uint16_t _TRACE_VGA_CIRRUS_WRITE_IO_DSTATE; extern uint16_t _TRACE_VGA_CIRRUS_WRITE_BLT_DSTATE; extern uint16_t _TRACE_VGA_CIRRUS_WRITE_GR_DSTATE; extern uint16_t _TRACE_VGA_CIRRUS_BITBLT_START_DSTATE; extern uint16_t _TRACE_SII9022_READ_REG_DSTATE; extern uint16_t _TRACE_SII9022_WRITE_REG_DSTATE; extern uint16_t _TRACE_SII9022_SWITCH_MODE_DSTATE; extern uint16_t _TRACE_ATI_MM_READ_DSTATE; extern uint16_t _TRACE_ATI_MM_WRITE_DSTATE; extern uint16_t _TRACE_ARTIST_REG_READ_DSTATE; extern uint16_t _TRACE_ARTIST_REG_WRITE_DSTATE; extern uint16_t _TRACE_ARTIST_VRAM_READ_DSTATE; extern uint16_t _TRACE_ARTIST_VRAM_WRITE_DSTATE; extern uint16_t _TRACE_ARTIST_FILL_WINDOW_DSTATE; extern uint16_t _TRACE_ARTIST_BLOCK_MOVE_DSTATE; extern uint16_t _TRACE_ARTIST_DRAW_LINE_DSTATE; extern uint16_t _TRACE_CG3_READ_DSTATE; extern uint16_t _TRACE_CG3_WRITE_DSTATE; extern uint16_t _TRACE_DPCD_READ_DSTATE; extern uint16_t _TRACE_DPCD_WRITE_DSTATE; extern uint16_t _TRACE_SM501_SYSTEM_CONFIG_READ_DSTATE; extern uint16_t _TRACE_SM501_SYSTEM_CONFIG_WRITE_DSTATE; extern uint16_t _TRACE_SM501_I2C_READ_DSTATE; extern uint16_t _TRACE_SM501_I2C_WRITE_DSTATE; extern uint16_t _TRACE_SM501_PALETTE_READ_DSTATE; extern uint16_t _TRACE_SM501_PALETTE_WRITE_DSTATE; extern uint16_t _TRACE_SM501_DISP_CTRL_READ_DSTATE; extern uint16_t _TRACE_SM501_DISP_CTRL_WRITE_DSTATE; extern uint16_t _TRACE_SM501_2D_ENGINE_READ_DSTATE; extern uint16_t _TRACE_SM501_2D_ENGINE_WRITE_DSTATE; extern uint16_t _TRACE_MACFB_CTRL_READ_DSTATE; extern uint16_t _TRACE_MACFB_CTRL_WRITE_DSTATE; extern uint16_t _TRACE_MACFB_SENSE_READ_DSTATE; extern uint16_t _TRACE_MACFB_SENSE_WRITE_DSTATE; extern uint16_t _TRACE_MACFB_UPDATE_MODE_DSTATE; extern uint16_t _TRACE_DM163_REDRAW_DSTATE; extern uint16_t _TRACE_DM163_DCK_DSTATE; extern uint16_t _TRACE_DM163_EN_B_DSTATE; extern uint16_t _TRACE_DM163_RST_B_DSTATE; extern uint16_t _TRACE_DM163_LAT_B_DSTATE; extern uint16_t _TRACE_DM163_SIN_DSTATE; extern uint16_t _TRACE_DM163_SELBK_DSTATE; extern uint16_t _TRACE_DM163_ACTIVATED_ROWS_DSTATE; extern uint16_t _TRACE_DM163_BITS_PPI_DSTATE; extern uint16_t _TRACE_DM163_LEDS_DSTATE; extern uint16_t _TRACE_DM163_CHANNELS_DSTATE; extern uint16_t _TRACE_DM163_REFRESH_RATE_DSTATE; #define TRACE_JAZZ_LED_READ_ENABLED 1 #define TRACE_JAZZ_LED_WRITE_ENABLED 1 #define TRACE_XENFB_MOUSE_EVENT_ENABLED 1 #define TRACE_XENFB_KEY_EVENT_ENABLED 1 #define TRACE_XENFB_INPUT_CONNECTED_ENABLED 1 #define TRACE_G364FB_READ_ENABLED 1 #define TRACE_G364FB_WRITE_ENABLED 1 #define TRACE_VMWARE_VALUE_READ_ENABLED 1 #define TRACE_VMWARE_VALUE_WRITE_ENABLED 1 #define TRACE_VMWARE_PALETTE_READ_ENABLED 1 #define TRACE_VMWARE_PALETTE_WRITE_ENABLED 1 #define TRACE_VMWARE_SCRATCH_READ_ENABLED 1 #define TRACE_VMWARE_SCRATCH_WRITE_ENABLED 1 #define TRACE_VMWARE_SETMODE_ENABLED 1 #define TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_ENABLED 1 #define TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_ENABLED 1 #define TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_ENABLED 1 #define TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH_ENABLED 1 #define TRACE_VIRTIO_GPU_FEATURES_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_GET_EDID_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_RES_UNREF_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_RES_FLUSH_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_CTX_CREATE_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_ENABLED 1 #define TRACE_VIRTIO_GPU_UPDATE_CURSOR_ENABLED 1 #define TRACE_VIRTIO_GPU_FENCE_CTRL_ENABLED 1 #define TRACE_VIRTIO_GPU_FENCE_RESP_ENABLED 1 #define TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES_ENABLED 1 #define TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES_ENABLED 1 #define TRACE_VIRTIO_GPU_CMD_SUSPENDED_ENABLED 1 #define TRACE_QXL_IO_WRITE_VGA_ENABLED 0 #define TRACE_QXL_CREATE_GUEST_PRIMARY_ENABLED 1 #define TRACE_QXL_CREATE_GUEST_PRIMARY_REST_ENABLED 1 #define TRACE_QXL_DESTROY_PRIMARY_ENABLED 1 #define TRACE_QXL_ENTER_VGA_MODE_ENABLED 1 #define TRACE_QXL_EXIT_VGA_MODE_ENABLED 1 #define TRACE_QXL_HARD_RESET_ENABLED 1 #define TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_ENABLED 1 #define TRACE_QXL_INTERFACE_ATTACH_WORKER_ENABLED 1 #define TRACE_QXL_INTERFACE_GET_INIT_INFO_ENABLED 1 #define TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_ENABLED 1 #define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_ENABLED 1 #define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_ENABLED 1 #define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_ENABLED 1 #define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_ENABLED 1 #define TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_ENABLED 1 #define TRACE_QXL_IO_LOG_ENABLED 1 #define TRACE_QXL_IO_READ_UNEXPECTED_ENABLED 1 #define TRACE_QXL_IO_UNEXPECTED_VGA_MODE_ENABLED 1 #define TRACE_QXL_IO_WRITE_ENABLED 1 #define TRACE_QXL_MEMSLOT_ADD_GUEST_ENABLED 1 #define TRACE_QXL_POST_LOAD_ENABLED 1 #define TRACE_QXL_PRE_LOAD_ENABLED 1 #define TRACE_QXL_PRE_SAVE_ENABLED 1 #define TRACE_QXL_RESET_SURFACES_ENABLED 1 #define TRACE_QXL_RING_COMMAND_CHECK_ENABLED 1 #define TRACE_QXL_RING_COMMAND_GET_ENABLED 1 #define TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_ENABLED 1 #define TRACE_QXL_RING_CURSOR_CHECK_ENABLED 1 #define TRACE_QXL_RING_CURSOR_GET_ENABLED 1 #define TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_ENABLED 1 #define TRACE_QXL_RING_RES_PUSH_ENABLED 1 #define TRACE_QXL_RING_RES_PUSH_REST_ENABLED 1 #define TRACE_QXL_RING_RES_PUT_ENABLED 1 #define TRACE_QXL_SET_MODE_ENABLED 1 #define TRACE_QXL_SOFT_RESET_ENABLED 1 #define TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_ENABLED 1 #define TRACE_QXL_SPICE_DESTROY_SURFACES_ENABLED 1 #define TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_ENABLED 1 #define TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_ENABLED 1 #define TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_ENABLED 1 #define TRACE_QXL_SPICE_MONITORS_CONFIG_ENABLED 1 #define TRACE_QXL_SPICE_LOADVM_COMMANDS_ENABLED 1 #define TRACE_QXL_SPICE_OOM_ENABLED 1 #define TRACE_QXL_SPICE_RESET_CURSOR_ENABLED 1 #define TRACE_QXL_SPICE_RESET_IMAGE_CACHE_ENABLED 1 #define TRACE_QXL_SPICE_RESET_MEMSLOTS_ENABLED 1 #define TRACE_QXL_SPICE_UPDATE_AREA_ENABLED 1 #define TRACE_QXL_SPICE_UPDATE_AREA_REST_ENABLED 1 #define TRACE_QXL_SURFACES_DIRTY_ENABLED 1 #define TRACE_QXL_SEND_EVENTS_ENABLED 1 #define TRACE_QXL_SEND_EVENTS_VM_STOPPED_ENABLED 1 #define TRACE_QXL_SET_GUEST_BUG_ENABLED 1 #define TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_ENABLED 1 #define TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_ENABLED 1 #define TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_ENABLED 1 #define TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_ENABLED 1 #define TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_ENABLED 1 #define TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_ENABLED 1 #define TRACE_QXL_RENDER_BLIT_ENABLED 1 #define TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_ENABLED 1 #define TRACE_QXL_RENDER_UPDATE_AREA_DONE_ENABLED 1 #define TRACE_VGA_STD_READ_IO_ENABLED 1 #define TRACE_VGA_STD_WRITE_IO_ENABLED 1 #define TRACE_VGA_VBE_READ_ENABLED 1 #define TRACE_VGA_VBE_WRITE_ENABLED 1 #define TRACE_VGA_CIRRUS_READ_IO_ENABLED 1 #define TRACE_VGA_CIRRUS_WRITE_IO_ENABLED 1 #define TRACE_VGA_CIRRUS_WRITE_BLT_ENABLED 1 #define TRACE_VGA_CIRRUS_WRITE_GR_ENABLED 1 #define TRACE_VGA_CIRRUS_BITBLT_START_ENABLED 1 #define TRACE_SII9022_READ_REG_ENABLED 1 #define TRACE_SII9022_WRITE_REG_ENABLED 1 #define TRACE_SII9022_SWITCH_MODE_ENABLED 1 #define TRACE_ATI_MM_READ_ENABLED 1 #define TRACE_ATI_MM_WRITE_ENABLED 1 #define TRACE_ARTIST_REG_READ_ENABLED 1 #define TRACE_ARTIST_REG_WRITE_ENABLED 1 #define TRACE_ARTIST_VRAM_READ_ENABLED 1 #define TRACE_ARTIST_VRAM_WRITE_ENABLED 1 #define TRACE_ARTIST_FILL_WINDOW_ENABLED 1 #define TRACE_ARTIST_BLOCK_MOVE_ENABLED 1 #define TRACE_ARTIST_DRAW_LINE_ENABLED 1 #define TRACE_CG3_READ_ENABLED 1 #define TRACE_CG3_WRITE_ENABLED 1 #define TRACE_DPCD_READ_ENABLED 1 #define TRACE_DPCD_WRITE_ENABLED 1 #define TRACE_SM501_SYSTEM_CONFIG_READ_ENABLED 1 #define TRACE_SM501_SYSTEM_CONFIG_WRITE_ENABLED 1 #define TRACE_SM501_I2C_READ_ENABLED 1 #define TRACE_SM501_I2C_WRITE_ENABLED 1 #define TRACE_SM501_PALETTE_READ_ENABLED 1 #define TRACE_SM501_PALETTE_WRITE_ENABLED 1 #define TRACE_SM501_DISP_CTRL_READ_ENABLED 1 #define TRACE_SM501_DISP_CTRL_WRITE_ENABLED 1 #define TRACE_SM501_2D_ENGINE_READ_ENABLED 1 #define TRACE_SM501_2D_ENGINE_WRITE_ENABLED 1 #define TRACE_MACFB_CTRL_READ_ENABLED 1 #define TRACE_MACFB_CTRL_WRITE_ENABLED 1 #define TRACE_MACFB_SENSE_READ_ENABLED 1 #define TRACE_MACFB_SENSE_WRITE_ENABLED 1 #define TRACE_MACFB_UPDATE_MODE_ENABLED 1 #define TRACE_DM163_REDRAW_ENABLED 1 #define TRACE_DM163_DCK_ENABLED 1 #define TRACE_DM163_EN_B_ENABLED 1 #define TRACE_DM163_RST_B_ENABLED 1 #define TRACE_DM163_LAT_B_ENABLED 1 #define TRACE_DM163_SIN_ENABLED 1 #define TRACE_DM163_SELBK_ENABLED 1 #define TRACE_DM163_ACTIVATED_ROWS_ENABLED 1 #define TRACE_DM163_BITS_PPI_ENABLED 1 #define TRACE_DM163_LEDS_ENABLED 1 #define TRACE_DM163_CHANNELS_ENABLED 1 #define TRACE_DM163_REFRESH_RATE_ENABLED 1 #include "qemu/log-for-trace.h" #include "qemu/error-report.h" #define TRACE_JAZZ_LED_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_JAZZ_LED_READ) || \ false) static inline void _nocheck__trace_jazz_led_read(uint64_t addr, uint8_t val) { if (trace_event_get_state(TRACE_JAZZ_LED_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 4 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:jazz_led_read " "read addr=0x%"PRIx64": 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 502 "trace/trace-hw_display.h" } else { #line 4 "../hw/display/trace-events" qemu_log("jazz_led_read " "read addr=0x%"PRIx64": 0x%x" "\n", addr, val); #line 506 "trace/trace-hw_display.h" } } } static inline void trace_jazz_led_read(uint64_t addr, uint8_t val) { if (true) { _nocheck__trace_jazz_led_read(addr, val); } } #define TRACE_JAZZ_LED_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_JAZZ_LED_WRITE) || \ false) static inline void _nocheck__trace_jazz_led_write(uint64_t addr, uint8_t new) { if (trace_event_get_state(TRACE_JAZZ_LED_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 5 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:jazz_led_write " "write addr=0x%"PRIx64": 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, new); #line 533 "trace/trace-hw_display.h" } else { #line 5 "../hw/display/trace-events" qemu_log("jazz_led_write " "write addr=0x%"PRIx64": 0x%x" "\n", addr, new); #line 537 "trace/trace-hw_display.h" } } } static inline void trace_jazz_led_write(uint64_t addr, uint8_t new) { if (true) { _nocheck__trace_jazz_led_write(addr, new); } } #define TRACE_XENFB_MOUSE_EVENT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XENFB_MOUSE_EVENT) || \ false) static inline void _nocheck__trace_xenfb_mouse_event(void * opaque, int dx, int dy, int dz, int button_state, int abs_pointer_wanted) { if (trace_event_get_state(TRACE_XENFB_MOUSE_EVENT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 8 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:xenfb_mouse_event " "%p x %d y %d z %d bs 0x%x abs %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , opaque, dx, dy, dz, button_state, abs_pointer_wanted); #line 564 "trace/trace-hw_display.h" } else { #line 8 "../hw/display/trace-events" qemu_log("xenfb_mouse_event " "%p x %d y %d z %d bs 0x%x abs %d" "\n", opaque, dx, dy, dz, button_state, abs_pointer_wanted); #line 568 "trace/trace-hw_display.h" } } } static inline void trace_xenfb_mouse_event(void * opaque, int dx, int dy, int dz, int button_state, int abs_pointer_wanted) { if (true) { _nocheck__trace_xenfb_mouse_event(opaque, dx, dy, dz, button_state, abs_pointer_wanted); } } #define TRACE_XENFB_KEY_EVENT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XENFB_KEY_EVENT) || \ false) static inline void _nocheck__trace_xenfb_key_event(void * opaque, int scancode, int button_state) { if (trace_event_get_state(TRACE_XENFB_KEY_EVENT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 9 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:xenfb_key_event " "%p scancode %d bs 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , opaque, scancode, button_state); #line 595 "trace/trace-hw_display.h" } else { #line 9 "../hw/display/trace-events" qemu_log("xenfb_key_event " "%p scancode %d bs 0x%x" "\n", opaque, scancode, button_state); #line 599 "trace/trace-hw_display.h" } } } static inline void trace_xenfb_key_event(void * opaque, int scancode, int button_state) { if (true) { _nocheck__trace_xenfb_key_event(opaque, scancode, button_state); } } #define TRACE_XENFB_INPUT_CONNECTED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XENFB_INPUT_CONNECTED) || \ false) static inline void _nocheck__trace_xenfb_input_connected(void * xendev, int abs_pointer_wanted) { if (trace_event_get_state(TRACE_XENFB_INPUT_CONNECTED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 10 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:xenfb_input_connected " "%p abs %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , xendev, abs_pointer_wanted); #line 626 "trace/trace-hw_display.h" } else { #line 10 "../hw/display/trace-events" qemu_log("xenfb_input_connected " "%p abs %d" "\n", xendev, abs_pointer_wanted); #line 630 "trace/trace-hw_display.h" } } } static inline void trace_xenfb_input_connected(void * xendev, int abs_pointer_wanted) { if (true) { _nocheck__trace_xenfb_input_connected(xendev, abs_pointer_wanted); } } #define TRACE_G364FB_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_G364FB_READ) || \ false) static inline void _nocheck__trace_g364fb_read(uint64_t addr, uint32_t val) { if (trace_event_get_state(TRACE_G364FB_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 13 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:g364fb_read " "read addr=0x%"PRIx64": 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 657 "trace/trace-hw_display.h" } else { #line 13 "../hw/display/trace-events" qemu_log("g364fb_read " "read addr=0x%"PRIx64": 0x%x" "\n", addr, val); #line 661 "trace/trace-hw_display.h" } } } static inline void trace_g364fb_read(uint64_t addr, uint32_t val) { if (true) { _nocheck__trace_g364fb_read(addr, val); } } #define TRACE_G364FB_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_G364FB_WRITE) || \ false) static inline void _nocheck__trace_g364fb_write(uint64_t addr, uint32_t new) { if (trace_event_get_state(TRACE_G364FB_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 14 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:g364fb_write " "write addr=0x%"PRIx64": 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, new); #line 688 "trace/trace-hw_display.h" } else { #line 14 "../hw/display/trace-events" qemu_log("g364fb_write " "write addr=0x%"PRIx64": 0x%x" "\n", addr, new); #line 692 "trace/trace-hw_display.h" } } } static inline void trace_g364fb_write(uint64_t addr, uint32_t new) { if (true) { _nocheck__trace_g364fb_write(addr, new); } } #define TRACE_VMWARE_VALUE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VMWARE_VALUE_READ) || \ false) static inline void _nocheck__trace_vmware_value_read(uint32_t index, uint32_t value) { if (trace_event_get_state(TRACE_VMWARE_VALUE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 17 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vmware_value_read " "index %d, value 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, value); #line 719 "trace/trace-hw_display.h" } else { #line 17 "../hw/display/trace-events" qemu_log("vmware_value_read " "index %d, value 0x%x" "\n", index, value); #line 723 "trace/trace-hw_display.h" } } } static inline void trace_vmware_value_read(uint32_t index, uint32_t value) { if (true) { _nocheck__trace_vmware_value_read(index, value); } } #define TRACE_VMWARE_VALUE_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VMWARE_VALUE_WRITE) || \ false) static inline void _nocheck__trace_vmware_value_write(uint32_t index, uint32_t value) { if (trace_event_get_state(TRACE_VMWARE_VALUE_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 18 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vmware_value_write " "index %d, value 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, value); #line 750 "trace/trace-hw_display.h" } else { #line 18 "../hw/display/trace-events" qemu_log("vmware_value_write " "index %d, value 0x%x" "\n", index, value); #line 754 "trace/trace-hw_display.h" } } } static inline void trace_vmware_value_write(uint32_t index, uint32_t value) { if (true) { _nocheck__trace_vmware_value_write(index, value); } } #define TRACE_VMWARE_PALETTE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VMWARE_PALETTE_READ) || \ false) static inline void _nocheck__trace_vmware_palette_read(uint32_t index, uint32_t value) { if (trace_event_get_state(TRACE_VMWARE_PALETTE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 19 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vmware_palette_read " "index %d, value 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, value); #line 781 "trace/trace-hw_display.h" } else { #line 19 "../hw/display/trace-events" qemu_log("vmware_palette_read " "index %d, value 0x%x" "\n", index, value); #line 785 "trace/trace-hw_display.h" } } } static inline void trace_vmware_palette_read(uint32_t index, uint32_t value) { if (true) { _nocheck__trace_vmware_palette_read(index, value); } } #define TRACE_VMWARE_PALETTE_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VMWARE_PALETTE_WRITE) || \ false) static inline void _nocheck__trace_vmware_palette_write(uint32_t index, uint32_t value) { if (trace_event_get_state(TRACE_VMWARE_PALETTE_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 20 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vmware_palette_write " "index %d, value 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, value); #line 812 "trace/trace-hw_display.h" } else { #line 20 "../hw/display/trace-events" qemu_log("vmware_palette_write " "index %d, value 0x%x" "\n", index, value); #line 816 "trace/trace-hw_display.h" } } } static inline void trace_vmware_palette_write(uint32_t index, uint32_t value) { if (true) { _nocheck__trace_vmware_palette_write(index, value); } } #define TRACE_VMWARE_SCRATCH_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VMWARE_SCRATCH_READ) || \ false) static inline void _nocheck__trace_vmware_scratch_read(uint32_t index, uint32_t value) { if (trace_event_get_state(TRACE_VMWARE_SCRATCH_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 21 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vmware_scratch_read " "index %d, value 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, value); #line 843 "trace/trace-hw_display.h" } else { #line 21 "../hw/display/trace-events" qemu_log("vmware_scratch_read " "index %d, value 0x%x" "\n", index, value); #line 847 "trace/trace-hw_display.h" } } } static inline void trace_vmware_scratch_read(uint32_t index, uint32_t value) { if (true) { _nocheck__trace_vmware_scratch_read(index, value); } } #define TRACE_VMWARE_SCRATCH_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VMWARE_SCRATCH_WRITE) || \ false) static inline void _nocheck__trace_vmware_scratch_write(uint32_t index, uint32_t value) { if (trace_event_get_state(TRACE_VMWARE_SCRATCH_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 22 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vmware_scratch_write " "index %d, value 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, value); #line 874 "trace/trace-hw_display.h" } else { #line 22 "../hw/display/trace-events" qemu_log("vmware_scratch_write " "index %d, value 0x%x" "\n", index, value); #line 878 "trace/trace-hw_display.h" } } } static inline void trace_vmware_scratch_write(uint32_t index, uint32_t value) { if (true) { _nocheck__trace_vmware_scratch_write(index, value); } } #define TRACE_VMWARE_SETMODE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VMWARE_SETMODE) || \ false) static inline void _nocheck__trace_vmware_setmode(uint32_t w, uint32_t h, uint32_t bpp) { if (trace_event_get_state(TRACE_VMWARE_SETMODE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 23 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vmware_setmode " "%dx%d @ %d bpp" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , w, h, bpp); #line 905 "trace/trace-hw_display.h" } else { #line 23 "../hw/display/trace-events" qemu_log("vmware_setmode " "%dx%d @ %d bpp" "\n", w, h, bpp); #line 909 "trace/trace-hw_display.h" } } } static inline void trace_vmware_setmode(uint32_t w, uint32_t h, uint32_t bpp) { if (true) { _nocheck__trace_vmware_setmode(w, h, bpp); } } #define TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO) || \ false) static inline void _nocheck__trace_vmware_verify_rect_less_than_zero(const char * name, const char * param, int x) { if (trace_event_get_state(TRACE_VMWARE_VERIFY_RECT_LESS_THAN_ZERO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 24 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vmware_verify_rect_less_than_zero " "%s: %s was < 0 (%d)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , name, param, x); #line 936 "trace/trace-hw_display.h" } else { #line 24 "../hw/display/trace-events" qemu_log("vmware_verify_rect_less_than_zero " "%s: %s was < 0 (%d)" "\n", name, param, x); #line 940 "trace/trace-hw_display.h" } } } static inline void trace_vmware_verify_rect_less_than_zero(const char * name, const char * param, int x) { if (true) { _nocheck__trace_vmware_verify_rect_less_than_zero(name, param, x); } } #define TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND) || \ false) static inline void _nocheck__trace_vmware_verify_rect_greater_than_bound(const char * name, const char * param, int bound, int x) { if (trace_event_get_state(TRACE_VMWARE_VERIFY_RECT_GREATER_THAN_BOUND) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 25 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vmware_verify_rect_greater_than_bound " "%s: %s was > %d (%d)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , name, param, bound, x); #line 967 "trace/trace-hw_display.h" } else { #line 25 "../hw/display/trace-events" qemu_log("vmware_verify_rect_greater_than_bound " "%s: %s was > %d (%d)" "\n", name, param, bound, x); #line 971 "trace/trace-hw_display.h" } } } static inline void trace_vmware_verify_rect_greater_than_bound(const char * name, const char * param, int bound, int x) { if (true) { _nocheck__trace_vmware_verify_rect_greater_than_bound(name, param, bound, x); } } #define TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED) || \ false) static inline void _nocheck__trace_vmware_verify_rect_surface_bound_exceeded(const char * name, const char * component, int bound, const char * param1, int value1, const char * param2, int value2) { if (trace_event_get_state(TRACE_VMWARE_VERIFY_RECT_SURFACE_BOUND_EXCEEDED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 26 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vmware_verify_rect_surface_bound_exceeded " "%s: %s > %d (%s: %d, %s: %d)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , name, component, bound, param1, value1, param2, value2); #line 998 "trace/trace-hw_display.h" } else { #line 26 "../hw/display/trace-events" qemu_log("vmware_verify_rect_surface_bound_exceeded " "%s: %s > %d (%s: %d, %s: %d)" "\n", name, component, bound, param1, value1, param2, value2); #line 1002 "trace/trace-hw_display.h" } } } static inline void trace_vmware_verify_rect_surface_bound_exceeded(const char * name, const char * component, int bound, const char * param1, int value1, const char * param2, int value2) { if (true) { _nocheck__trace_vmware_verify_rect_surface_bound_exceeded(name, component, bound, param1, value1, param2, value2); } } #define TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH) || \ false) static inline void _nocheck__trace_vmware_update_rect_delayed_flush(void) { if (trace_event_get_state(TRACE_VMWARE_UPDATE_RECT_DELAYED_FLUSH) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 27 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vmware_update_rect_delayed_flush " "display update FIFO full - forcing flush" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 1029 "trace/trace-hw_display.h" } else { #line 27 "../hw/display/trace-events" qemu_log("vmware_update_rect_delayed_flush " "display update FIFO full - forcing flush" "\n"); #line 1033 "trace/trace-hw_display.h" } } } static inline void trace_vmware_update_rect_delayed_flush(void) { if (true) { _nocheck__trace_vmware_update_rect_delayed_flush(); } } #define TRACE_VIRTIO_GPU_FEATURES_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_FEATURES) || \ false) static inline void _nocheck__trace_virtio_gpu_features(bool virgl) { if (trace_event_get_state(TRACE_VIRTIO_GPU_FEATURES) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 30 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_features " "virgl %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , virgl); #line 1060 "trace/trace-hw_display.h" } else { #line 30 "../hw/display/trace-events" qemu_log("virtio_gpu_features " "virgl %d" "\n", virgl); #line 1064 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_features(bool virgl) { if (true) { _nocheck__trace_virtio_gpu_features(virgl); } } #define TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_get_display_info(void) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_GET_DISPLAY_INFO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 34 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_get_display_info " "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 1091 "trace/trace-hw_display.h" } else { #line 34 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_get_display_info " "" "\n"); #line 1095 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_get_display_info(void) { if (true) { _nocheck__trace_virtio_gpu_cmd_get_display_info(); } } #define TRACE_VIRTIO_GPU_CMD_GET_EDID_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_GET_EDID) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_get_edid(uint32_t scanout) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_GET_EDID) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 35 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_get_edid " "scanout %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , scanout); #line 1122 "trace/trace-hw_display.h" } else { #line 35 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_get_edid " "scanout %d" "\n", scanout); #line 1126 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_get_edid(uint32_t scanout) { if (true) { _nocheck__trace_virtio_gpu_cmd_get_edid(scanout); } } #define TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_SET_SCANOUT) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_set_scanout(uint32_t id, uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_SET_SCANOUT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 36 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_set_scanout " "id %d, res 0x%x, w %d, h %d, x %d, y %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , id, res, w, h, x, y); #line 1153 "trace/trace-hw_display.h" } else { #line 36 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_set_scanout " "id %d, res 0x%x, w %d, h %d, x %d, y %d" "\n", id, res, w, h, x, y); #line 1157 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_set_scanout(uint32_t id, uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) { if (true) { _nocheck__trace_virtio_gpu_cmd_set_scanout(id, res, w, h, x, y); } } #define TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_set_scanout_blob(uint32_t id, uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_SET_SCANOUT_BLOB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 37 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_set_scanout_blob " "id %d, res 0x%x, w %d, h %d, x %d, y %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , id, res, w, h, x, y); #line 1184 "trace/trace-hw_display.h" } else { #line 37 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_set_scanout_blob " "id %d, res 0x%x, w %d, h %d, x %d, y %d" "\n", id, res, w, h, x, y); #line 1188 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_set_scanout_blob(uint32_t id, uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) { if (true) { _nocheck__trace_virtio_gpu_cmd_set_scanout_blob(id, res, w, h, x, y); } } #define TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_res_create_2d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_CREATE_2D) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 38 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_res_create_2d " "res 0x%x, fmt 0x%x, w %d, h %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , res, fmt, w, h); #line 1215 "trace/trace-hw_display.h" } else { #line 38 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_res_create_2d " "res 0x%x, fmt 0x%x, w %d, h %d" "\n", res, fmt, w, h); #line 1219 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_res_create_2d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h) { if (true) { _nocheck__trace_virtio_gpu_cmd_res_create_2d(res, fmt, w, h); } } #define TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_res_create_3d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h, uint32_t d) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_CREATE_3D) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 39 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_res_create_3d " "res 0x%x, fmt 0x%x, w %d, h %d, d %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , res, fmt, w, h, d); #line 1246 "trace/trace-hw_display.h" } else { #line 39 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_res_create_3d " "res 0x%x, fmt 0x%x, w %d, h %d, d %d" "\n", res, fmt, w, h, d); #line 1250 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_res_create_3d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h, uint32_t d) { if (true) { _nocheck__trace_virtio_gpu_cmd_res_create_3d(res, fmt, w, h, d); } } #define TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_res_create_blob(uint32_t res, uint64_t size) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_CREATE_BLOB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 40 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_res_create_blob " "res 0x%x, size %" PRId64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , res, size); #line 1277 "trace/trace-hw_display.h" } else { #line 40 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_res_create_blob " "res 0x%x, size %" PRId64 "\n", res, size); #line 1281 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_res_create_blob(uint32_t res, uint64_t size) { if (true) { _nocheck__trace_virtio_gpu_cmd_res_create_blob(res, size); } } #define TRACE_VIRTIO_GPU_CMD_RES_UNREF_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_UNREF) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_res_unref(uint32_t res) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_UNREF) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 41 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_res_unref " "res 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , res); #line 1308 "trace/trace-hw_display.h" } else { #line 41 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_res_unref " "res 0x%x" "\n", res); #line 1312 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_res_unref(uint32_t res) { if (true) { _nocheck__trace_virtio_gpu_cmd_res_unref(res); } } #define TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_res_back_attach(uint32_t res) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_BACK_ATTACH) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 42 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_res_back_attach " "res 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , res); #line 1339 "trace/trace-hw_display.h" } else { #line 42 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_res_back_attach " "res 0x%x" "\n", res); #line 1343 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_res_back_attach(uint32_t res) { if (true) { _nocheck__trace_virtio_gpu_cmd_res_back_attach(res); } } #define TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_res_back_detach(uint32_t res) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_BACK_DETACH) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 43 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_res_back_detach " "res 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , res); #line 1370 "trace/trace-hw_display.h" } else { #line 43 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_res_back_detach " "res 0x%x" "\n", res); #line 1374 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_res_back_detach(uint32_t res) { if (true) { _nocheck__trace_virtio_gpu_cmd_res_back_detach(res); } } #define TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_res_xfer_toh_2d(uint32_t res) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_2D) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 44 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_res_xfer_toh_2d " "res 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , res); #line 1401 "trace/trace-hw_display.h" } else { #line 44 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_res_xfer_toh_2d " "res 0x%x" "\n", res); #line 1405 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_res_xfer_toh_2d(uint32_t res) { if (true) { _nocheck__trace_virtio_gpu_cmd_res_xfer_toh_2d(res); } } #define TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_res_xfer_toh_3d(uint32_t res) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_XFER_TOH_3D) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 45 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_res_xfer_toh_3d " "res 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , res); #line 1432 "trace/trace-hw_display.h" } else { #line 45 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_res_xfer_toh_3d " "res 0x%x" "\n", res); #line 1436 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_res_xfer_toh_3d(uint32_t res) { if (true) { _nocheck__trace_virtio_gpu_cmd_res_xfer_toh_3d(res); } } #define TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_res_xfer_fromh_3d(uint32_t res) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_XFER_FROMH_3D) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 46 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_res_xfer_fromh_3d " "res 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , res); #line 1463 "trace/trace-hw_display.h" } else { #line 46 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_res_xfer_fromh_3d " "res 0x%x" "\n", res); #line 1467 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_res_xfer_fromh_3d(uint32_t res) { if (true) { _nocheck__trace_virtio_gpu_cmd_res_xfer_fromh_3d(res); } } #define TRACE_VIRTIO_GPU_CMD_RES_FLUSH_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_RES_FLUSH) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_res_flush(uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_RES_FLUSH) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 47 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_res_flush " "res 0x%x, w %d, h %d, x %d, y %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , res, w, h, x, y); #line 1494 "trace/trace-hw_display.h" } else { #line 47 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_res_flush " "res 0x%x, w %d, h %d, x %d, y %d" "\n", res, w, h, x, y); #line 1498 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_res_flush(uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) { if (true) { _nocheck__trace_virtio_gpu_cmd_res_flush(res, w, h, x, y); } } #define TRACE_VIRTIO_GPU_CMD_CTX_CREATE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_CTX_CREATE) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_ctx_create(uint32_t ctx, const char * name) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_CTX_CREATE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 48 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_ctx_create " "ctx 0x%x, name %s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ctx, name); #line 1525 "trace/trace-hw_display.h" } else { #line 48 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_ctx_create " "ctx 0x%x, name %s" "\n", ctx, name); #line 1529 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_ctx_create(uint32_t ctx, const char * name) { if (true) { _nocheck__trace_virtio_gpu_cmd_ctx_create(ctx, name); } } #define TRACE_VIRTIO_GPU_CMD_CTX_DESTROY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_CTX_DESTROY) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_ctx_destroy(uint32_t ctx) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_CTX_DESTROY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 49 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_ctx_destroy " "ctx 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ctx); #line 1556 "trace/trace-hw_display.h" } else { #line 49 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_ctx_destroy " "ctx 0x%x" "\n", ctx); #line 1560 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_ctx_destroy(uint32_t ctx) { if (true) { _nocheck__trace_virtio_gpu_cmd_ctx_destroy(ctx); } } #define TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_ctx_res_attach(uint32_t ctx, uint32_t res) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_CTX_RES_ATTACH) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 50 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_ctx_res_attach " "ctx 0x%x, res 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ctx, res); #line 1587 "trace/trace-hw_display.h" } else { #line 50 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_ctx_res_attach " "ctx 0x%x, res 0x%x" "\n", ctx, res); #line 1591 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_ctx_res_attach(uint32_t ctx, uint32_t res) { if (true) { _nocheck__trace_virtio_gpu_cmd_ctx_res_attach(ctx, res); } } #define TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_ctx_res_detach(uint32_t ctx, uint32_t res) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_CTX_RES_DETACH) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 51 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_ctx_res_detach " "ctx 0x%x, res 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ctx, res); #line 1618 "trace/trace-hw_display.h" } else { #line 51 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_ctx_res_detach " "ctx 0x%x, res 0x%x" "\n", ctx, res); #line 1622 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_ctx_res_detach(uint32_t ctx, uint32_t res) { if (true) { _nocheck__trace_virtio_gpu_cmd_ctx_res_detach(ctx, res); } } #define TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_ctx_submit(uint32_t ctx, uint32_t size) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_CTX_SUBMIT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 52 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_ctx_submit " "ctx 0x%x, size %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ctx, size); #line 1649 "trace/trace-hw_display.h" } else { #line 52 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_ctx_submit " "ctx 0x%x, size %d" "\n", ctx, size); #line 1653 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_ctx_submit(uint32_t ctx, uint32_t size) { if (true) { _nocheck__trace_virtio_gpu_cmd_ctx_submit(ctx, size); } } #define TRACE_VIRTIO_GPU_UPDATE_CURSOR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_UPDATE_CURSOR) || \ false) static inline void _nocheck__trace_virtio_gpu_update_cursor(uint32_t scanout, uint32_t x, uint32_t y, const char * type, uint32_t res) { if (trace_event_get_state(TRACE_VIRTIO_GPU_UPDATE_CURSOR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 53 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_update_cursor " "scanout %d, x %d, y %d, %s, res 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , scanout, x, y, type, res); #line 1680 "trace/trace-hw_display.h" } else { #line 53 "../hw/display/trace-events" qemu_log("virtio_gpu_update_cursor " "scanout %d, x %d, y %d, %s, res 0x%x" "\n", scanout, x, y, type, res); #line 1684 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_update_cursor(uint32_t scanout, uint32_t x, uint32_t y, const char * type, uint32_t res) { if (true) { _nocheck__trace_virtio_gpu_update_cursor(scanout, x, y, type, res); } } #define TRACE_VIRTIO_GPU_FENCE_CTRL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_FENCE_CTRL) || \ false) static inline void _nocheck__trace_virtio_gpu_fence_ctrl(uint64_t fence, uint32_t type) { if (trace_event_get_state(TRACE_VIRTIO_GPU_FENCE_CTRL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 54 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_fence_ctrl " "fence 0x%" PRIx64 ", type 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , fence, type); #line 1711 "trace/trace-hw_display.h" } else { #line 54 "../hw/display/trace-events" qemu_log("virtio_gpu_fence_ctrl " "fence 0x%" PRIx64 ", type 0x%x" "\n", fence, type); #line 1715 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_fence_ctrl(uint64_t fence, uint32_t type) { if (true) { _nocheck__trace_virtio_gpu_fence_ctrl(fence, type); } } #define TRACE_VIRTIO_GPU_FENCE_RESP_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_FENCE_RESP) || \ false) static inline void _nocheck__trace_virtio_gpu_fence_resp(uint64_t fence) { if (trace_event_get_state(TRACE_VIRTIO_GPU_FENCE_RESP) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 55 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_fence_resp " "fence 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , fence); #line 1742 "trace/trace-hw_display.h" } else { #line 55 "../hw/display/trace-events" qemu_log("virtio_gpu_fence_resp " "fence 0x%" PRIx64 "\n", fence); #line 1746 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_fence_resp(uint64_t fence) { if (true) { _nocheck__trace_virtio_gpu_fence_resp(fence); } } #define TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES) || \ false) static inline void _nocheck__trace_virtio_gpu_inc_inflight_fences(uint32_t inflight) { if (trace_event_get_state(TRACE_VIRTIO_GPU_INC_INFLIGHT_FENCES) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 56 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_inc_inflight_fences " "in-flight+ %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , inflight); #line 1773 "trace/trace-hw_display.h" } else { #line 56 "../hw/display/trace-events" qemu_log("virtio_gpu_inc_inflight_fences " "in-flight+ %u" "\n", inflight); #line 1777 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_inc_inflight_fences(uint32_t inflight) { if (true) { _nocheck__trace_virtio_gpu_inc_inflight_fences(inflight); } } #define TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES) || \ false) static inline void _nocheck__trace_virtio_gpu_dec_inflight_fences(uint32_t inflight) { if (trace_event_get_state(TRACE_VIRTIO_GPU_DEC_INFLIGHT_FENCES) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 57 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_dec_inflight_fences " "in-flight- %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , inflight); #line 1804 "trace/trace-hw_display.h" } else { #line 57 "../hw/display/trace-events" qemu_log("virtio_gpu_dec_inflight_fences " "in-flight- %u" "\n", inflight); #line 1808 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_dec_inflight_fences(uint32_t inflight) { if (true) { _nocheck__trace_virtio_gpu_dec_inflight_fences(inflight); } } #define TRACE_VIRTIO_GPU_CMD_SUSPENDED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRTIO_GPU_CMD_SUSPENDED) || \ false) static inline void _nocheck__trace_virtio_gpu_cmd_suspended(uint32_t cmd) { if (trace_event_get_state(TRACE_VIRTIO_GPU_CMD_SUSPENDED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 58 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:virtio_gpu_cmd_suspended " "cmd 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cmd); #line 1835 "trace/trace-hw_display.h" } else { #line 58 "../hw/display/trace-events" qemu_log("virtio_gpu_cmd_suspended " "cmd 0x%x" "\n", cmd); #line 1839 "trace/trace-hw_display.h" } } } static inline void trace_virtio_gpu_cmd_suspended(uint32_t cmd) { if (true) { _nocheck__trace_virtio_gpu_cmd_suspended(cmd); } } #define TRACE_QXL_IO_WRITE_VGA_BACKEND_DSTATE() ( \ false) static inline void _nocheck__trace_qxl_io_write_vga(int qid, const char * mode, uint32_t addr, uint32_t val) { } static inline void trace_qxl_io_write_vga(int qid, const char * mode, uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_qxl_io_write_vga(qid, mode, addr, val); } } #define TRACE_QXL_CREATE_GUEST_PRIMARY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_CREATE_GUEST_PRIMARY) || \ false) static inline void _nocheck__trace_qxl_create_guest_primary(int qid, uint32_t width, uint32_t height, uint64_t mem, uint32_t format, uint32_t position) { if (trace_event_get_state(TRACE_QXL_CREATE_GUEST_PRIMARY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 62 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_create_guest_primary " "%d %ux%u mem=0x%" PRIx64 " %u,%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, width, height, mem, format, position); #line 1880 "trace/trace-hw_display.h" } else { #line 62 "../hw/display/trace-events" qemu_log("qxl_create_guest_primary " "%d %ux%u mem=0x%" PRIx64 " %u,%u" "\n", qid, width, height, mem, format, position); #line 1884 "trace/trace-hw_display.h" } } } static inline void trace_qxl_create_guest_primary(int qid, uint32_t width, uint32_t height, uint64_t mem, uint32_t format, uint32_t position) { if (true) { _nocheck__trace_qxl_create_guest_primary(qid, width, height, mem, format, position); } } #define TRACE_QXL_CREATE_GUEST_PRIMARY_REST_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_CREATE_GUEST_PRIMARY_REST) || \ false) static inline void _nocheck__trace_qxl_create_guest_primary_rest(int qid, int32_t stride, uint32_t type, uint32_t flags) { if (trace_event_get_state(TRACE_QXL_CREATE_GUEST_PRIMARY_REST) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 63 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_create_guest_primary_rest " "%d %d,%d,%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, stride, type, flags); #line 1911 "trace/trace-hw_display.h" } else { #line 63 "../hw/display/trace-events" qemu_log("qxl_create_guest_primary_rest " "%d %d,%d,%d" "\n", qid, stride, type, flags); #line 1915 "trace/trace-hw_display.h" } } } static inline void trace_qxl_create_guest_primary_rest(int qid, int32_t stride, uint32_t type, uint32_t flags) { if (true) { _nocheck__trace_qxl_create_guest_primary_rest(qid, stride, type, flags); } } #define TRACE_QXL_DESTROY_PRIMARY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_DESTROY_PRIMARY) || \ false) static inline void _nocheck__trace_qxl_destroy_primary(int qid) { if (trace_event_get_state(TRACE_QXL_DESTROY_PRIMARY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 64 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_destroy_primary " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 1942 "trace/trace-hw_display.h" } else { #line 64 "../hw/display/trace-events" qemu_log("qxl_destroy_primary " "%d" "\n", qid); #line 1946 "trace/trace-hw_display.h" } } } static inline void trace_qxl_destroy_primary(int qid) { if (true) { _nocheck__trace_qxl_destroy_primary(qid); } } #define TRACE_QXL_ENTER_VGA_MODE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_ENTER_VGA_MODE) || \ false) static inline void _nocheck__trace_qxl_enter_vga_mode(int qid) { if (trace_event_get_state(TRACE_QXL_ENTER_VGA_MODE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 65 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_enter_vga_mode " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 1973 "trace/trace-hw_display.h" } else { #line 65 "../hw/display/trace-events" qemu_log("qxl_enter_vga_mode " "%d" "\n", qid); #line 1977 "trace/trace-hw_display.h" } } } static inline void trace_qxl_enter_vga_mode(int qid) { if (true) { _nocheck__trace_qxl_enter_vga_mode(qid); } } #define TRACE_QXL_EXIT_VGA_MODE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_EXIT_VGA_MODE) || \ false) static inline void _nocheck__trace_qxl_exit_vga_mode(int qid) { if (trace_event_get_state(TRACE_QXL_EXIT_VGA_MODE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 66 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_exit_vga_mode " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 2004 "trace/trace-hw_display.h" } else { #line 66 "../hw/display/trace-events" qemu_log("qxl_exit_vga_mode " "%d" "\n", qid); #line 2008 "trace/trace-hw_display.h" } } } static inline void trace_qxl_exit_vga_mode(int qid) { if (true) { _nocheck__trace_qxl_exit_vga_mode(qid); } } #define TRACE_QXL_HARD_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_HARD_RESET) || \ false) static inline void _nocheck__trace_qxl_hard_reset(int qid, int64_t loadvm) { if (trace_event_get_state(TRACE_QXL_HARD_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 67 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_hard_reset " "%d loadvm=%"PRId64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, loadvm); #line 2035 "trace/trace-hw_display.h" } else { #line 67 "../hw/display/trace-events" qemu_log("qxl_hard_reset " "%d loadvm=%"PRId64 "\n", qid, loadvm); #line 2039 "trace/trace-hw_display.h" } } } static inline void trace_qxl_hard_reset(int qid, int64_t loadvm) { if (true) { _nocheck__trace_qxl_hard_reset(qid, loadvm); } } #define TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO) || \ false) static inline void _nocheck__trace_qxl_interface_async_complete_io(int qid, uint32_t current_async, void * cookie) { if (trace_event_get_state(TRACE_QXL_INTERFACE_ASYNC_COMPLETE_IO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 68 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_interface_async_complete_io " "%d current=%d cookie=%p" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, current_async, cookie); #line 2066 "trace/trace-hw_display.h" } else { #line 68 "../hw/display/trace-events" qemu_log("qxl_interface_async_complete_io " "%d current=%d cookie=%p" "\n", qid, current_async, cookie); #line 2070 "trace/trace-hw_display.h" } } } static inline void trace_qxl_interface_async_complete_io(int qid, uint32_t current_async, void * cookie) { if (true) { _nocheck__trace_qxl_interface_async_complete_io(qid, current_async, cookie); } } #define TRACE_QXL_INTERFACE_ATTACH_WORKER_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_ATTACH_WORKER) || \ false) static inline void _nocheck__trace_qxl_interface_attach_worker(int qid) { if (trace_event_get_state(TRACE_QXL_INTERFACE_ATTACH_WORKER) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 69 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_interface_attach_worker " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 2097 "trace/trace-hw_display.h" } else { #line 69 "../hw/display/trace-events" qemu_log("qxl_interface_attach_worker " "%d" "\n", qid); #line 2101 "trace/trace-hw_display.h" } } } static inline void trace_qxl_interface_attach_worker(int qid) { if (true) { _nocheck__trace_qxl_interface_attach_worker(qid); } } #define TRACE_QXL_INTERFACE_GET_INIT_INFO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_GET_INIT_INFO) || \ false) static inline void _nocheck__trace_qxl_interface_get_init_info(int qid) { if (trace_event_get_state(TRACE_QXL_INTERFACE_GET_INIT_INFO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 70 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_interface_get_init_info " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 2128 "trace/trace-hw_display.h" } else { #line 70 "../hw/display/trace-events" qemu_log("qxl_interface_get_init_info " "%d" "\n", qid); #line 2132 "trace/trace-hw_display.h" } } } static inline void trace_qxl_interface_get_init_info(int qid) { if (true) { _nocheck__trace_qxl_interface_get_init_info(qid); } } #define TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL) || \ false) static inline void _nocheck__trace_qxl_interface_set_compression_level(int qid, int64_t level) { if (trace_event_get_state(TRACE_QXL_INTERFACE_SET_COMPRESSION_LEVEL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 71 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_interface_set_compression_level " "%d %"PRId64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, level); #line 2159 "trace/trace-hw_display.h" } else { #line 71 "../hw/display/trace-events" qemu_log("qxl_interface_set_compression_level " "%d %"PRId64 "\n", qid, level); #line 2163 "trace/trace-hw_display.h" } } } static inline void trace_qxl_interface_set_compression_level(int qid, int64_t level) { if (true) { _nocheck__trace_qxl_interface_set_compression_level(qid, level); } } #define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE) || \ false) static inline void _nocheck__trace_qxl_interface_update_area_complete(int qid, uint32_t surface_id, uint32_t dirty_left, uint32_t dirty_right, uint32_t dirty_top, uint32_t dirty_bottom) { if (trace_event_get_state(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 72 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_interface_update_area_complete " "%d surface=%d [%d,%d,%d,%d]" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, surface_id, dirty_left, dirty_right, dirty_top, dirty_bottom); #line 2190 "trace/trace-hw_display.h" } else { #line 72 "../hw/display/trace-events" qemu_log("qxl_interface_update_area_complete " "%d surface=%d [%d,%d,%d,%d]" "\n", qid, surface_id, dirty_left, dirty_right, dirty_top, dirty_bottom); #line 2194 "trace/trace-hw_display.h" } } } static inline void trace_qxl_interface_update_area_complete(int qid, uint32_t surface_id, uint32_t dirty_left, uint32_t dirty_right, uint32_t dirty_top, uint32_t dirty_bottom) { if (true) { _nocheck__trace_qxl_interface_update_area_complete(qid, surface_id, dirty_left, dirty_right, dirty_top, dirty_bottom); } } #define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST) || \ false) static inline void _nocheck__trace_qxl_interface_update_area_complete_rest(int qid, uint32_t num_updated_rects) { if (trace_event_get_state(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_REST) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 73 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_interface_update_area_complete_rest " "%d #=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, num_updated_rects); #line 2221 "trace/trace-hw_display.h" } else { #line 73 "../hw/display/trace-events" qemu_log("qxl_interface_update_area_complete_rest " "%d #=%d" "\n", qid, num_updated_rects); #line 2225 "trace/trace-hw_display.h" } } } static inline void trace_qxl_interface_update_area_complete_rest(int qid, uint32_t num_updated_rects) { if (true) { _nocheck__trace_qxl_interface_update_area_complete_rest(qid, num_updated_rects); } } #define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW) || \ false) static inline void _nocheck__trace_qxl_interface_update_area_complete_overflow(int qid, int max) { if (trace_event_get_state(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_OVERFLOW) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 74 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_interface_update_area_complete_overflow " "%d max=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, max); #line 2252 "trace/trace-hw_display.h" } else { #line 74 "../hw/display/trace-events" qemu_log("qxl_interface_update_area_complete_overflow " "%d max=%d" "\n", qid, max); #line 2256 "trace/trace-hw_display.h" } } } static inline void trace_qxl_interface_update_area_complete_overflow(int qid, int max) { if (true) { _nocheck__trace_qxl_interface_update_area_complete_overflow(qid, max); } } #define TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH) || \ false) static inline void _nocheck__trace_qxl_interface_update_area_complete_schedule_bh(int qid, uint32_t num_dirty) { if (trace_event_get_state(TRACE_QXL_INTERFACE_UPDATE_AREA_COMPLETE_SCHEDULE_BH) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 75 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_interface_update_area_complete_schedule_bh " "%d #dirty=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, num_dirty); #line 2283 "trace/trace-hw_display.h" } else { #line 75 "../hw/display/trace-events" qemu_log("qxl_interface_update_area_complete_schedule_bh " "%d #dirty=%d" "\n", qid, num_dirty); #line 2287 "trace/trace-hw_display.h" } } } static inline void trace_qxl_interface_update_area_complete_schedule_bh(int qid, uint32_t num_dirty) { if (true) { _nocheck__trace_qxl_interface_update_area_complete_schedule_bh(qid, num_dirty); } } #define TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED) || \ false) static inline void _nocheck__trace_qxl_io_destroy_primary_ignored(int qid, const char * mode) { if (trace_event_get_state(TRACE_QXL_IO_DESTROY_PRIMARY_IGNORED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 76 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_io_destroy_primary_ignored " "%d %s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, mode); #line 2314 "trace/trace-hw_display.h" } else { #line 76 "../hw/display/trace-events" qemu_log("qxl_io_destroy_primary_ignored " "%d %s" "\n", qid, mode); #line 2318 "trace/trace-hw_display.h" } } } static inline void trace_qxl_io_destroy_primary_ignored(int qid, const char * mode) { if (true) { _nocheck__trace_qxl_io_destroy_primary_ignored(qid, mode); } } #define TRACE_QXL_IO_LOG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_IO_LOG) || \ false) static inline void _nocheck__trace_qxl_io_log(int qid, const char * log_buf) { if (trace_event_get_state(TRACE_QXL_IO_LOG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 77 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_io_log " "%d %s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, log_buf); #line 2345 "trace/trace-hw_display.h" } else { #line 77 "../hw/display/trace-events" qemu_log("qxl_io_log " "%d %s" "\n", qid, log_buf); #line 2349 "trace/trace-hw_display.h" } } } static inline void trace_qxl_io_log(int qid, const char * log_buf) { if (true) { _nocheck__trace_qxl_io_log(qid, log_buf); } } #define TRACE_QXL_IO_READ_UNEXPECTED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_IO_READ_UNEXPECTED) || \ false) static inline void _nocheck__trace_qxl_io_read_unexpected(int qid) { if (trace_event_get_state(TRACE_QXL_IO_READ_UNEXPECTED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 78 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_io_read_unexpected " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 2376 "trace/trace-hw_display.h" } else { #line 78 "../hw/display/trace-events" qemu_log("qxl_io_read_unexpected " "%d" "\n", qid); #line 2380 "trace/trace-hw_display.h" } } } static inline void trace_qxl_io_read_unexpected(int qid) { if (true) { _nocheck__trace_qxl_io_read_unexpected(qid); } } #define TRACE_QXL_IO_UNEXPECTED_VGA_MODE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_IO_UNEXPECTED_VGA_MODE) || \ false) static inline void _nocheck__trace_qxl_io_unexpected_vga_mode(int qid, uint64_t addr, uint64_t val, const char * desc) { if (trace_event_get_state(TRACE_QXL_IO_UNEXPECTED_VGA_MODE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 79 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_io_unexpected_vga_mode " "%d 0x%"PRIx64"=%"PRIu64" (%s)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, addr, val, desc); #line 2407 "trace/trace-hw_display.h" } else { #line 79 "../hw/display/trace-events" qemu_log("qxl_io_unexpected_vga_mode " "%d 0x%"PRIx64"=%"PRIu64" (%s)" "\n", qid, addr, val, desc); #line 2411 "trace/trace-hw_display.h" } } } static inline void trace_qxl_io_unexpected_vga_mode(int qid, uint64_t addr, uint64_t val, const char * desc) { if (true) { _nocheck__trace_qxl_io_unexpected_vga_mode(qid, addr, val, desc); } } #define TRACE_QXL_IO_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_IO_WRITE) || \ false) static inline void _nocheck__trace_qxl_io_write(int qid, const char * mode, uint64_t addr, const char * aname, uint64_t val, unsigned size, int async) { if (trace_event_get_state(TRACE_QXL_IO_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 80 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_io_write " "%d %s addr=%"PRIu64 " (%s) val=%"PRIu64" size=%u async=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, mode, addr, aname, val, size, async); #line 2438 "trace/trace-hw_display.h" } else { #line 80 "../hw/display/trace-events" qemu_log("qxl_io_write " "%d %s addr=%"PRIu64 " (%s) val=%"PRIu64" size=%u async=%d" "\n", qid, mode, addr, aname, val, size, async); #line 2442 "trace/trace-hw_display.h" } } } static inline void trace_qxl_io_write(int qid, const char * mode, uint64_t addr, const char * aname, uint64_t val, unsigned size, int async) { if (true) { _nocheck__trace_qxl_io_write(qid, mode, addr, aname, val, size, async); } } #define TRACE_QXL_MEMSLOT_ADD_GUEST_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_MEMSLOT_ADD_GUEST) || \ false) static inline void _nocheck__trace_qxl_memslot_add_guest(int qid, uint32_t slot_id, uint64_t guest_start, uint64_t guest_end) { if (trace_event_get_state(TRACE_QXL_MEMSLOT_ADD_GUEST) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 81 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_memslot_add_guest " "%d %u: guest phys 0x%"PRIx64 " - 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, slot_id, guest_start, guest_end); #line 2469 "trace/trace-hw_display.h" } else { #line 81 "../hw/display/trace-events" qemu_log("qxl_memslot_add_guest " "%d %u: guest phys 0x%"PRIx64 " - 0x%" PRIx64 "\n", qid, slot_id, guest_start, guest_end); #line 2473 "trace/trace-hw_display.h" } } } static inline void trace_qxl_memslot_add_guest(int qid, uint32_t slot_id, uint64_t guest_start, uint64_t guest_end) { if (true) { _nocheck__trace_qxl_memslot_add_guest(qid, slot_id, guest_start, guest_end); } } #define TRACE_QXL_POST_LOAD_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_POST_LOAD) || \ false) static inline void _nocheck__trace_qxl_post_load(int qid, const char * mode) { if (trace_event_get_state(TRACE_QXL_POST_LOAD) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 82 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_post_load " "%d %s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, mode); #line 2500 "trace/trace-hw_display.h" } else { #line 82 "../hw/display/trace-events" qemu_log("qxl_post_load " "%d %s" "\n", qid, mode); #line 2504 "trace/trace-hw_display.h" } } } static inline void trace_qxl_post_load(int qid, const char * mode) { if (true) { _nocheck__trace_qxl_post_load(qid, mode); } } #define TRACE_QXL_PRE_LOAD_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_PRE_LOAD) || \ false) static inline void _nocheck__trace_qxl_pre_load(int qid) { if (trace_event_get_state(TRACE_QXL_PRE_LOAD) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 83 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_pre_load " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 2531 "trace/trace-hw_display.h" } else { #line 83 "../hw/display/trace-events" qemu_log("qxl_pre_load " "%d" "\n", qid); #line 2535 "trace/trace-hw_display.h" } } } static inline void trace_qxl_pre_load(int qid) { if (true) { _nocheck__trace_qxl_pre_load(qid); } } #define TRACE_QXL_PRE_SAVE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_PRE_SAVE) || \ false) static inline void _nocheck__trace_qxl_pre_save(int qid) { if (trace_event_get_state(TRACE_QXL_PRE_SAVE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 84 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_pre_save " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 2562 "trace/trace-hw_display.h" } else { #line 84 "../hw/display/trace-events" qemu_log("qxl_pre_save " "%d" "\n", qid); #line 2566 "trace/trace-hw_display.h" } } } static inline void trace_qxl_pre_save(int qid) { if (true) { _nocheck__trace_qxl_pre_save(qid); } } #define TRACE_QXL_RESET_SURFACES_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RESET_SURFACES) || \ false) static inline void _nocheck__trace_qxl_reset_surfaces(int qid) { if (trace_event_get_state(TRACE_QXL_RESET_SURFACES) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 85 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_reset_surfaces " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 2593 "trace/trace-hw_display.h" } else { #line 85 "../hw/display/trace-events" qemu_log("qxl_reset_surfaces " "%d" "\n", qid); #line 2597 "trace/trace-hw_display.h" } } } static inline void trace_qxl_reset_surfaces(int qid) { if (true) { _nocheck__trace_qxl_reset_surfaces(qid); } } #define TRACE_QXL_RING_COMMAND_CHECK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_COMMAND_CHECK) || \ false) static inline void _nocheck__trace_qxl_ring_command_check(int qid, const char * mode) { if (trace_event_get_state(TRACE_QXL_RING_COMMAND_CHECK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 86 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_ring_command_check " "%d %s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, mode); #line 2624 "trace/trace-hw_display.h" } else { #line 86 "../hw/display/trace-events" qemu_log("qxl_ring_command_check " "%d %s" "\n", qid, mode); #line 2628 "trace/trace-hw_display.h" } } } static inline void trace_qxl_ring_command_check(int qid, const char * mode) { if (true) { _nocheck__trace_qxl_ring_command_check(qid, mode); } } #define TRACE_QXL_RING_COMMAND_GET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_COMMAND_GET) || \ false) static inline void _nocheck__trace_qxl_ring_command_get(int qid, const char * mode) { if (trace_event_get_state(TRACE_QXL_RING_COMMAND_GET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 87 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_ring_command_get " "%d %s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, mode); #line 2655 "trace/trace-hw_display.h" } else { #line 87 "../hw/display/trace-events" qemu_log("qxl_ring_command_get " "%d %s" "\n", qid, mode); #line 2659 "trace/trace-hw_display.h" } } } static inline void trace_qxl_ring_command_get(int qid, const char * mode) { if (true) { _nocheck__trace_qxl_ring_command_get(qid, mode); } } #define TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION) || \ false) static inline void _nocheck__trace_qxl_ring_command_req_notification(int qid) { if (trace_event_get_state(TRACE_QXL_RING_COMMAND_REQ_NOTIFICATION) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 88 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_ring_command_req_notification " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 2686 "trace/trace-hw_display.h" } else { #line 88 "../hw/display/trace-events" qemu_log("qxl_ring_command_req_notification " "%d" "\n", qid); #line 2690 "trace/trace-hw_display.h" } } } static inline void trace_qxl_ring_command_req_notification(int qid) { if (true) { _nocheck__trace_qxl_ring_command_req_notification(qid); } } #define TRACE_QXL_RING_CURSOR_CHECK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_CURSOR_CHECK) || \ false) static inline void _nocheck__trace_qxl_ring_cursor_check(int qid, const char * mode) { if (trace_event_get_state(TRACE_QXL_RING_CURSOR_CHECK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 89 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_ring_cursor_check " "%d %s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, mode); #line 2717 "trace/trace-hw_display.h" } else { #line 89 "../hw/display/trace-events" qemu_log("qxl_ring_cursor_check " "%d %s" "\n", qid, mode); #line 2721 "trace/trace-hw_display.h" } } } static inline void trace_qxl_ring_cursor_check(int qid, const char * mode) { if (true) { _nocheck__trace_qxl_ring_cursor_check(qid, mode); } } #define TRACE_QXL_RING_CURSOR_GET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_CURSOR_GET) || \ false) static inline void _nocheck__trace_qxl_ring_cursor_get(int qid, const char * mode) { if (trace_event_get_state(TRACE_QXL_RING_CURSOR_GET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 90 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_ring_cursor_get " "%d %s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, mode); #line 2748 "trace/trace-hw_display.h" } else { #line 90 "../hw/display/trace-events" qemu_log("qxl_ring_cursor_get " "%d %s" "\n", qid, mode); #line 2752 "trace/trace-hw_display.h" } } } static inline void trace_qxl_ring_cursor_get(int qid, const char * mode) { if (true) { _nocheck__trace_qxl_ring_cursor_get(qid, mode); } } #define TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION) || \ false) static inline void _nocheck__trace_qxl_ring_cursor_req_notification(int qid) { if (trace_event_get_state(TRACE_QXL_RING_CURSOR_REQ_NOTIFICATION) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 91 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_ring_cursor_req_notification " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 2779 "trace/trace-hw_display.h" } else { #line 91 "../hw/display/trace-events" qemu_log("qxl_ring_cursor_req_notification " "%d" "\n", qid); #line 2783 "trace/trace-hw_display.h" } } } static inline void trace_qxl_ring_cursor_req_notification(int qid) { if (true) { _nocheck__trace_qxl_ring_cursor_req_notification(qid); } } #define TRACE_QXL_RING_RES_PUSH_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_RES_PUSH) || \ false) static inline void _nocheck__trace_qxl_ring_res_push(int qid, const char * mode, uint32_t surface_count, uint32_t free_res, void * last_release, const char * notify) { if (trace_event_get_state(TRACE_QXL_RING_RES_PUSH) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 92 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_ring_res_push " "%d %s s#=%d res#=%d last=%p notify=%s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, mode, surface_count, free_res, last_release, notify); #line 2810 "trace/trace-hw_display.h" } else { #line 92 "../hw/display/trace-events" qemu_log("qxl_ring_res_push " "%d %s s#=%d res#=%d last=%p notify=%s" "\n", qid, mode, surface_count, free_res, last_release, notify); #line 2814 "trace/trace-hw_display.h" } } } static inline void trace_qxl_ring_res_push(int qid, const char * mode, uint32_t surface_count, uint32_t free_res, void * last_release, const char * notify) { if (true) { _nocheck__trace_qxl_ring_res_push(qid, mode, surface_count, free_res, last_release, notify); } } #define TRACE_QXL_RING_RES_PUSH_REST_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_RES_PUSH_REST) || \ false) static inline void _nocheck__trace_qxl_ring_res_push_rest(int qid, uint32_t ring_has, uint32_t ring_size, uint32_t prod, uint32_t cons) { if (trace_event_get_state(TRACE_QXL_RING_RES_PUSH_REST) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 93 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_ring_res_push_rest " "%d ring %d/%d [%d,%d]" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, ring_has, ring_size, prod, cons); #line 2841 "trace/trace-hw_display.h" } else { #line 93 "../hw/display/trace-events" qemu_log("qxl_ring_res_push_rest " "%d ring %d/%d [%d,%d]" "\n", qid, ring_has, ring_size, prod, cons); #line 2845 "trace/trace-hw_display.h" } } } static inline void trace_qxl_ring_res_push_rest(int qid, uint32_t ring_has, uint32_t ring_size, uint32_t prod, uint32_t cons) { if (true) { _nocheck__trace_qxl_ring_res_push_rest(qid, ring_has, ring_size, prod, cons); } } #define TRACE_QXL_RING_RES_PUT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RING_RES_PUT) || \ false) static inline void _nocheck__trace_qxl_ring_res_put(int qid, uint32_t free_res) { if (trace_event_get_state(TRACE_QXL_RING_RES_PUT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 94 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_ring_res_put " "%d #res=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, free_res); #line 2872 "trace/trace-hw_display.h" } else { #line 94 "../hw/display/trace-events" qemu_log("qxl_ring_res_put " "%d #res=%d" "\n", qid, free_res); #line 2876 "trace/trace-hw_display.h" } } } static inline void trace_qxl_ring_res_put(int qid, uint32_t free_res) { if (true) { _nocheck__trace_qxl_ring_res_put(qid, free_res); } } #define TRACE_QXL_SET_MODE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SET_MODE) || \ false) static inline void _nocheck__trace_qxl_set_mode(int qid, int modenr, uint32_t x_res, uint32_t y_res, uint32_t bits, uint64_t devmem) { if (trace_event_get_state(TRACE_QXL_SET_MODE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 95 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_set_mode " "%d mode=%d [ x=%d y=%d @ bpp=%d devmem=0x%" PRIx64 " ]" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, modenr, x_res, y_res, bits, devmem); #line 2903 "trace/trace-hw_display.h" } else { #line 95 "../hw/display/trace-events" qemu_log("qxl_set_mode " "%d mode=%d [ x=%d y=%d @ bpp=%d devmem=0x%" PRIx64 " ]" "\n", qid, modenr, x_res, y_res, bits, devmem); #line 2907 "trace/trace-hw_display.h" } } } static inline void trace_qxl_set_mode(int qid, int modenr, uint32_t x_res, uint32_t y_res, uint32_t bits, uint64_t devmem) { if (true) { _nocheck__trace_qxl_set_mode(qid, modenr, x_res, y_res, bits, devmem); } } #define TRACE_QXL_SOFT_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SOFT_RESET) || \ false) static inline void _nocheck__trace_qxl_soft_reset(int qid) { if (trace_event_get_state(TRACE_QXL_SOFT_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 96 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_soft_reset " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 2934 "trace/trace-hw_display.h" } else { #line 96 "../hw/display/trace-events" qemu_log("qxl_soft_reset " "%d" "\n", qid); #line 2938 "trace/trace-hw_display.h" } } } static inline void trace_qxl_soft_reset(int qid) { if (true) { _nocheck__trace_qxl_soft_reset(qid); } } #define TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE) || \ false) static inline void _nocheck__trace_qxl_spice_destroy_surfaces_complete(int qid) { if (trace_event_get_state(TRACE_QXL_SPICE_DESTROY_SURFACES_COMPLETE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 97 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_destroy_surfaces_complete " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 2965 "trace/trace-hw_display.h" } else { #line 97 "../hw/display/trace-events" qemu_log("qxl_spice_destroy_surfaces_complete " "%d" "\n", qid); #line 2969 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_destroy_surfaces_complete(int qid) { if (true) { _nocheck__trace_qxl_spice_destroy_surfaces_complete(qid); } } #define TRACE_QXL_SPICE_DESTROY_SURFACES_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_DESTROY_SURFACES) || \ false) static inline void _nocheck__trace_qxl_spice_destroy_surfaces(int qid, int async) { if (trace_event_get_state(TRACE_QXL_SPICE_DESTROY_SURFACES) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 98 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_destroy_surfaces " "%d async=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, async); #line 2996 "trace/trace-hw_display.h" } else { #line 98 "../hw/display/trace-events" qemu_log("qxl_spice_destroy_surfaces " "%d async=%d" "\n", qid, async); #line 3000 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_destroy_surfaces(int qid, int async) { if (true) { _nocheck__trace_qxl_spice_destroy_surfaces(qid, async); } } #define TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE) || \ false) static inline void _nocheck__trace_qxl_spice_destroy_surface_wait_complete(int qid, uint32_t id) { if (trace_event_get_state(TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_COMPLETE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 99 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_destroy_surface_wait_complete " "%d sid=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, id); #line 3027 "trace/trace-hw_display.h" } else { #line 99 "../hw/display/trace-events" qemu_log("qxl_spice_destroy_surface_wait_complete " "%d sid=%d" "\n", qid, id); #line 3031 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_destroy_surface_wait_complete(int qid, uint32_t id) { if (true) { _nocheck__trace_qxl_spice_destroy_surface_wait_complete(qid, id); } } #define TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT) || \ false) static inline void _nocheck__trace_qxl_spice_destroy_surface_wait(int qid, uint32_t id, int async) { if (trace_event_get_state(TRACE_QXL_SPICE_DESTROY_SURFACE_WAIT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 100 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_destroy_surface_wait " "%d sid=%d async=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, id, async); #line 3058 "trace/trace-hw_display.h" } else { #line 100 "../hw/display/trace-events" qemu_log("qxl_spice_destroy_surface_wait " "%d sid=%d async=%d" "\n", qid, id, async); #line 3062 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_destroy_surface_wait(int qid, uint32_t id, int async) { if (true) { _nocheck__trace_qxl_spice_destroy_surface_wait(qid, id, async); } } #define TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC) || \ false) static inline void _nocheck__trace_qxl_spice_flush_surfaces_async(int qid, uint32_t surface_count, uint32_t num_free_res) { if (trace_event_get_state(TRACE_QXL_SPICE_FLUSH_SURFACES_ASYNC) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 101 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_flush_surfaces_async " "%d s#=%d, res#=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, surface_count, num_free_res); #line 3089 "trace/trace-hw_display.h" } else { #line 101 "../hw/display/trace-events" qemu_log("qxl_spice_flush_surfaces_async " "%d s#=%d, res#=%d" "\n", qid, surface_count, num_free_res); #line 3093 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_flush_surfaces_async(int qid, uint32_t surface_count, uint32_t num_free_res) { if (true) { _nocheck__trace_qxl_spice_flush_surfaces_async(qid, surface_count, num_free_res); } } #define TRACE_QXL_SPICE_MONITORS_CONFIG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_MONITORS_CONFIG) || \ false) static inline void _nocheck__trace_qxl_spice_monitors_config(int qid) { if (trace_event_get_state(TRACE_QXL_SPICE_MONITORS_CONFIG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 102 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_monitors_config " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 3120 "trace/trace-hw_display.h" } else { #line 102 "../hw/display/trace-events" qemu_log("qxl_spice_monitors_config " "%d" "\n", qid); #line 3124 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_monitors_config(int qid) { if (true) { _nocheck__trace_qxl_spice_monitors_config(qid); } } #define TRACE_QXL_SPICE_LOADVM_COMMANDS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_LOADVM_COMMANDS) || \ false) static inline void _nocheck__trace_qxl_spice_loadvm_commands(int qid, void * ext, uint32_t count) { if (trace_event_get_state(TRACE_QXL_SPICE_LOADVM_COMMANDS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 103 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_loadvm_commands " "%d ext=%p count=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, ext, count); #line 3151 "trace/trace-hw_display.h" } else { #line 103 "../hw/display/trace-events" qemu_log("qxl_spice_loadvm_commands " "%d ext=%p count=%d" "\n", qid, ext, count); #line 3155 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_loadvm_commands(int qid, void * ext, uint32_t count) { if (true) { _nocheck__trace_qxl_spice_loadvm_commands(qid, ext, count); } } #define TRACE_QXL_SPICE_OOM_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_OOM) || \ false) static inline void _nocheck__trace_qxl_spice_oom(int qid) { if (trace_event_get_state(TRACE_QXL_SPICE_OOM) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 104 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_oom " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 3182 "trace/trace-hw_display.h" } else { #line 104 "../hw/display/trace-events" qemu_log("qxl_spice_oom " "%d" "\n", qid); #line 3186 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_oom(int qid) { if (true) { _nocheck__trace_qxl_spice_oom(qid); } } #define TRACE_QXL_SPICE_RESET_CURSOR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_RESET_CURSOR) || \ false) static inline void _nocheck__trace_qxl_spice_reset_cursor(int qid) { if (trace_event_get_state(TRACE_QXL_SPICE_RESET_CURSOR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 105 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_reset_cursor " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 3213 "trace/trace-hw_display.h" } else { #line 105 "../hw/display/trace-events" qemu_log("qxl_spice_reset_cursor " "%d" "\n", qid); #line 3217 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_reset_cursor(int qid) { if (true) { _nocheck__trace_qxl_spice_reset_cursor(qid); } } #define TRACE_QXL_SPICE_RESET_IMAGE_CACHE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_RESET_IMAGE_CACHE) || \ false) static inline void _nocheck__trace_qxl_spice_reset_image_cache(int qid) { if (trace_event_get_state(TRACE_QXL_SPICE_RESET_IMAGE_CACHE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 106 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_reset_image_cache " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 3244 "trace/trace-hw_display.h" } else { #line 106 "../hw/display/trace-events" qemu_log("qxl_spice_reset_image_cache " "%d" "\n", qid); #line 3248 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_reset_image_cache(int qid) { if (true) { _nocheck__trace_qxl_spice_reset_image_cache(qid); } } #define TRACE_QXL_SPICE_RESET_MEMSLOTS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_RESET_MEMSLOTS) || \ false) static inline void _nocheck__trace_qxl_spice_reset_memslots(int qid) { if (trace_event_get_state(TRACE_QXL_SPICE_RESET_MEMSLOTS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 107 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_reset_memslots " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 3275 "trace/trace-hw_display.h" } else { #line 107 "../hw/display/trace-events" qemu_log("qxl_spice_reset_memslots " "%d" "\n", qid); #line 3279 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_reset_memslots(int qid) { if (true) { _nocheck__trace_qxl_spice_reset_memslots(qid); } } #define TRACE_QXL_SPICE_UPDATE_AREA_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_UPDATE_AREA) || \ false) static inline void _nocheck__trace_qxl_spice_update_area(int qid, uint32_t surface_id, uint32_t left, uint32_t right, uint32_t top, uint32_t bottom) { if (trace_event_get_state(TRACE_QXL_SPICE_UPDATE_AREA) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 108 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_update_area " "%d sid=%d [%d,%d,%d,%d]" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, surface_id, left, right, top, bottom); #line 3306 "trace/trace-hw_display.h" } else { #line 108 "../hw/display/trace-events" qemu_log("qxl_spice_update_area " "%d sid=%d [%d,%d,%d,%d]" "\n", qid, surface_id, left, right, top, bottom); #line 3310 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_update_area(int qid, uint32_t surface_id, uint32_t left, uint32_t right, uint32_t top, uint32_t bottom) { if (true) { _nocheck__trace_qxl_spice_update_area(qid, surface_id, left, right, top, bottom); } } #define TRACE_QXL_SPICE_UPDATE_AREA_REST_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SPICE_UPDATE_AREA_REST) || \ false) static inline void _nocheck__trace_qxl_spice_update_area_rest(int qid, uint32_t num_dirty_rects, uint32_t clear_dirty_region) { if (trace_event_get_state(TRACE_QXL_SPICE_UPDATE_AREA_REST) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 109 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_spice_update_area_rest " "%d #d=%d clear=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, num_dirty_rects, clear_dirty_region); #line 3337 "trace/trace-hw_display.h" } else { #line 109 "../hw/display/trace-events" qemu_log("qxl_spice_update_area_rest " "%d #d=%d clear=%d" "\n", qid, num_dirty_rects, clear_dirty_region); #line 3341 "trace/trace-hw_display.h" } } } static inline void trace_qxl_spice_update_area_rest(int qid, uint32_t num_dirty_rects, uint32_t clear_dirty_region) { if (true) { _nocheck__trace_qxl_spice_update_area_rest(qid, num_dirty_rects, clear_dirty_region); } } #define TRACE_QXL_SURFACES_DIRTY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SURFACES_DIRTY) || \ false) static inline void _nocheck__trace_qxl_surfaces_dirty(int qid, uint64_t offset, uint64_t size) { if (trace_event_get_state(TRACE_QXL_SURFACES_DIRTY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 110 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_surfaces_dirty " "%d offset=0x%"PRIx64" size=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, offset, size); #line 3368 "trace/trace-hw_display.h" } else { #line 110 "../hw/display/trace-events" qemu_log("qxl_surfaces_dirty " "%d offset=0x%"PRIx64" size=0x%"PRIx64 "\n", qid, offset, size); #line 3372 "trace/trace-hw_display.h" } } } static inline void trace_qxl_surfaces_dirty(int qid, uint64_t offset, uint64_t size) { if (true) { _nocheck__trace_qxl_surfaces_dirty(qid, offset, size); } } #define TRACE_QXL_SEND_EVENTS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SEND_EVENTS) || \ false) static inline void _nocheck__trace_qxl_send_events(int qid, uint32_t events) { if (trace_event_get_state(TRACE_QXL_SEND_EVENTS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 111 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_send_events " "%d %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, events); #line 3399 "trace/trace-hw_display.h" } else { #line 111 "../hw/display/trace-events" qemu_log("qxl_send_events " "%d %d" "\n", qid, events); #line 3403 "trace/trace-hw_display.h" } } } static inline void trace_qxl_send_events(int qid, uint32_t events) { if (true) { _nocheck__trace_qxl_send_events(qid, events); } } #define TRACE_QXL_SEND_EVENTS_VM_STOPPED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SEND_EVENTS_VM_STOPPED) || \ false) static inline void _nocheck__trace_qxl_send_events_vm_stopped(int qid, uint32_t events) { if (trace_event_get_state(TRACE_QXL_SEND_EVENTS_VM_STOPPED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 112 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_send_events_vm_stopped " "%d %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, events); #line 3430 "trace/trace-hw_display.h" } else { #line 112 "../hw/display/trace-events" qemu_log("qxl_send_events_vm_stopped " "%d %d" "\n", qid, events); #line 3434 "trace/trace-hw_display.h" } } } static inline void trace_qxl_send_events_vm_stopped(int qid, uint32_t events) { if (true) { _nocheck__trace_qxl_send_events_vm_stopped(qid, events); } } #define TRACE_QXL_SET_GUEST_BUG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SET_GUEST_BUG) || \ false) static inline void _nocheck__trace_qxl_set_guest_bug(int qid) { if (trace_event_get_state(TRACE_QXL_SET_GUEST_BUG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 113 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_set_guest_bug " "%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid); #line 3461 "trace/trace-hw_display.h" } else { #line 113 "../hw/display/trace-events" qemu_log("qxl_set_guest_bug " "%d" "\n", qid); #line 3465 "trace/trace-hw_display.h" } } } static inline void trace_qxl_set_guest_bug(int qid) { if (true) { _nocheck__trace_qxl_set_guest_bug(qid); } } #define TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG) || \ false) static inline void _nocheck__trace_qxl_interrupt_client_monitors_config(int qid, int num_heads, void * heads) { if (trace_event_get_state(TRACE_QXL_INTERRUPT_CLIENT_MONITORS_CONFIG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 114 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_interrupt_client_monitors_config " "%d %d %p" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, num_heads, heads); #line 3492 "trace/trace-hw_display.h" } else { #line 114 "../hw/display/trace-events" qemu_log("qxl_interrupt_client_monitors_config " "%d %d %p" "\n", qid, num_heads, heads); #line 3496 "trace/trace-hw_display.h" } } } static inline void trace_qxl_interrupt_client_monitors_config(int qid, int num_heads, void * heads) { if (true) { _nocheck__trace_qxl_interrupt_client_monitors_config(qid, num_heads, heads); } } #define TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST) || \ false) static inline void _nocheck__trace_qxl_client_monitors_config_unsupported_by_guest(int qid, uint32_t int_mask, void * client_monitors_config) { if (trace_event_get_state(TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_GUEST) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 115 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_client_monitors_config_unsupported_by_guest " "%d 0x%X %p" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, int_mask, client_monitors_config); #line 3523 "trace/trace-hw_display.h" } else { #line 115 "../hw/display/trace-events" qemu_log("qxl_client_monitors_config_unsupported_by_guest " "%d 0x%X %p" "\n", qid, int_mask, client_monitors_config); #line 3527 "trace/trace-hw_display.h" } } } static inline void trace_qxl_client_monitors_config_unsupported_by_guest(int qid, uint32_t int_mask, void * client_monitors_config) { if (true) { _nocheck__trace_qxl_client_monitors_config_unsupported_by_guest(qid, int_mask, client_monitors_config); } } #define TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE) || \ false) static inline void _nocheck__trace_qxl_client_monitors_config_unsupported_by_device(int qid, int revision) { if (trace_event_get_state(TRACE_QXL_CLIENT_MONITORS_CONFIG_UNSUPPORTED_BY_DEVICE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 116 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_client_monitors_config_unsupported_by_device " "%d revision=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, revision); #line 3554 "trace/trace-hw_display.h" } else { #line 116 "../hw/display/trace-events" qemu_log("qxl_client_monitors_config_unsupported_by_device " "%d revision=%d" "\n", qid, revision); #line 3558 "trace/trace-hw_display.h" } } } static inline void trace_qxl_client_monitors_config_unsupported_by_device(int qid, int revision) { if (true) { _nocheck__trace_qxl_client_monitors_config_unsupported_by_device(qid, revision); } } #define TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED) || \ false) static inline void _nocheck__trace_qxl_client_monitors_config_capped(int qid, int requested, int limit) { if (trace_event_get_state(TRACE_QXL_CLIENT_MONITORS_CONFIG_CAPPED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 117 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_client_monitors_config_capped " "%d %d %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, requested, limit); #line 3585 "trace/trace-hw_display.h" } else { #line 117 "../hw/display/trace-events" qemu_log("qxl_client_monitors_config_capped " "%d %d %d" "\n", qid, requested, limit); #line 3589 "trace/trace-hw_display.h" } } } static inline void trace_qxl_client_monitors_config_capped(int qid, int requested, int limit) { if (true) { _nocheck__trace_qxl_client_monitors_config_capped(qid, requested, limit); } } #define TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC) || \ false) static inline void _nocheck__trace_qxl_client_monitors_config_crc(int qid, unsigned size, uint32_t crc32) { if (trace_event_get_state(TRACE_QXL_CLIENT_MONITORS_CONFIG_CRC) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 118 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_client_monitors_config_crc " "%d %u %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, size, crc32); #line 3616 "trace/trace-hw_display.h" } else { #line 118 "../hw/display/trace-events" qemu_log("qxl_client_monitors_config_crc " "%d %u %u" "\n", qid, size, crc32); #line 3620 "trace/trace-hw_display.h" } } } static inline void trace_qxl_client_monitors_config_crc(int qid, unsigned size, uint32_t crc32) { if (true) { _nocheck__trace_qxl_client_monitors_config_crc(qid, size, crc32); } } #define TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION) || \ false) static inline void _nocheck__trace_qxl_set_client_capabilities_unsupported_by_revision(int qid, int revision) { if (trace_event_get_state(TRACE_QXL_SET_CLIENT_CAPABILITIES_UNSUPPORTED_BY_REVISION) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 119 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_set_client_capabilities_unsupported_by_revision " "%d revision=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , qid, revision); #line 3647 "trace/trace-hw_display.h" } else { #line 119 "../hw/display/trace-events" qemu_log("qxl_set_client_capabilities_unsupported_by_revision " "%d revision=%d" "\n", qid, revision); #line 3651 "trace/trace-hw_display.h" } } } static inline void trace_qxl_set_client_capabilities_unsupported_by_revision(int qid, int revision) { if (true) { _nocheck__trace_qxl_set_client_capabilities_unsupported_by_revision(qid, revision); } } #define TRACE_QXL_RENDER_BLIT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RENDER_BLIT) || \ false) static inline void _nocheck__trace_qxl_render_blit(int32_t stride, int32_t left, int32_t right, int32_t top, int32_t bottom) { if (trace_event_get_state(TRACE_QXL_RENDER_BLIT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 122 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_render_blit " "stride=%d [%d, %d, %d, %d]" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , stride, left, right, top, bottom); #line 3678 "trace/trace-hw_display.h" } else { #line 122 "../hw/display/trace-events" qemu_log("qxl_render_blit " "stride=%d [%d, %d, %d, %d]" "\n", stride, left, right, top, bottom); #line 3682 "trace/trace-hw_display.h" } } } static inline void trace_qxl_render_blit(int32_t stride, int32_t left, int32_t right, int32_t top, int32_t bottom) { if (true) { _nocheck__trace_qxl_render_blit(stride, left, right, top, bottom); } } #define TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED) || \ false) static inline void _nocheck__trace_qxl_render_guest_primary_resized(int32_t width, int32_t height, int32_t stride, int32_t bytes_pp, int32_t bits_pp) { if (trace_event_get_state(TRACE_QXL_RENDER_GUEST_PRIMARY_RESIZED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 123 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_render_guest_primary_resized " "%dx%d, stride %d, bpp %d, depth %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , width, height, stride, bytes_pp, bits_pp); #line 3709 "trace/trace-hw_display.h" } else { #line 123 "../hw/display/trace-events" qemu_log("qxl_render_guest_primary_resized " "%dx%d, stride %d, bpp %d, depth %d" "\n", width, height, stride, bytes_pp, bits_pp); #line 3713 "trace/trace-hw_display.h" } } } static inline void trace_qxl_render_guest_primary_resized(int32_t width, int32_t height, int32_t stride, int32_t bytes_pp, int32_t bits_pp) { if (true) { _nocheck__trace_qxl_render_guest_primary_resized(width, height, stride, bytes_pp, bits_pp); } } #define TRACE_QXL_RENDER_UPDATE_AREA_DONE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QXL_RENDER_UPDATE_AREA_DONE) || \ false) static inline void _nocheck__trace_qxl_render_update_area_done(void * cookie) { if (trace_event_get_state(TRACE_QXL_RENDER_UPDATE_AREA_DONE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 124 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:qxl_render_update_area_done " "%p" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cookie); #line 3740 "trace/trace-hw_display.h" } else { #line 124 "../hw/display/trace-events" qemu_log("qxl_render_update_area_done " "%p" "\n", cookie); #line 3744 "trace/trace-hw_display.h" } } } static inline void trace_qxl_render_update_area_done(void * cookie) { if (true) { _nocheck__trace_qxl_render_update_area_done(cookie); } } #define TRACE_VGA_STD_READ_IO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VGA_STD_READ_IO) || \ false) static inline void _nocheck__trace_vga_std_read_io(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_VGA_STD_READ_IO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 127 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vga_std_read_io " "addr 0x%x, val 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 3771 "trace/trace-hw_display.h" } else { #line 127 "../hw/display/trace-events" qemu_log("vga_std_read_io " "addr 0x%x, val 0x%x" "\n", addr, val); #line 3775 "trace/trace-hw_display.h" } } } static inline void trace_vga_std_read_io(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_vga_std_read_io(addr, val); } } #define TRACE_VGA_STD_WRITE_IO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VGA_STD_WRITE_IO) || \ false) static inline void _nocheck__trace_vga_std_write_io(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_VGA_STD_WRITE_IO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 128 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vga_std_write_io " "addr 0x%x, val 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 3802 "trace/trace-hw_display.h" } else { #line 128 "../hw/display/trace-events" qemu_log("vga_std_write_io " "addr 0x%x, val 0x%x" "\n", addr, val); #line 3806 "trace/trace-hw_display.h" } } } static inline void trace_vga_std_write_io(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_vga_std_write_io(addr, val); } } #define TRACE_VGA_VBE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VGA_VBE_READ) || \ false) static inline void _nocheck__trace_vga_vbe_read(uint32_t index, uint32_t val) { if (trace_event_get_state(TRACE_VGA_VBE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 129 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vga_vbe_read " "index 0x%x, val 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, val); #line 3833 "trace/trace-hw_display.h" } else { #line 129 "../hw/display/trace-events" qemu_log("vga_vbe_read " "index 0x%x, val 0x%x" "\n", index, val); #line 3837 "trace/trace-hw_display.h" } } } static inline void trace_vga_vbe_read(uint32_t index, uint32_t val) { if (true) { _nocheck__trace_vga_vbe_read(index, val); } } #define TRACE_VGA_VBE_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VGA_VBE_WRITE) || \ false) static inline void _nocheck__trace_vga_vbe_write(uint32_t index, uint32_t val) { if (trace_event_get_state(TRACE_VGA_VBE_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 130 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vga_vbe_write " "index 0x%x, val 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, val); #line 3864 "trace/trace-hw_display.h" } else { #line 130 "../hw/display/trace-events" qemu_log("vga_vbe_write " "index 0x%x, val 0x%x" "\n", index, val); #line 3868 "trace/trace-hw_display.h" } } } static inline void trace_vga_vbe_write(uint32_t index, uint32_t val) { if (true) { _nocheck__trace_vga_vbe_write(index, val); } } #define TRACE_VGA_CIRRUS_READ_IO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VGA_CIRRUS_READ_IO) || \ false) static inline void _nocheck__trace_vga_cirrus_read_io(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_VGA_CIRRUS_READ_IO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 133 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vga_cirrus_read_io " "addr 0x%x, val 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 3895 "trace/trace-hw_display.h" } else { #line 133 "../hw/display/trace-events" qemu_log("vga_cirrus_read_io " "addr 0x%x, val 0x%x" "\n", addr, val); #line 3899 "trace/trace-hw_display.h" } } } static inline void trace_vga_cirrus_read_io(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_vga_cirrus_read_io(addr, val); } } #define TRACE_VGA_CIRRUS_WRITE_IO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VGA_CIRRUS_WRITE_IO) || \ false) static inline void _nocheck__trace_vga_cirrus_write_io(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_VGA_CIRRUS_WRITE_IO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 134 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vga_cirrus_write_io " "addr 0x%x, val 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 3926 "trace/trace-hw_display.h" } else { #line 134 "../hw/display/trace-events" qemu_log("vga_cirrus_write_io " "addr 0x%x, val 0x%x" "\n", addr, val); #line 3930 "trace/trace-hw_display.h" } } } static inline void trace_vga_cirrus_write_io(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_vga_cirrus_write_io(addr, val); } } #define TRACE_VGA_CIRRUS_WRITE_BLT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VGA_CIRRUS_WRITE_BLT) || \ false) static inline void _nocheck__trace_vga_cirrus_write_blt(uint32_t offset, uint32_t val) { if (trace_event_get_state(TRACE_VGA_CIRRUS_WRITE_BLT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 135 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vga_cirrus_write_blt " "offset 0x%x, val 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, val); #line 3957 "trace/trace-hw_display.h" } else { #line 135 "../hw/display/trace-events" qemu_log("vga_cirrus_write_blt " "offset 0x%x, val 0x%x" "\n", offset, val); #line 3961 "trace/trace-hw_display.h" } } } static inline void trace_vga_cirrus_write_blt(uint32_t offset, uint32_t val) { if (true) { _nocheck__trace_vga_cirrus_write_blt(offset, val); } } #define TRACE_VGA_CIRRUS_WRITE_GR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VGA_CIRRUS_WRITE_GR) || \ false) static inline void _nocheck__trace_vga_cirrus_write_gr(uint8_t index, uint8_t val) { if (trace_event_get_state(TRACE_VGA_CIRRUS_WRITE_GR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 136 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vga_cirrus_write_gr " "GR addr 0x%02x, val 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, val); #line 3988 "trace/trace-hw_display.h" } else { #line 136 "../hw/display/trace-events" qemu_log("vga_cirrus_write_gr " "GR addr 0x%02x, val 0x%02x" "\n", index, val); #line 3992 "trace/trace-hw_display.h" } } } static inline void trace_vga_cirrus_write_gr(uint8_t index, uint8_t val) { if (true) { _nocheck__trace_vga_cirrus_write_gr(index, val); } } #define TRACE_VGA_CIRRUS_BITBLT_START_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VGA_CIRRUS_BITBLT_START) || \ false) static inline void _nocheck__trace_vga_cirrus_bitblt_start(uint8_t blt_rop, uint8_t blt_mode, uint8_t blt_modeext, int blt_width, int blt_height, int blt_dstpitch, int blt_srcpitch, uint32_t blt_dstaddr, uint32_t blt_srcaddr, uint8_t gr_val) { if (trace_event_get_state(TRACE_VGA_CIRRUS_BITBLT_START) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 137 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:vga_cirrus_bitblt_start " "rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08"PRIx32" saddr=0x%08"PRIx32" writemask=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , blt_rop, blt_mode, blt_modeext, blt_width, blt_height, blt_dstpitch, blt_srcpitch, blt_dstaddr, blt_srcaddr, gr_val); #line 4019 "trace/trace-hw_display.h" } else { #line 137 "../hw/display/trace-events" qemu_log("vga_cirrus_bitblt_start " "rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08"PRIx32" saddr=0x%08"PRIx32" writemask=0x%02x" "\n", blt_rop, blt_mode, blt_modeext, blt_width, blt_height, blt_dstpitch, blt_srcpitch, blt_dstaddr, blt_srcaddr, gr_val); #line 4023 "trace/trace-hw_display.h" } } } static inline void trace_vga_cirrus_bitblt_start(uint8_t blt_rop, uint8_t blt_mode, uint8_t blt_modeext, int blt_width, int blt_height, int blt_dstpitch, int blt_srcpitch, uint32_t blt_dstaddr, uint32_t blt_srcaddr, uint8_t gr_val) { if (true) { _nocheck__trace_vga_cirrus_bitblt_start(blt_rop, blt_mode, blt_modeext, blt_width, blt_height, blt_dstpitch, blt_srcpitch, blt_dstaddr, blt_srcaddr, gr_val); } } #define TRACE_SII9022_READ_REG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SII9022_READ_REG) || \ false) static inline void _nocheck__trace_sii9022_read_reg(uint8_t addr, uint8_t val) { if (trace_event_get_state(TRACE_SII9022_READ_REG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 140 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sii9022_read_reg " "addr 0x%02x, val 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4050 "trace/trace-hw_display.h" } else { #line 140 "../hw/display/trace-events" qemu_log("sii9022_read_reg " "addr 0x%02x, val 0x%02x" "\n", addr, val); #line 4054 "trace/trace-hw_display.h" } } } static inline void trace_sii9022_read_reg(uint8_t addr, uint8_t val) { if (true) { _nocheck__trace_sii9022_read_reg(addr, val); } } #define TRACE_SII9022_WRITE_REG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SII9022_WRITE_REG) || \ false) static inline void _nocheck__trace_sii9022_write_reg(uint8_t addr, uint8_t val) { if (trace_event_get_state(TRACE_SII9022_WRITE_REG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 141 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sii9022_write_reg " "addr 0x%02x, val 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4081 "trace/trace-hw_display.h" } else { #line 141 "../hw/display/trace-events" qemu_log("sii9022_write_reg " "addr 0x%02x, val 0x%02x" "\n", addr, val); #line 4085 "trace/trace-hw_display.h" } } } static inline void trace_sii9022_write_reg(uint8_t addr, uint8_t val) { if (true) { _nocheck__trace_sii9022_write_reg(addr, val); } } #define TRACE_SII9022_SWITCH_MODE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SII9022_SWITCH_MODE) || \ false) static inline void _nocheck__trace_sii9022_switch_mode(const char * mode) { if (trace_event_get_state(TRACE_SII9022_SWITCH_MODE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 142 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sii9022_switch_mode " "mode: %s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , mode); #line 4112 "trace/trace-hw_display.h" } else { #line 142 "../hw/display/trace-events" qemu_log("sii9022_switch_mode " "mode: %s" "\n", mode); #line 4116 "trace/trace-hw_display.h" } } } static inline void trace_sii9022_switch_mode(const char * mode) { if (true) { _nocheck__trace_sii9022_switch_mode(mode); } } #define TRACE_ATI_MM_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ATI_MM_READ) || \ false) static inline void _nocheck__trace_ati_mm_read(unsigned int size, uint64_t addr, const char * name, uint64_t val) { if (trace_event_get_state(TRACE_ATI_MM_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 145 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:ati_mm_read " "%u 0x%"PRIx64 " %s -> 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, name, val); #line 4143 "trace/trace-hw_display.h" } else { #line 145 "../hw/display/trace-events" qemu_log("ati_mm_read " "%u 0x%"PRIx64 " %s -> 0x%"PRIx64 "\n", size, addr, name, val); #line 4147 "trace/trace-hw_display.h" } } } static inline void trace_ati_mm_read(unsigned int size, uint64_t addr, const char * name, uint64_t val) { if (true) { _nocheck__trace_ati_mm_read(size, addr, name, val); } } #define TRACE_ATI_MM_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ATI_MM_WRITE) || \ false) static inline void _nocheck__trace_ati_mm_write(unsigned int size, uint64_t addr, const char * name, uint64_t val) { if (trace_event_get_state(TRACE_ATI_MM_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 146 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:ati_mm_write " "%u 0x%"PRIx64 " %s <- 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, name, val); #line 4174 "trace/trace-hw_display.h" } else { #line 146 "../hw/display/trace-events" qemu_log("ati_mm_write " "%u 0x%"PRIx64 " %s <- 0x%"PRIx64 "\n", size, addr, name, val); #line 4178 "trace/trace-hw_display.h" } } } static inline void trace_ati_mm_write(unsigned int size, uint64_t addr, const char * name, uint64_t val) { if (true) { _nocheck__trace_ati_mm_write(size, addr, name, val); } } #define TRACE_ARTIST_REG_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARTIST_REG_READ) || \ false) static inline void _nocheck__trace_artist_reg_read(unsigned int size, uint64_t addr, const char * name, uint64_t val) { if (trace_event_get_state(TRACE_ARTIST_REG_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 149 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:artist_reg_read " "%u 0x%"PRIx64 "%s -> 0x%08"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, name, val); #line 4205 "trace/trace-hw_display.h" } else { #line 149 "../hw/display/trace-events" qemu_log("artist_reg_read " "%u 0x%"PRIx64 "%s -> 0x%08"PRIx64 "\n", size, addr, name, val); #line 4209 "trace/trace-hw_display.h" } } } static inline void trace_artist_reg_read(unsigned int size, uint64_t addr, const char * name, uint64_t val) { if (true) { _nocheck__trace_artist_reg_read(size, addr, name, val); } } #define TRACE_ARTIST_REG_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARTIST_REG_WRITE) || \ false) static inline void _nocheck__trace_artist_reg_write(unsigned int size, uint64_t addr, const char * name, uint64_t val) { if (trace_event_get_state(TRACE_ARTIST_REG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 150 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:artist_reg_write " "%u 0x%"PRIx64 "%s <- 0x%08"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, name, val); #line 4236 "trace/trace-hw_display.h" } else { #line 150 "../hw/display/trace-events" qemu_log("artist_reg_write " "%u 0x%"PRIx64 "%s <- 0x%08"PRIx64 "\n", size, addr, name, val); #line 4240 "trace/trace-hw_display.h" } } } static inline void trace_artist_reg_write(unsigned int size, uint64_t addr, const char * name, uint64_t val) { if (true) { _nocheck__trace_artist_reg_write(size, addr, name, val); } } #define TRACE_ARTIST_VRAM_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARTIST_VRAM_READ) || \ false) static inline void _nocheck__trace_artist_vram_read(unsigned int size, uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_ARTIST_VRAM_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 151 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:artist_vram_read " "%u 0x%08"PRIx64 " -> 0x%08"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, val); #line 4267 "trace/trace-hw_display.h" } else { #line 151 "../hw/display/trace-events" qemu_log("artist_vram_read " "%u 0x%08"PRIx64 " -> 0x%08"PRIx64 "\n", size, addr, val); #line 4271 "trace/trace-hw_display.h" } } } static inline void trace_artist_vram_read(unsigned int size, uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_artist_vram_read(size, addr, val); } } #define TRACE_ARTIST_VRAM_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARTIST_VRAM_WRITE) || \ false) static inline void _nocheck__trace_artist_vram_write(unsigned int size, uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_ARTIST_VRAM_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 152 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:artist_vram_write " "%u 0x%08"PRIx64 " <- 0x%08"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, val); #line 4298 "trace/trace-hw_display.h" } else { #line 152 "../hw/display/trace-events" qemu_log("artist_vram_write " "%u 0x%08"PRIx64 " <- 0x%08"PRIx64 "\n", size, addr, val); #line 4302 "trace/trace-hw_display.h" } } } static inline void trace_artist_vram_write(unsigned int size, uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_artist_vram_write(size, addr, val); } } #define TRACE_ARTIST_FILL_WINDOW_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARTIST_FILL_WINDOW) || \ false) static inline void _nocheck__trace_artist_fill_window(unsigned int start_x, unsigned int start_y, unsigned int width, unsigned int height, uint32_t op, uint32_t ctlpln) { if (trace_event_get_state(TRACE_ARTIST_FILL_WINDOW) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 153 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:artist_fill_window " "start=%ux%u length=%ux%u op=0x%08x ctlpln=0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , start_x, start_y, width, height, op, ctlpln); #line 4329 "trace/trace-hw_display.h" } else { #line 153 "../hw/display/trace-events" qemu_log("artist_fill_window " "start=%ux%u length=%ux%u op=0x%08x ctlpln=0x%08x" "\n", start_x, start_y, width, height, op, ctlpln); #line 4333 "trace/trace-hw_display.h" } } } static inline void trace_artist_fill_window(unsigned int start_x, unsigned int start_y, unsigned int width, unsigned int height, uint32_t op, uint32_t ctlpln) { if (true) { _nocheck__trace_artist_fill_window(start_x, start_y, width, height, op, ctlpln); } } #define TRACE_ARTIST_BLOCK_MOVE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARTIST_BLOCK_MOVE) || \ false) static inline void _nocheck__trace_artist_block_move(unsigned int start_x, unsigned int start_y, unsigned int dest_x, unsigned int dest_y, unsigned int width, unsigned int height) { if (trace_event_get_state(TRACE_ARTIST_BLOCK_MOVE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 154 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:artist_block_move " "source %ux%u -> dest %ux%u size %ux%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , start_x, start_y, dest_x, dest_y, width, height); #line 4360 "trace/trace-hw_display.h" } else { #line 154 "../hw/display/trace-events" qemu_log("artist_block_move " "source %ux%u -> dest %ux%u size %ux%u" "\n", start_x, start_y, dest_x, dest_y, width, height); #line 4364 "trace/trace-hw_display.h" } } } static inline void trace_artist_block_move(unsigned int start_x, unsigned int start_y, unsigned int dest_x, unsigned int dest_y, unsigned int width, unsigned int height) { if (true) { _nocheck__trace_artist_block_move(start_x, start_y, dest_x, dest_y, width, height); } } #define TRACE_ARTIST_DRAW_LINE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARTIST_DRAW_LINE) || \ false) static inline void _nocheck__trace_artist_draw_line(unsigned int start_x, unsigned int start_y, unsigned int end_x, unsigned int end_y) { if (trace_event_get_state(TRACE_ARTIST_DRAW_LINE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 155 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:artist_draw_line " "%ux%u %ux%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , start_x, start_y, end_x, end_y); #line 4391 "trace/trace-hw_display.h" } else { #line 155 "../hw/display/trace-events" qemu_log("artist_draw_line " "%ux%u %ux%u" "\n", start_x, start_y, end_x, end_y); #line 4395 "trace/trace-hw_display.h" } } } static inline void trace_artist_draw_line(unsigned int start_x, unsigned int start_y, unsigned int end_x, unsigned int end_y) { if (true) { _nocheck__trace_artist_draw_line(start_x, start_y, end_x, end_y); } } #define TRACE_CG3_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_CG3_READ) || \ false) static inline void _nocheck__trace_cg3_read(uint32_t addr, uint32_t val, unsigned size) { if (trace_event_get_state(TRACE_CG3_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 158 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:cg3_read " "read addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val, size); #line 4422 "trace/trace-hw_display.h" } else { #line 158 "../hw/display/trace-events" qemu_log("cg3_read " "read addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u" "\n", addr, val, size); #line 4426 "trace/trace-hw_display.h" } } } static inline void trace_cg3_read(uint32_t addr, uint32_t val, unsigned size) { if (true) { _nocheck__trace_cg3_read(addr, val, size); } } #define TRACE_CG3_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_CG3_WRITE) || \ false) static inline void _nocheck__trace_cg3_write(uint32_t addr, uint32_t val, unsigned size) { if (trace_event_get_state(TRACE_CG3_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 159 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:cg3_write " "write addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val, size); #line 4453 "trace/trace-hw_display.h" } else { #line 159 "../hw/display/trace-events" qemu_log("cg3_write " "write addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u" "\n", addr, val, size); #line 4457 "trace/trace-hw_display.h" } } } static inline void trace_cg3_write(uint32_t addr, uint32_t val, unsigned size) { if (true) { _nocheck__trace_cg3_write(addr, val, size); } } #define TRACE_DPCD_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DPCD_READ) || \ false) static inline void _nocheck__trace_dpcd_read(uint32_t addr, uint8_t val) { if (trace_event_get_state(TRACE_DPCD_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 162 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dpcd_read " "read addr:0x%"PRIx32" val:0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4484 "trace/trace-hw_display.h" } else { #line 162 "../hw/display/trace-events" qemu_log("dpcd_read " "read addr:0x%"PRIx32" val:0x%02x" "\n", addr, val); #line 4488 "trace/trace-hw_display.h" } } } static inline void trace_dpcd_read(uint32_t addr, uint8_t val) { if (true) { _nocheck__trace_dpcd_read(addr, val); } } #define TRACE_DPCD_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DPCD_WRITE) || \ false) static inline void _nocheck__trace_dpcd_write(uint32_t addr, uint8_t val) { if (trace_event_get_state(TRACE_DPCD_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 163 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dpcd_write " "write addr:0x%"PRIx32" val:0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4515 "trace/trace-hw_display.h" } else { #line 163 "../hw/display/trace-events" qemu_log("dpcd_write " "write addr:0x%"PRIx32" val:0x%02x" "\n", addr, val); #line 4519 "trace/trace-hw_display.h" } } } static inline void trace_dpcd_write(uint32_t addr, uint8_t val) { if (true) { _nocheck__trace_dpcd_write(addr, val); } } #define TRACE_SM501_SYSTEM_CONFIG_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SM501_SYSTEM_CONFIG_READ) || \ false) static inline void _nocheck__trace_sm501_system_config_read(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_SM501_SYSTEM_CONFIG_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 166 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sm501_system_config_read " "addr=0x%x, val=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4546 "trace/trace-hw_display.h" } else { #line 166 "../hw/display/trace-events" qemu_log("sm501_system_config_read " "addr=0x%x, val=0x%x" "\n", addr, val); #line 4550 "trace/trace-hw_display.h" } } } static inline void trace_sm501_system_config_read(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_sm501_system_config_read(addr, val); } } #define TRACE_SM501_SYSTEM_CONFIG_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SM501_SYSTEM_CONFIG_WRITE) || \ false) static inline void _nocheck__trace_sm501_system_config_write(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_SM501_SYSTEM_CONFIG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 167 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sm501_system_config_write " "addr=0x%x, val=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4577 "trace/trace-hw_display.h" } else { #line 167 "../hw/display/trace-events" qemu_log("sm501_system_config_write " "addr=0x%x, val=0x%x" "\n", addr, val); #line 4581 "trace/trace-hw_display.h" } } } static inline void trace_sm501_system_config_write(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_sm501_system_config_write(addr, val); } } #define TRACE_SM501_I2C_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SM501_I2C_READ) || \ false) static inline void _nocheck__trace_sm501_i2c_read(uint32_t addr, uint8_t val) { if (trace_event_get_state(TRACE_SM501_I2C_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 168 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sm501_i2c_read " "addr=0x%x, val=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4608 "trace/trace-hw_display.h" } else { #line 168 "../hw/display/trace-events" qemu_log("sm501_i2c_read " "addr=0x%x, val=0x%x" "\n", addr, val); #line 4612 "trace/trace-hw_display.h" } } } static inline void trace_sm501_i2c_read(uint32_t addr, uint8_t val) { if (true) { _nocheck__trace_sm501_i2c_read(addr, val); } } #define TRACE_SM501_I2C_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SM501_I2C_WRITE) || \ false) static inline void _nocheck__trace_sm501_i2c_write(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_SM501_I2C_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 169 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sm501_i2c_write " "addr=0x%x, val=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4639 "trace/trace-hw_display.h" } else { #line 169 "../hw/display/trace-events" qemu_log("sm501_i2c_write " "addr=0x%x, val=0x%x" "\n", addr, val); #line 4643 "trace/trace-hw_display.h" } } } static inline void trace_sm501_i2c_write(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_sm501_i2c_write(addr, val); } } #define TRACE_SM501_PALETTE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SM501_PALETTE_READ) || \ false) static inline void _nocheck__trace_sm501_palette_read(uint32_t addr) { if (trace_event_get_state(TRACE_SM501_PALETTE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 170 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sm501_palette_read " "addr=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr); #line 4670 "trace/trace-hw_display.h" } else { #line 170 "../hw/display/trace-events" qemu_log("sm501_palette_read " "addr=0x%x" "\n", addr); #line 4674 "trace/trace-hw_display.h" } } } static inline void trace_sm501_palette_read(uint32_t addr) { if (true) { _nocheck__trace_sm501_palette_read(addr); } } #define TRACE_SM501_PALETTE_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SM501_PALETTE_WRITE) || \ false) static inline void _nocheck__trace_sm501_palette_write(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_SM501_PALETTE_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 171 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sm501_palette_write " "addr=0x%x, val=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4701 "trace/trace-hw_display.h" } else { #line 171 "../hw/display/trace-events" qemu_log("sm501_palette_write " "addr=0x%x, val=0x%x" "\n", addr, val); #line 4705 "trace/trace-hw_display.h" } } } static inline void trace_sm501_palette_write(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_sm501_palette_write(addr, val); } } #define TRACE_SM501_DISP_CTRL_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SM501_DISP_CTRL_READ) || \ false) static inline void _nocheck__trace_sm501_disp_ctrl_read(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_SM501_DISP_CTRL_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 172 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sm501_disp_ctrl_read " "addr=0x%x, val=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4732 "trace/trace-hw_display.h" } else { #line 172 "../hw/display/trace-events" qemu_log("sm501_disp_ctrl_read " "addr=0x%x, val=0x%x" "\n", addr, val); #line 4736 "trace/trace-hw_display.h" } } } static inline void trace_sm501_disp_ctrl_read(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_sm501_disp_ctrl_read(addr, val); } } #define TRACE_SM501_DISP_CTRL_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SM501_DISP_CTRL_WRITE) || \ false) static inline void _nocheck__trace_sm501_disp_ctrl_write(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_SM501_DISP_CTRL_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 173 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sm501_disp_ctrl_write " "addr=0x%x, val=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4763 "trace/trace-hw_display.h" } else { #line 173 "../hw/display/trace-events" qemu_log("sm501_disp_ctrl_write " "addr=0x%x, val=0x%x" "\n", addr, val); #line 4767 "trace/trace-hw_display.h" } } } static inline void trace_sm501_disp_ctrl_write(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_sm501_disp_ctrl_write(addr, val); } } #define TRACE_SM501_2D_ENGINE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SM501_2D_ENGINE_READ) || \ false) static inline void _nocheck__trace_sm501_2d_engine_read(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_SM501_2D_ENGINE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 174 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sm501_2d_engine_read " "addr=0x%x, val=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4794 "trace/trace-hw_display.h" } else { #line 174 "../hw/display/trace-events" qemu_log("sm501_2d_engine_read " "addr=0x%x, val=0x%x" "\n", addr, val); #line 4798 "trace/trace-hw_display.h" } } } static inline void trace_sm501_2d_engine_read(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_sm501_2d_engine_read(addr, val); } } #define TRACE_SM501_2D_ENGINE_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SM501_2D_ENGINE_WRITE) || \ false) static inline void _nocheck__trace_sm501_2d_engine_write(uint32_t addr, uint32_t val) { if (trace_event_get_state(TRACE_SM501_2D_ENGINE_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 175 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:sm501_2d_engine_write " "addr=0x%x, val=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 4825 "trace/trace-hw_display.h" } else { #line 175 "../hw/display/trace-events" qemu_log("sm501_2d_engine_write " "addr=0x%x, val=0x%x" "\n", addr, val); #line 4829 "trace/trace-hw_display.h" } } } static inline void trace_sm501_2d_engine_write(uint32_t addr, uint32_t val) { if (true) { _nocheck__trace_sm501_2d_engine_write(addr, val); } } #define TRACE_MACFB_CTRL_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MACFB_CTRL_READ) || \ false) static inline void _nocheck__trace_macfb_ctrl_read(uint64_t addr, uint64_t value, unsigned int size) { if (trace_event_get_state(TRACE_MACFB_CTRL_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 178 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:macfb_ctrl_read " "addr 0x%"PRIx64 " value 0x%"PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, value, size); #line 4856 "trace/trace-hw_display.h" } else { #line 178 "../hw/display/trace-events" qemu_log("macfb_ctrl_read " "addr 0x%"PRIx64 " value 0x%"PRIx64 " size %u" "\n", addr, value, size); #line 4860 "trace/trace-hw_display.h" } } } static inline void trace_macfb_ctrl_read(uint64_t addr, uint64_t value, unsigned int size) { if (true) { _nocheck__trace_macfb_ctrl_read(addr, value, size); } } #define TRACE_MACFB_CTRL_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MACFB_CTRL_WRITE) || \ false) static inline void _nocheck__trace_macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned int size) { if (trace_event_get_state(TRACE_MACFB_CTRL_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 179 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:macfb_ctrl_write " "addr 0x%"PRIx64 " value 0x%"PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, value, size); #line 4887 "trace/trace-hw_display.h" } else { #line 179 "../hw/display/trace-events" qemu_log("macfb_ctrl_write " "addr 0x%"PRIx64 " value 0x%"PRIx64 " size %u" "\n", addr, value, size); #line 4891 "trace/trace-hw_display.h" } } } static inline void trace_macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned int size) { if (true) { _nocheck__trace_macfb_ctrl_write(addr, value, size); } } #define TRACE_MACFB_SENSE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MACFB_SENSE_READ) || \ false) static inline void _nocheck__trace_macfb_sense_read(uint32_t value) { if (trace_event_get_state(TRACE_MACFB_SENSE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 180 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:macfb_sense_read " "video sense: 0x%"PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , value); #line 4918 "trace/trace-hw_display.h" } else { #line 180 "../hw/display/trace-events" qemu_log("macfb_sense_read " "video sense: 0x%"PRIx32 "\n", value); #line 4922 "trace/trace-hw_display.h" } } } static inline void trace_macfb_sense_read(uint32_t value) { if (true) { _nocheck__trace_macfb_sense_read(value); } } #define TRACE_MACFB_SENSE_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MACFB_SENSE_WRITE) || \ false) static inline void _nocheck__trace_macfb_sense_write(uint32_t value) { if (trace_event_get_state(TRACE_MACFB_SENSE_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 181 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:macfb_sense_write " "video sense: 0x%"PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , value); #line 4949 "trace/trace-hw_display.h" } else { #line 181 "../hw/display/trace-events" qemu_log("macfb_sense_write " "video sense: 0x%"PRIx32 "\n", value); #line 4953 "trace/trace-hw_display.h" } } } static inline void trace_macfb_sense_write(uint32_t value) { if (true) { _nocheck__trace_macfb_sense_write(value); } } #define TRACE_MACFB_UPDATE_MODE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MACFB_UPDATE_MODE) || \ false) static inline void _nocheck__trace_macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) { if (trace_event_get_state(TRACE_MACFB_UPDATE_MODE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 182 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:macfb_update_mode " "setting mode to width %"PRId32 " height %"PRId32 " size %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , width, height, depth); #line 4980 "trace/trace-hw_display.h" } else { #line 182 "../hw/display/trace-events" qemu_log("macfb_update_mode " "setting mode to width %"PRId32 " height %"PRId32 " size %d" "\n", width, height, depth); #line 4984 "trace/trace-hw_display.h" } } } static inline void trace_macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) { if (true) { _nocheck__trace_macfb_update_mode(width, height, depth); } } #define TRACE_DM163_REDRAW_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_REDRAW) || \ false) static inline void _nocheck__trace_dm163_redraw(uint8_t redraw) { if (trace_event_get_state(TRACE_DM163_REDRAW) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 185 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_redraw " "0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , redraw); #line 5011 "trace/trace-hw_display.h" } else { #line 185 "../hw/display/trace-events" qemu_log("dm163_redraw " "0x%02x" "\n", redraw); #line 5015 "trace/trace-hw_display.h" } } } static inline void trace_dm163_redraw(uint8_t redraw) { if (true) { _nocheck__trace_dm163_redraw(redraw); } } #define TRACE_DM163_DCK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_DCK) || \ false) static inline void _nocheck__trace_dm163_dck(unsigned new_state) { if (trace_event_get_state(TRACE_DM163_DCK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 186 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_dck " "dck : %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , new_state); #line 5042 "trace/trace-hw_display.h" } else { #line 186 "../hw/display/trace-events" qemu_log("dm163_dck " "dck : %u" "\n", new_state); #line 5046 "trace/trace-hw_display.h" } } } static inline void trace_dm163_dck(unsigned new_state) { if (true) { _nocheck__trace_dm163_dck(new_state); } } #define TRACE_DM163_EN_B_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_EN_B) || \ false) static inline void _nocheck__trace_dm163_en_b(unsigned new_state) { if (trace_event_get_state(TRACE_DM163_EN_B) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 187 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_en_b " "en_b : %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , new_state); #line 5073 "trace/trace-hw_display.h" } else { #line 187 "../hw/display/trace-events" qemu_log("dm163_en_b " "en_b : %u" "\n", new_state); #line 5077 "trace/trace-hw_display.h" } } } static inline void trace_dm163_en_b(unsigned new_state) { if (true) { _nocheck__trace_dm163_en_b(new_state); } } #define TRACE_DM163_RST_B_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_RST_B) || \ false) static inline void _nocheck__trace_dm163_rst_b(unsigned new_state) { if (trace_event_get_state(TRACE_DM163_RST_B) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 188 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_rst_b " "rst_b : %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , new_state); #line 5104 "trace/trace-hw_display.h" } else { #line 188 "../hw/display/trace-events" qemu_log("dm163_rst_b " "rst_b : %u" "\n", new_state); #line 5108 "trace/trace-hw_display.h" } } } static inline void trace_dm163_rst_b(unsigned new_state) { if (true) { _nocheck__trace_dm163_rst_b(new_state); } } #define TRACE_DM163_LAT_B_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_LAT_B) || \ false) static inline void _nocheck__trace_dm163_lat_b(unsigned new_state) { if (trace_event_get_state(TRACE_DM163_LAT_B) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 189 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_lat_b " "lat_b : %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , new_state); #line 5135 "trace/trace-hw_display.h" } else { #line 189 "../hw/display/trace-events" qemu_log("dm163_lat_b " "lat_b : %u" "\n", new_state); #line 5139 "trace/trace-hw_display.h" } } } static inline void trace_dm163_lat_b(unsigned new_state) { if (true) { _nocheck__trace_dm163_lat_b(new_state); } } #define TRACE_DM163_SIN_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_SIN) || \ false) static inline void _nocheck__trace_dm163_sin(unsigned new_state) { if (trace_event_get_state(TRACE_DM163_SIN) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 190 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_sin " "sin : %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , new_state); #line 5166 "trace/trace-hw_display.h" } else { #line 190 "../hw/display/trace-events" qemu_log("dm163_sin " "sin : %u" "\n", new_state); #line 5170 "trace/trace-hw_display.h" } } } static inline void trace_dm163_sin(unsigned new_state) { if (true) { _nocheck__trace_dm163_sin(new_state); } } #define TRACE_DM163_SELBK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_SELBK) || \ false) static inline void _nocheck__trace_dm163_selbk(unsigned new_state) { if (trace_event_get_state(TRACE_DM163_SELBK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 191 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_selbk " "selbk : %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , new_state); #line 5197 "trace/trace-hw_display.h" } else { #line 191 "../hw/display/trace-events" qemu_log("dm163_selbk " "selbk : %u" "\n", new_state); #line 5201 "trace/trace-hw_display.h" } } } static inline void trace_dm163_selbk(unsigned new_state) { if (true) { _nocheck__trace_dm163_selbk(new_state); } } #define TRACE_DM163_ACTIVATED_ROWS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_ACTIVATED_ROWS) || \ false) static inline void _nocheck__trace_dm163_activated_rows(int new_state) { if (trace_event_get_state(TRACE_DM163_ACTIVATED_ROWS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 192 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_activated_rows " "Activated rows : 0x%" PRIx32 "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , new_state); #line 5228 "trace/trace-hw_display.h" } else { #line 192 "../hw/display/trace-events" qemu_log("dm163_activated_rows " "Activated rows : 0x%" PRIx32 "" "\n", new_state); #line 5232 "trace/trace-hw_display.h" } } } static inline void trace_dm163_activated_rows(int new_state) { if (true) { _nocheck__trace_dm163_activated_rows(new_state); } } #define TRACE_DM163_BITS_PPI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_BITS_PPI) || \ false) static inline void _nocheck__trace_dm163_bits_ppi(unsigned dest_width) { if (trace_event_get_state(TRACE_DM163_BITS_PPI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 193 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_bits_ppi " "dest_width : %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dest_width); #line 5259 "trace/trace-hw_display.h" } else { #line 193 "../hw/display/trace-events" qemu_log("dm163_bits_ppi " "dest_width : %u" "\n", dest_width); #line 5263 "trace/trace-hw_display.h" } } } static inline void trace_dm163_bits_ppi(unsigned dest_width) { if (true) { _nocheck__trace_dm163_bits_ppi(dest_width); } } #define TRACE_DM163_LEDS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_LEDS) || \ false) static inline void _nocheck__trace_dm163_leds(int led, uint32_t value) { if (trace_event_get_state(TRACE_DM163_LEDS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 194 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_leds " "led %d: 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , led, value); #line 5290 "trace/trace-hw_display.h" } else { #line 194 "../hw/display/trace-events" qemu_log("dm163_leds " "led %d: 0x%x" "\n", led, value); #line 5294 "trace/trace-hw_display.h" } } } static inline void trace_dm163_leds(int led, uint32_t value) { if (true) { _nocheck__trace_dm163_leds(led, value); } } #define TRACE_DM163_CHANNELS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_CHANNELS) || \ false) static inline void _nocheck__trace_dm163_channels(int channel, uint8_t value) { if (trace_event_get_state(TRACE_DM163_CHANNELS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 195 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_channels " "channel %d: 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , channel, value); #line 5321 "trace/trace-hw_display.h" } else { #line 195 "../hw/display/trace-events" qemu_log("dm163_channels " "channel %d: 0x%x" "\n", channel, value); #line 5325 "trace/trace-hw_display.h" } } } static inline void trace_dm163_channels(int channel, uint8_t value) { if (true) { _nocheck__trace_dm163_channels(channel, value); } } #define TRACE_DM163_REFRESH_RATE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DM163_REFRESH_RATE) || \ false) static inline void _nocheck__trace_dm163_refresh_rate(uint32_t rr) { if (trace_event_get_state(TRACE_DM163_REFRESH_RATE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 196 "../hw/display/trace-events" qemu_log("%d@%zu.%06zu:dm163_refresh_rate " "refresh rate %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , rr); #line 5352 "trace/trace-hw_display.h" } else { #line 196 "../hw/display/trace-events" qemu_log("dm163_refresh_rate " "refresh rate %d" "\n", rr); #line 5356 "trace/trace-hw_display.h" } } } static inline void trace_dm163_refresh_rate(uint32_t rr) { if (true) { _nocheck__trace_dm163_refresh_rate(rr); } } #endif /* TRACE_HW_DISPLAY_GENERATED_TRACERS_H */