/* This file is autogenerated by tracetool, do not edit. */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_gpio.h"

uint16_t _TRACE_NPCM7XX_GPIO_READ_DSTATE;
uint16_t _TRACE_NPCM7XX_GPIO_WRITE_DSTATE;
uint16_t _TRACE_NPCM7XX_GPIO_SET_INPUT_DSTATE;
uint16_t _TRACE_NPCM7XX_GPIO_SET_OUTPUT_DSTATE;
uint16_t _TRACE_NPCM7XX_GPIO_UPDATE_EVENTS_DSTATE;
uint16_t _TRACE_NRF51_GPIO_READ_DSTATE;
uint16_t _TRACE_NRF51_GPIO_WRITE_DSTATE;
uint16_t _TRACE_NRF51_GPIO_SET_DSTATE;
uint16_t _TRACE_NRF51_GPIO_UPDATE_OUTPUT_IRQ_DSTATE;
uint16_t _TRACE_PCA955X_GPIO_STATUS_DSTATE;
uint16_t _TRACE_PCA955X_GPIO_CHANGE_DSTATE;
uint16_t _TRACE_PL061_UPDATE_DSTATE;
uint16_t _TRACE_PL061_SET_OUTPUT_DSTATE;
uint16_t _TRACE_PL061_INPUT_CHANGE_DSTATE;
uint16_t _TRACE_PL061_UPDATE_ISTATE_DSTATE;
uint16_t _TRACE_PL061_READ_DSTATE;
uint16_t _TRACE_PL061_WRITE_DSTATE;
uint16_t _TRACE_PL061_RESET_DSTATE;
uint16_t _TRACE_SIFIVE_GPIO_READ_DSTATE;
uint16_t _TRACE_SIFIVE_GPIO_WRITE_DSTATE;
uint16_t _TRACE_SIFIVE_GPIO_SET_DSTATE;
uint16_t _TRACE_SIFIVE_GPIO_UPDATE_OUTPUT_IRQ_DSTATE;
uint16_t _TRACE_ASPEED_GPIO_READ_DSTATE;
uint16_t _TRACE_ASPEED_GPIO_WRITE_DSTATE;
uint16_t _TRACE_STM32L4X5_GPIO_READ_DSTATE;
uint16_t _TRACE_STM32L4X5_GPIO_WRITE_DSTATE;
uint16_t _TRACE_STM32L4X5_GPIO_UPDATE_IDR_DSTATE;
uint16_t _TRACE_STM32L4X5_GPIO_PINS_DSTATE;
TraceEvent _TRACE_NPCM7XX_GPIO_READ_EVENT = {
    .id = 0,
    .name = "npcm7xx_gpio_read",
    .sstate = TRACE_NPCM7XX_GPIO_READ_ENABLED,
    .dstate = &_TRACE_NPCM7XX_GPIO_READ_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_GPIO_WRITE_EVENT = {
    .id = 0,
    .name = "npcm7xx_gpio_write",
    .sstate = TRACE_NPCM7XX_GPIO_WRITE_ENABLED,
    .dstate = &_TRACE_NPCM7XX_GPIO_WRITE_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_GPIO_SET_INPUT_EVENT = {
    .id = 0,
    .name = "npcm7xx_gpio_set_input",
    .sstate = TRACE_NPCM7XX_GPIO_SET_INPUT_ENABLED,
    .dstate = &_TRACE_NPCM7XX_GPIO_SET_INPUT_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_GPIO_SET_OUTPUT_EVENT = {
    .id = 0,
    .name = "npcm7xx_gpio_set_output",
    .sstate = TRACE_NPCM7XX_GPIO_SET_OUTPUT_ENABLED,
    .dstate = &_TRACE_NPCM7XX_GPIO_SET_OUTPUT_DSTATE 
};
TraceEvent _TRACE_NPCM7XX_GPIO_UPDATE_EVENTS_EVENT = {
    .id = 0,
    .name = "npcm7xx_gpio_update_events",
    .sstate = TRACE_NPCM7XX_GPIO_UPDATE_EVENTS_ENABLED,
    .dstate = &_TRACE_NPCM7XX_GPIO_UPDATE_EVENTS_DSTATE 
};
TraceEvent _TRACE_NRF51_GPIO_READ_EVENT = {
    .id = 0,
    .name = "nrf51_gpio_read",
    .sstate = TRACE_NRF51_GPIO_READ_ENABLED,
    .dstate = &_TRACE_NRF51_GPIO_READ_DSTATE 
};
TraceEvent _TRACE_NRF51_GPIO_WRITE_EVENT = {
    .id = 0,
    .name = "nrf51_gpio_write",
    .sstate = TRACE_NRF51_GPIO_WRITE_ENABLED,
    .dstate = &_TRACE_NRF51_GPIO_WRITE_DSTATE 
};
TraceEvent _TRACE_NRF51_GPIO_SET_EVENT = {
    .id = 0,
    .name = "nrf51_gpio_set",
    .sstate = TRACE_NRF51_GPIO_SET_ENABLED,
    .dstate = &_TRACE_NRF51_GPIO_SET_DSTATE 
};
TraceEvent _TRACE_NRF51_GPIO_UPDATE_OUTPUT_IRQ_EVENT = {
    .id = 0,
    .name = "nrf51_gpio_update_output_irq",
    .sstate = TRACE_NRF51_GPIO_UPDATE_OUTPUT_IRQ_ENABLED,
    .dstate = &_TRACE_NRF51_GPIO_UPDATE_OUTPUT_IRQ_DSTATE 
};
TraceEvent _TRACE_PCA955X_GPIO_STATUS_EVENT = {
    .id = 0,
    .name = "pca955x_gpio_status",
    .sstate = TRACE_PCA955X_GPIO_STATUS_ENABLED,
    .dstate = &_TRACE_PCA955X_GPIO_STATUS_DSTATE 
};
TraceEvent _TRACE_PCA955X_GPIO_CHANGE_EVENT = {
    .id = 0,
    .name = "pca955x_gpio_change",
    .sstate = TRACE_PCA955X_GPIO_CHANGE_ENABLED,
    .dstate = &_TRACE_PCA955X_GPIO_CHANGE_DSTATE 
};
TraceEvent _TRACE_PL061_UPDATE_EVENT = {
    .id = 0,
    .name = "pl061_update",
    .sstate = TRACE_PL061_UPDATE_ENABLED,
    .dstate = &_TRACE_PL061_UPDATE_DSTATE 
};
TraceEvent _TRACE_PL061_SET_OUTPUT_EVENT = {
    .id = 0,
    .name = "pl061_set_output",
    .sstate = TRACE_PL061_SET_OUTPUT_ENABLED,
    .dstate = &_TRACE_PL061_SET_OUTPUT_DSTATE 
};
TraceEvent _TRACE_PL061_INPUT_CHANGE_EVENT = {
    .id = 0,
    .name = "pl061_input_change",
    .sstate = TRACE_PL061_INPUT_CHANGE_ENABLED,
    .dstate = &_TRACE_PL061_INPUT_CHANGE_DSTATE 
};
TraceEvent _TRACE_PL061_UPDATE_ISTATE_EVENT = {
    .id = 0,
    .name = "pl061_update_istate",
    .sstate = TRACE_PL061_UPDATE_ISTATE_ENABLED,
    .dstate = &_TRACE_PL061_UPDATE_ISTATE_DSTATE 
};
TraceEvent _TRACE_PL061_READ_EVENT = {
    .id = 0,
    .name = "pl061_read",
    .sstate = TRACE_PL061_READ_ENABLED,
    .dstate = &_TRACE_PL061_READ_DSTATE 
};
TraceEvent _TRACE_PL061_WRITE_EVENT = {
    .id = 0,
    .name = "pl061_write",
    .sstate = TRACE_PL061_WRITE_ENABLED,
    .dstate = &_TRACE_PL061_WRITE_DSTATE 
};
TraceEvent _TRACE_PL061_RESET_EVENT = {
    .id = 0,
    .name = "pl061_reset",
    .sstate = TRACE_PL061_RESET_ENABLED,
    .dstate = &_TRACE_PL061_RESET_DSTATE 
};
TraceEvent _TRACE_SIFIVE_GPIO_READ_EVENT = {
    .id = 0,
    .name = "sifive_gpio_read",
    .sstate = TRACE_SIFIVE_GPIO_READ_ENABLED,
    .dstate = &_TRACE_SIFIVE_GPIO_READ_DSTATE 
};
TraceEvent _TRACE_SIFIVE_GPIO_WRITE_EVENT = {
    .id = 0,
    .name = "sifive_gpio_write",
    .sstate = TRACE_SIFIVE_GPIO_WRITE_ENABLED,
    .dstate = &_TRACE_SIFIVE_GPIO_WRITE_DSTATE 
};
TraceEvent _TRACE_SIFIVE_GPIO_SET_EVENT = {
    .id = 0,
    .name = "sifive_gpio_set",
    .sstate = TRACE_SIFIVE_GPIO_SET_ENABLED,
    .dstate = &_TRACE_SIFIVE_GPIO_SET_DSTATE 
};
TraceEvent _TRACE_SIFIVE_GPIO_UPDATE_OUTPUT_IRQ_EVENT = {
    .id = 0,
    .name = "sifive_gpio_update_output_irq",
    .sstate = TRACE_SIFIVE_GPIO_UPDATE_OUTPUT_IRQ_ENABLED,
    .dstate = &_TRACE_SIFIVE_GPIO_UPDATE_OUTPUT_IRQ_DSTATE 
};
TraceEvent _TRACE_ASPEED_GPIO_READ_EVENT = {
    .id = 0,
    .name = "aspeed_gpio_read",
    .sstate = TRACE_ASPEED_GPIO_READ_ENABLED,
    .dstate = &_TRACE_ASPEED_GPIO_READ_DSTATE 
};
TraceEvent _TRACE_ASPEED_GPIO_WRITE_EVENT = {
    .id = 0,
    .name = "aspeed_gpio_write",
    .sstate = TRACE_ASPEED_GPIO_WRITE_ENABLED,
    .dstate = &_TRACE_ASPEED_GPIO_WRITE_DSTATE 
};
TraceEvent _TRACE_STM32L4X5_GPIO_READ_EVENT = {
    .id = 0,
    .name = "stm32l4x5_gpio_read",
    .sstate = TRACE_STM32L4X5_GPIO_READ_ENABLED,
    .dstate = &_TRACE_STM32L4X5_GPIO_READ_DSTATE 
};
TraceEvent _TRACE_STM32L4X5_GPIO_WRITE_EVENT = {
    .id = 0,
    .name = "stm32l4x5_gpio_write",
    .sstate = TRACE_STM32L4X5_GPIO_WRITE_ENABLED,
    .dstate = &_TRACE_STM32L4X5_GPIO_WRITE_DSTATE 
};
TraceEvent _TRACE_STM32L4X5_GPIO_UPDATE_IDR_EVENT = {
    .id = 0,
    .name = "stm32l4x5_gpio_update_idr",
    .sstate = TRACE_STM32L4X5_GPIO_UPDATE_IDR_ENABLED,
    .dstate = &_TRACE_STM32L4X5_GPIO_UPDATE_IDR_DSTATE 
};
TraceEvent _TRACE_STM32L4X5_GPIO_PINS_EVENT = {
    .id = 0,
    .name = "stm32l4x5_gpio_pins",
    .sstate = TRACE_STM32L4X5_GPIO_PINS_ENABLED,
    .dstate = &_TRACE_STM32L4X5_GPIO_PINS_DSTATE 
};
TraceEvent *hw_gpio_trace_events[] = {
    &_TRACE_NPCM7XX_GPIO_READ_EVENT,
    &_TRACE_NPCM7XX_GPIO_WRITE_EVENT,
    &_TRACE_NPCM7XX_GPIO_SET_INPUT_EVENT,
    &_TRACE_NPCM7XX_GPIO_SET_OUTPUT_EVENT,
    &_TRACE_NPCM7XX_GPIO_UPDATE_EVENTS_EVENT,
    &_TRACE_NRF51_GPIO_READ_EVENT,
    &_TRACE_NRF51_GPIO_WRITE_EVENT,
    &_TRACE_NRF51_GPIO_SET_EVENT,
    &_TRACE_NRF51_GPIO_UPDATE_OUTPUT_IRQ_EVENT,
    &_TRACE_PCA955X_GPIO_STATUS_EVENT,
    &_TRACE_PCA955X_GPIO_CHANGE_EVENT,
    &_TRACE_PL061_UPDATE_EVENT,
    &_TRACE_PL061_SET_OUTPUT_EVENT,
    &_TRACE_PL061_INPUT_CHANGE_EVENT,
    &_TRACE_PL061_UPDATE_ISTATE_EVENT,
    &_TRACE_PL061_READ_EVENT,
    &_TRACE_PL061_WRITE_EVENT,
    &_TRACE_PL061_RESET_EVENT,
    &_TRACE_SIFIVE_GPIO_READ_EVENT,
    &_TRACE_SIFIVE_GPIO_WRITE_EVENT,
    &_TRACE_SIFIVE_GPIO_SET_EVENT,
    &_TRACE_SIFIVE_GPIO_UPDATE_OUTPUT_IRQ_EVENT,
    &_TRACE_ASPEED_GPIO_READ_EVENT,
    &_TRACE_ASPEED_GPIO_WRITE_EVENT,
    &_TRACE_STM32L4X5_GPIO_READ_EVENT,
    &_TRACE_STM32L4X5_GPIO_WRITE_EVENT,
    &_TRACE_STM32L4X5_GPIO_UPDATE_IDR_EVENT,
    &_TRACE_STM32L4X5_GPIO_PINS_EVENT,
  NULL,
};

static void trace_hw_gpio_register_events(void)
{
    trace_event_register_group(hw_gpio_trace_events);
}
trace_init(trace_hw_gpio_register_events)