/* This file is autogenerated by tracetool, do not edit. */

#ifndef TRACE_HW_GPIO_GENERATED_TRACERS_H
#define TRACE_HW_GPIO_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_NPCM7XX_GPIO_READ_EVENT;
extern TraceEvent _TRACE_NPCM7XX_GPIO_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_GPIO_SET_INPUT_EVENT;
extern TraceEvent _TRACE_NPCM7XX_GPIO_SET_OUTPUT_EVENT;
extern TraceEvent _TRACE_NPCM7XX_GPIO_UPDATE_EVENTS_EVENT;
extern TraceEvent _TRACE_NRF51_GPIO_READ_EVENT;
extern TraceEvent _TRACE_NRF51_GPIO_WRITE_EVENT;
extern TraceEvent _TRACE_NRF51_GPIO_SET_EVENT;
extern TraceEvent _TRACE_NRF51_GPIO_UPDATE_OUTPUT_IRQ_EVENT;
extern TraceEvent _TRACE_PCA955X_GPIO_STATUS_EVENT;
extern TraceEvent _TRACE_PCA955X_GPIO_CHANGE_EVENT;
extern TraceEvent _TRACE_PL061_UPDATE_EVENT;
extern TraceEvent _TRACE_PL061_SET_OUTPUT_EVENT;
extern TraceEvent _TRACE_PL061_INPUT_CHANGE_EVENT;
extern TraceEvent _TRACE_PL061_UPDATE_ISTATE_EVENT;
extern TraceEvent _TRACE_PL061_READ_EVENT;
extern TraceEvent _TRACE_PL061_WRITE_EVENT;
extern TraceEvent _TRACE_PL061_RESET_EVENT;
extern TraceEvent _TRACE_SIFIVE_GPIO_READ_EVENT;
extern TraceEvent _TRACE_SIFIVE_GPIO_WRITE_EVENT;
extern TraceEvent _TRACE_SIFIVE_GPIO_SET_EVENT;
extern TraceEvent _TRACE_SIFIVE_GPIO_UPDATE_OUTPUT_IRQ_EVENT;
extern TraceEvent _TRACE_ASPEED_GPIO_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_GPIO_WRITE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_GPIO_READ_EVENT;
extern TraceEvent _TRACE_STM32L4X5_GPIO_WRITE_EVENT;
extern TraceEvent _TRACE_STM32L4X5_GPIO_UPDATE_IDR_EVENT;
extern TraceEvent _TRACE_STM32L4X5_GPIO_PINS_EVENT;
extern uint16_t _TRACE_NPCM7XX_GPIO_READ_DSTATE;
extern uint16_t _TRACE_NPCM7XX_GPIO_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_GPIO_SET_INPUT_DSTATE;
extern uint16_t _TRACE_NPCM7XX_GPIO_SET_OUTPUT_DSTATE;
extern uint16_t _TRACE_NPCM7XX_GPIO_UPDATE_EVENTS_DSTATE;
extern uint16_t _TRACE_NRF51_GPIO_READ_DSTATE;
extern uint16_t _TRACE_NRF51_GPIO_WRITE_DSTATE;
extern uint16_t _TRACE_NRF51_GPIO_SET_DSTATE;
extern uint16_t _TRACE_NRF51_GPIO_UPDATE_OUTPUT_IRQ_DSTATE;
extern uint16_t _TRACE_PCA955X_GPIO_STATUS_DSTATE;
extern uint16_t _TRACE_PCA955X_GPIO_CHANGE_DSTATE;
extern uint16_t _TRACE_PL061_UPDATE_DSTATE;
extern uint16_t _TRACE_PL061_SET_OUTPUT_DSTATE;
extern uint16_t _TRACE_PL061_INPUT_CHANGE_DSTATE;
extern uint16_t _TRACE_PL061_UPDATE_ISTATE_DSTATE;
extern uint16_t _TRACE_PL061_READ_DSTATE;
extern uint16_t _TRACE_PL061_WRITE_DSTATE;
extern uint16_t _TRACE_PL061_RESET_DSTATE;
extern uint16_t _TRACE_SIFIVE_GPIO_READ_DSTATE;
extern uint16_t _TRACE_SIFIVE_GPIO_WRITE_DSTATE;
extern uint16_t _TRACE_SIFIVE_GPIO_SET_DSTATE;
extern uint16_t _TRACE_SIFIVE_GPIO_UPDATE_OUTPUT_IRQ_DSTATE;
extern uint16_t _TRACE_ASPEED_GPIO_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_GPIO_WRITE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_GPIO_READ_DSTATE;
extern uint16_t _TRACE_STM32L4X5_GPIO_WRITE_DSTATE;
extern uint16_t _TRACE_STM32L4X5_GPIO_UPDATE_IDR_DSTATE;
extern uint16_t _TRACE_STM32L4X5_GPIO_PINS_DSTATE;
#define TRACE_NPCM7XX_GPIO_READ_ENABLED 1
#define TRACE_NPCM7XX_GPIO_WRITE_ENABLED 1
#define TRACE_NPCM7XX_GPIO_SET_INPUT_ENABLED 1
#define TRACE_NPCM7XX_GPIO_SET_OUTPUT_ENABLED 1
#define TRACE_NPCM7XX_GPIO_UPDATE_EVENTS_ENABLED 1
#define TRACE_NRF51_GPIO_READ_ENABLED 1
#define TRACE_NRF51_GPIO_WRITE_ENABLED 1
#define TRACE_NRF51_GPIO_SET_ENABLED 1
#define TRACE_NRF51_GPIO_UPDATE_OUTPUT_IRQ_ENABLED 1
#define TRACE_PCA955X_GPIO_STATUS_ENABLED 1
#define TRACE_PCA955X_GPIO_CHANGE_ENABLED 1
#define TRACE_PL061_UPDATE_ENABLED 1
#define TRACE_PL061_SET_OUTPUT_ENABLED 1
#define TRACE_PL061_INPUT_CHANGE_ENABLED 1
#define TRACE_PL061_UPDATE_ISTATE_ENABLED 1
#define TRACE_PL061_READ_ENABLED 1
#define TRACE_PL061_WRITE_ENABLED 1
#define TRACE_PL061_RESET_ENABLED 1
#define TRACE_SIFIVE_GPIO_READ_ENABLED 1
#define TRACE_SIFIVE_GPIO_WRITE_ENABLED 1
#define TRACE_SIFIVE_GPIO_SET_ENABLED 1
#define TRACE_SIFIVE_GPIO_UPDATE_OUTPUT_IRQ_ENABLED 1
#define TRACE_ASPEED_GPIO_READ_ENABLED 1
#define TRACE_ASPEED_GPIO_WRITE_ENABLED 1
#define TRACE_STM32L4X5_GPIO_READ_ENABLED 1
#define TRACE_STM32L4X5_GPIO_WRITE_ENABLED 1
#define TRACE_STM32L4X5_GPIO_UPDATE_IDR_ENABLED 1
#define TRACE_STM32L4X5_GPIO_PINS_ENABLED 1
#include "qemu/log-for-trace.h"
#include "qemu/error-report.h"


#define TRACE_NPCM7XX_GPIO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_GPIO_READ) || \
    false)

static inline void _nocheck__trace_npcm7xx_gpio_read(const char * id, uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_GPIO_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 4 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_gpio_read " " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, offset, value);
#line 112 "trace/trace-hw_gpio.h"
        } else {
#line 4 "../hw/gpio/trace-events"
            qemu_log("npcm7xx_gpio_read " " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 "\n", id, offset, value);
#line 116 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_npcm7xx_gpio_read(const char * id, uint64_t offset, uint64_t value)
{
    if (true) {
        _nocheck__trace_npcm7xx_gpio_read(id, offset, value);
    }
}

#define TRACE_NPCM7XX_GPIO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_GPIO_WRITE) || \
    false)

static inline void _nocheck__trace_npcm7xx_gpio_write(const char * id, uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_GPIO_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 5 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_gpio_write " "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, offset, value);
#line 143 "trace/trace-hw_gpio.h"
        } else {
#line 5 "../hw/gpio/trace-events"
            qemu_log("npcm7xx_gpio_write " "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 "\n", id, offset, value);
#line 147 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_npcm7xx_gpio_write(const char * id, uint64_t offset, uint64_t value)
{
    if (true) {
        _nocheck__trace_npcm7xx_gpio_write(id, offset, value);
    }
}

#define TRACE_NPCM7XX_GPIO_SET_INPUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_GPIO_SET_INPUT) || \
    false)

static inline void _nocheck__trace_npcm7xx_gpio_set_input(const char * id, int32_t line, int32_t level)
{
    if (trace_event_get_state(TRACE_NPCM7XX_GPIO_SET_INPUT) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 6 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_gpio_set_input " "%s line: %" PRIi32 " level: %" PRIi32 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, line, level);
#line 174 "trace/trace-hw_gpio.h"
        } else {
#line 6 "../hw/gpio/trace-events"
            qemu_log("npcm7xx_gpio_set_input " "%s line: %" PRIi32 " level: %" PRIi32 "\n", id, line, level);
#line 178 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_npcm7xx_gpio_set_input(const char * id, int32_t line, int32_t level)
{
    if (true) {
        _nocheck__trace_npcm7xx_gpio_set_input(id, line, level);
    }
}

#define TRACE_NPCM7XX_GPIO_SET_OUTPUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_GPIO_SET_OUTPUT) || \
    false)

static inline void _nocheck__trace_npcm7xx_gpio_set_output(const char * id, int32_t line, int32_t level)
{
    if (trace_event_get_state(TRACE_NPCM7XX_GPIO_SET_OUTPUT) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 7 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_gpio_set_output " "%s line: %" PRIi32 " level: %" PRIi32 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, line, level);
#line 205 "trace/trace-hw_gpio.h"
        } else {
#line 7 "../hw/gpio/trace-events"
            qemu_log("npcm7xx_gpio_set_output " "%s line: %" PRIi32 " level: %" PRIi32 "\n", id, line, level);
#line 209 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_npcm7xx_gpio_set_output(const char * id, int32_t line, int32_t level)
{
    if (true) {
        _nocheck__trace_npcm7xx_gpio_set_output(id, line, level);
    }
}

#define TRACE_NPCM7XX_GPIO_UPDATE_EVENTS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_GPIO_UPDATE_EVENTS) || \
    false)

static inline void _nocheck__trace_npcm7xx_gpio_update_events(const char * id, uint32_t evst, uint32_t even)
{
    if (trace_event_get_state(TRACE_NPCM7XX_GPIO_UPDATE_EVENTS) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 8 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_gpio_update_events " "%s evst: 0x%08" PRIx32 " even: 0x%08" PRIx32 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, evst, even);
#line 236 "trace/trace-hw_gpio.h"
        } else {
#line 8 "../hw/gpio/trace-events"
            qemu_log("npcm7xx_gpio_update_events " "%s evst: 0x%08" PRIx32 " even: 0x%08" PRIx32 "\n", id, evst, even);
#line 240 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_npcm7xx_gpio_update_events(const char * id, uint32_t evst, uint32_t even)
{
    if (true) {
        _nocheck__trace_npcm7xx_gpio_update_events(id, evst, even);
    }
}

#define TRACE_NRF51_GPIO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NRF51_GPIO_READ) || \
    false)

static inline void _nocheck__trace_nrf51_gpio_read(uint64_t offset, uint64_t r)
{
    if (trace_event_get_state(TRACE_NRF51_GPIO_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 11 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:nrf51_gpio_read " "offset 0x%" PRIx64 " value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , offset, r);
#line 267 "trace/trace-hw_gpio.h"
        } else {
#line 11 "../hw/gpio/trace-events"
            qemu_log("nrf51_gpio_read " "offset 0x%" PRIx64 " value 0x%" PRIx64 "\n", offset, r);
#line 271 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_nrf51_gpio_read(uint64_t offset, uint64_t r)
{
    if (true) {
        _nocheck__trace_nrf51_gpio_read(offset, r);
    }
}

#define TRACE_NRF51_GPIO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NRF51_GPIO_WRITE) || \
    false)

static inline void _nocheck__trace_nrf51_gpio_write(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_NRF51_GPIO_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 12 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:nrf51_gpio_write " "offset 0x%" PRIx64 " value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , offset, value);
#line 298 "trace/trace-hw_gpio.h"
        } else {
#line 12 "../hw/gpio/trace-events"
            qemu_log("nrf51_gpio_write " "offset 0x%" PRIx64 " value 0x%" PRIx64 "\n", offset, value);
#line 302 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_nrf51_gpio_write(uint64_t offset, uint64_t value)
{
    if (true) {
        _nocheck__trace_nrf51_gpio_write(offset, value);
    }
}

#define TRACE_NRF51_GPIO_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NRF51_GPIO_SET) || \
    false)

static inline void _nocheck__trace_nrf51_gpio_set(int64_t line, int64_t value)
{
    if (trace_event_get_state(TRACE_NRF51_GPIO_SET) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 13 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:nrf51_gpio_set " "line %" PRIi64 " value %" PRIi64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , line, value);
#line 329 "trace/trace-hw_gpio.h"
        } else {
#line 13 "../hw/gpio/trace-events"
            qemu_log("nrf51_gpio_set " "line %" PRIi64 " value %" PRIi64 "\n", line, value);
#line 333 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_nrf51_gpio_set(int64_t line, int64_t value)
{
    if (true) {
        _nocheck__trace_nrf51_gpio_set(line, value);
    }
}

#define TRACE_NRF51_GPIO_UPDATE_OUTPUT_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NRF51_GPIO_UPDATE_OUTPUT_IRQ) || \
    false)

static inline void _nocheck__trace_nrf51_gpio_update_output_irq(int64_t line, int64_t value)
{
    if (trace_event_get_state(TRACE_NRF51_GPIO_UPDATE_OUTPUT_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 14 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:nrf51_gpio_update_output_irq " "line %" PRIi64 " value %" PRIi64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , line, value);
#line 360 "trace/trace-hw_gpio.h"
        } else {
#line 14 "../hw/gpio/trace-events"
            qemu_log("nrf51_gpio_update_output_irq " "line %" PRIi64 " value %" PRIi64 "\n", line, value);
#line 364 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_nrf51_gpio_update_output_irq(int64_t line, int64_t value)
{
    if (true) {
        _nocheck__trace_nrf51_gpio_update_output_irq(line, value);
    }
}

#define TRACE_PCA955X_GPIO_STATUS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCA955X_GPIO_STATUS) || \
    false)

static inline void _nocheck__trace_pca955x_gpio_status(const char * description, const char * buf)
{
    if (trace_event_get_state(TRACE_PCA955X_GPIO_STATUS) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 17 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:pca955x_gpio_status " "%s GPIOs 0-15 [%s]" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , description, buf);
#line 391 "trace/trace-hw_gpio.h"
        } else {
#line 17 "../hw/gpio/trace-events"
            qemu_log("pca955x_gpio_status " "%s GPIOs 0-15 [%s]" "\n", description, buf);
#line 395 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_pca955x_gpio_status(const char * description, const char * buf)
{
    if (true) {
        _nocheck__trace_pca955x_gpio_status(description, buf);
    }
}

#define TRACE_PCA955X_GPIO_CHANGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCA955X_GPIO_CHANGE) || \
    false)

static inline void _nocheck__trace_pca955x_gpio_change(const char * description, unsigned id, unsigned prev_state, unsigned current_state)
{
    if (trace_event_get_state(TRACE_PCA955X_GPIO_CHANGE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 18 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:pca955x_gpio_change " "%s GPIO id:%u status: %u -> %u" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , description, id, prev_state, current_state);
#line 422 "trace/trace-hw_gpio.h"
        } else {
#line 18 "../hw/gpio/trace-events"
            qemu_log("pca955x_gpio_change " "%s GPIO id:%u status: %u -> %u" "\n", description, id, prev_state, current_state);
#line 426 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_pca955x_gpio_change(const char * description, unsigned id, unsigned prev_state, unsigned current_state)
{
    if (true) {
        _nocheck__trace_pca955x_gpio_change(description, id, prev_state, current_state);
    }
}

#define TRACE_PL061_UPDATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL061_UPDATE) || \
    false)

static inline void _nocheck__trace_pl061_update(const char * id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating)
{
    if (trace_event_get_state(TRACE_PL061_UPDATE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 21 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:pl061_update " "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, dir, data, pullups, floating);
#line 453 "trace/trace-hw_gpio.h"
        } else {
#line 21 "../hw/gpio/trace-events"
            qemu_log("pl061_update " "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x" "\n", id, dir, data, pullups, floating);
#line 457 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_pl061_update(const char * id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating)
{
    if (true) {
        _nocheck__trace_pl061_update(id, dir, data, pullups, floating);
    }
}

#define TRACE_PL061_SET_OUTPUT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL061_SET_OUTPUT) || \
    false)

static inline void _nocheck__trace_pl061_set_output(const char * id, int gpio, int level)
{
    if (trace_event_get_state(TRACE_PL061_SET_OUTPUT) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 22 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:pl061_set_output " "%s setting output %d to %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, gpio, level);
#line 484 "trace/trace-hw_gpio.h"
        } else {
#line 22 "../hw/gpio/trace-events"
            qemu_log("pl061_set_output " "%s setting output %d to %d" "\n", id, gpio, level);
#line 488 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_pl061_set_output(const char * id, int gpio, int level)
{
    if (true) {
        _nocheck__trace_pl061_set_output(id, gpio, level);
    }
}

#define TRACE_PL061_INPUT_CHANGE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL061_INPUT_CHANGE) || \
    false)

static inline void _nocheck__trace_pl061_input_change(const char * id, int gpio, int level)
{
    if (trace_event_get_state(TRACE_PL061_INPUT_CHANGE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 23 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:pl061_input_change " "%s input %d changed to %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, gpio, level);
#line 515 "trace/trace-hw_gpio.h"
        } else {
#line 23 "../hw/gpio/trace-events"
            qemu_log("pl061_input_change " "%s input %d changed to %d" "\n", id, gpio, level);
#line 519 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_pl061_input_change(const char * id, int gpio, int level)
{
    if (true) {
        _nocheck__trace_pl061_input_change(id, gpio, level);
    }
}

#define TRACE_PL061_UPDATE_ISTATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL061_UPDATE_ISTATE) || \
    false)

static inline void _nocheck__trace_pl061_update_istate(const char * id, uint32_t istate, uint32_t im, int level)
{
    if (trace_event_get_state(TRACE_PL061_UPDATE_ISTATE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 24 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:pl061_update_istate " "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, istate, im, level);
#line 546 "trace/trace-hw_gpio.h"
        } else {
#line 24 "../hw/gpio/trace-events"
            qemu_log("pl061_update_istate " "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" "\n", id, istate, im, level);
#line 550 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_pl061_update_istate(const char * id, uint32_t istate, uint32_t im, int level)
{
    if (true) {
        _nocheck__trace_pl061_update_istate(id, istate, im, level);
    }
}

#define TRACE_PL061_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL061_READ) || \
    false)

static inline void _nocheck__trace_pl061_read(const char * id, uint64_t offset, uint64_t r)
{
    if (trace_event_get_state(TRACE_PL061_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 25 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:pl061_read " "%s offset 0x%" PRIx64 " value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, offset, r);
#line 577 "trace/trace-hw_gpio.h"
        } else {
#line 25 "../hw/gpio/trace-events"
            qemu_log("pl061_read " "%s offset 0x%" PRIx64 " value 0x%" PRIx64 "\n", id, offset, r);
#line 581 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_pl061_read(const char * id, uint64_t offset, uint64_t r)
{
    if (true) {
        _nocheck__trace_pl061_read(id, offset, r);
    }
}

#define TRACE_PL061_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL061_WRITE) || \
    false)

static inline void _nocheck__trace_pl061_write(const char * id, uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_PL061_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 26 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:pl061_write " "%s offset 0x%" PRIx64 " value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, offset, value);
#line 608 "trace/trace-hw_gpio.h"
        } else {
#line 26 "../hw/gpio/trace-events"
            qemu_log("pl061_write " "%s offset 0x%" PRIx64 " value 0x%" PRIx64 "\n", id, offset, value);
#line 612 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_pl061_write(const char * id, uint64_t offset, uint64_t value)
{
    if (true) {
        _nocheck__trace_pl061_write(id, offset, value);
    }
}

#define TRACE_PL061_RESET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PL061_RESET) || \
    false)

static inline void _nocheck__trace_pl061_reset(const char * id)
{
    if (trace_event_get_state(TRACE_PL061_RESET) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 27 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:pl061_reset " "%s reset" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id);
#line 639 "trace/trace-hw_gpio.h"
        } else {
#line 27 "../hw/gpio/trace-events"
            qemu_log("pl061_reset " "%s reset" "\n", id);
#line 643 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_pl061_reset(const char * id)
{
    if (true) {
        _nocheck__trace_pl061_reset(id);
    }
}

#define TRACE_SIFIVE_GPIO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SIFIVE_GPIO_READ) || \
    false)

static inline void _nocheck__trace_sifive_gpio_read(uint64_t offset, uint64_t r)
{
    if (trace_event_get_state(TRACE_SIFIVE_GPIO_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 30 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:sifive_gpio_read " "offset 0x%" PRIx64 " value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , offset, r);
#line 670 "trace/trace-hw_gpio.h"
        } else {
#line 30 "../hw/gpio/trace-events"
            qemu_log("sifive_gpio_read " "offset 0x%" PRIx64 " value 0x%" PRIx64 "\n", offset, r);
#line 674 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_sifive_gpio_read(uint64_t offset, uint64_t r)
{
    if (true) {
        _nocheck__trace_sifive_gpio_read(offset, r);
    }
}

#define TRACE_SIFIVE_GPIO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SIFIVE_GPIO_WRITE) || \
    false)

static inline void _nocheck__trace_sifive_gpio_write(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_SIFIVE_GPIO_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 31 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:sifive_gpio_write " "offset 0x%" PRIx64 " value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , offset, value);
#line 701 "trace/trace-hw_gpio.h"
        } else {
#line 31 "../hw/gpio/trace-events"
            qemu_log("sifive_gpio_write " "offset 0x%" PRIx64 " value 0x%" PRIx64 "\n", offset, value);
#line 705 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_sifive_gpio_write(uint64_t offset, uint64_t value)
{
    if (true) {
        _nocheck__trace_sifive_gpio_write(offset, value);
    }
}

#define TRACE_SIFIVE_GPIO_SET_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SIFIVE_GPIO_SET) || \
    false)

static inline void _nocheck__trace_sifive_gpio_set(int64_t line, int64_t value)
{
    if (trace_event_get_state(TRACE_SIFIVE_GPIO_SET) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 32 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:sifive_gpio_set " "line %" PRIi64 " value %" PRIi64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , line, value);
#line 732 "trace/trace-hw_gpio.h"
        } else {
#line 32 "../hw/gpio/trace-events"
            qemu_log("sifive_gpio_set " "line %" PRIi64 " value %" PRIi64 "\n", line, value);
#line 736 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_sifive_gpio_set(int64_t line, int64_t value)
{
    if (true) {
        _nocheck__trace_sifive_gpio_set(line, value);
    }
}

#define TRACE_SIFIVE_GPIO_UPDATE_OUTPUT_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SIFIVE_GPIO_UPDATE_OUTPUT_IRQ) || \
    false)

static inline void _nocheck__trace_sifive_gpio_update_output_irq(int64_t line, int64_t value)
{
    if (trace_event_get_state(TRACE_SIFIVE_GPIO_UPDATE_OUTPUT_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 33 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:sifive_gpio_update_output_irq " "line %" PRIi64 " value %" PRIi64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , line, value);
#line 763 "trace/trace-hw_gpio.h"
        } else {
#line 33 "../hw/gpio/trace-events"
            qemu_log("sifive_gpio_update_output_irq " "line %" PRIi64 " value %" PRIi64 "\n", line, value);
#line 767 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_sifive_gpio_update_output_irq(int64_t line, int64_t value)
{
    if (true) {
        _nocheck__trace_sifive_gpio_update_output_irq(line, value);
    }
}

#define TRACE_ASPEED_GPIO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_GPIO_READ) || \
    false)

static inline void _nocheck__trace_aspeed_gpio_read(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_GPIO_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 36 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:aspeed_gpio_read " "offset: 0x%" PRIx64 " value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , offset, value);
#line 794 "trace/trace-hw_gpio.h"
        } else {
#line 36 "../hw/gpio/trace-events"
            qemu_log("aspeed_gpio_read " "offset: 0x%" PRIx64 " value 0x%" PRIx64 "\n", offset, value);
#line 798 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_aspeed_gpio_read(uint64_t offset, uint64_t value)
{
    if (true) {
        _nocheck__trace_aspeed_gpio_read(offset, value);
    }
}

#define TRACE_ASPEED_GPIO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_GPIO_WRITE) || \
    false)

static inline void _nocheck__trace_aspeed_gpio_write(uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_GPIO_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 37 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:aspeed_gpio_write " "offset: 0x%" PRIx64 " value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , offset, value);
#line 825 "trace/trace-hw_gpio.h"
        } else {
#line 37 "../hw/gpio/trace-events"
            qemu_log("aspeed_gpio_write " "offset: 0x%" PRIx64 " value 0x%" PRIx64 "\n", offset, value);
#line 829 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_aspeed_gpio_write(uint64_t offset, uint64_t value)
{
    if (true) {
        _nocheck__trace_aspeed_gpio_write(offset, value);
    }
}

#define TRACE_STM32L4X5_GPIO_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_GPIO_READ) || \
    false)

static inline void _nocheck__trace_stm32l4x5_gpio_read(char * gpio, uint64_t addr)
{
    if (trace_event_get_state(TRACE_STM32L4X5_GPIO_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 40 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:stm32l4x5_gpio_read " "GPIO%s addr: 0x%" PRIx64 " " "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , gpio, addr);
#line 856 "trace/trace-hw_gpio.h"
        } else {
#line 40 "../hw/gpio/trace-events"
            qemu_log("stm32l4x5_gpio_read " "GPIO%s addr: 0x%" PRIx64 " " "\n", gpio, addr);
#line 860 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_stm32l4x5_gpio_read(char * gpio, uint64_t addr)
{
    if (true) {
        _nocheck__trace_stm32l4x5_gpio_read(gpio, addr);
    }
}

#define TRACE_STM32L4X5_GPIO_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_GPIO_WRITE) || \
    false)

static inline void _nocheck__trace_stm32l4x5_gpio_write(char * gpio, uint64_t addr, uint64_t data)
{
    if (trace_event_get_state(TRACE_STM32L4X5_GPIO_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 41 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:stm32l4x5_gpio_write " "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , gpio, addr, data);
#line 887 "trace/trace-hw_gpio.h"
        } else {
#line 41 "../hw/gpio/trace-events"
            qemu_log("stm32l4x5_gpio_write " "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", gpio, addr, data);
#line 891 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_stm32l4x5_gpio_write(char * gpio, uint64_t addr, uint64_t data)
{
    if (true) {
        _nocheck__trace_stm32l4x5_gpio_write(gpio, addr, data);
    }
}

#define TRACE_STM32L4X5_GPIO_UPDATE_IDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_GPIO_UPDATE_IDR) || \
    false)

static inline void _nocheck__trace_stm32l4x5_gpio_update_idr(char * gpio, uint32_t old_idr, uint32_t new_idr)
{
    if (trace_event_get_state(TRACE_STM32L4X5_GPIO_UPDATE_IDR) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 42 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:stm32l4x5_gpio_update_idr " "GPIO%s from: 0x%x to: 0x%x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , gpio, old_idr, new_idr);
#line 918 "trace/trace-hw_gpio.h"
        } else {
#line 42 "../hw/gpio/trace-events"
            qemu_log("stm32l4x5_gpio_update_idr " "GPIO%s from: 0x%x to: 0x%x" "\n", gpio, old_idr, new_idr);
#line 922 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_stm32l4x5_gpio_update_idr(char * gpio, uint32_t old_idr, uint32_t new_idr)
{
    if (true) {
        _nocheck__trace_stm32l4x5_gpio_update_idr(gpio, old_idr, new_idr);
    }
}

#define TRACE_STM32L4X5_GPIO_PINS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_GPIO_PINS) || \
    false)

static inline void _nocheck__trace_stm32l4x5_gpio_pins(char * gpio, uint16_t disconnected, uint16_t high)
{
    if (trace_event_get_state(TRACE_STM32L4X5_GPIO_PINS) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 43 "../hw/gpio/trace-events"
            qemu_log("%d@%zu.%06zu:stm32l4x5_gpio_pins " "GPIO%s disconnected pins: 0x%x levels: 0x%x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , gpio, disconnected, high);
#line 949 "trace/trace-hw_gpio.h"
        } else {
#line 43 "../hw/gpio/trace-events"
            qemu_log("stm32l4x5_gpio_pins " "GPIO%s disconnected pins: 0x%x levels: 0x%x" "\n", gpio, disconnected, high);
#line 953 "trace/trace-hw_gpio.h"
        }
    }
}

static inline void trace_stm32l4x5_gpio_pins(char * gpio, uint16_t disconnected, uint16_t high)
{
    if (true) {
        _nocheck__trace_stm32l4x5_gpio_pins(gpio, disconnected, high);
    }
}
#endif /* TRACE_HW_GPIO_GENERATED_TRACERS_H */