/* This file is autogenerated by tracetool, do not edit. */

#ifndef TRACE_HW_I2C_GENERATED_TRACERS_H
#define TRACE_HW_I2C_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_BITBANG_I2C_STATE_EVENT;
extern TraceEvent _TRACE_BITBANG_I2C_ADDR_EVENT;
extern TraceEvent _TRACE_BITBANG_I2C_SEND_EVENT;
extern TraceEvent _TRACE_BITBANG_I2C_RECV_EVENT;
extern TraceEvent _TRACE_BITBANG_I2C_DATA_EVENT;
extern TraceEvent _TRACE_I2C_EVENT_EVENT;
extern TraceEvent _TRACE_I2C_SEND_EVENT;
extern TraceEvent _TRACE_I2C_SEND_ASYNC_EVENT;
extern TraceEvent _TRACE_I2C_RECV_EVENT;
extern TraceEvent _TRACE_I2C_ACK_EVENT;
extern TraceEvent _TRACE_SMBUS_IOPORT_READB_EVENT;
extern TraceEvent _TRACE_SMBUS_IOPORT_WRITEB_EVENT;
extern TraceEvent _TRACE_SMBUS_TRANSACTION_EVENT;
extern TraceEvent _TRACE_ALLWINNER_I2C_READ_EVENT;
extern TraceEvent _TRACE_ALLWINNER_I2C_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_CMD_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_READ_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_WRITE_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_SEND_EVENT;
extern TraceEvent _TRACE_ASPEED_I2C_BUS_RECV_EVENT;
extern TraceEvent _TRACE_MPC_I2C_READ_EVENT;
extern TraceEvent _TRACE_MPC_I2C_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_READ_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_WRITE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_START_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_SEND_ADDRESS_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_SEND_BYTE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_RECV_BYTE_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_STOP_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_NACK_EVENT;
extern TraceEvent _TRACE_NPCM7XX_SMBUS_RECV_FIFO_EVENT;
extern TraceEvent _TRACE_PCA954X_WRITE_BYTES_EVENT;
extern TraceEvent _TRACE_PCA954X_READ_DATA_EVENT;
extern uint16_t _TRACE_BITBANG_I2C_STATE_DSTATE;
extern uint16_t _TRACE_BITBANG_I2C_ADDR_DSTATE;
extern uint16_t _TRACE_BITBANG_I2C_SEND_DSTATE;
extern uint16_t _TRACE_BITBANG_I2C_RECV_DSTATE;
extern uint16_t _TRACE_BITBANG_I2C_DATA_DSTATE;
extern uint16_t _TRACE_I2C_EVENT_DSTATE;
extern uint16_t _TRACE_I2C_SEND_DSTATE;
extern uint16_t _TRACE_I2C_SEND_ASYNC_DSTATE;
extern uint16_t _TRACE_I2C_RECV_DSTATE;
extern uint16_t _TRACE_I2C_ACK_DSTATE;
extern uint16_t _TRACE_SMBUS_IOPORT_READB_DSTATE;
extern uint16_t _TRACE_SMBUS_IOPORT_WRITEB_DSTATE;
extern uint16_t _TRACE_SMBUS_TRANSACTION_DSTATE;
extern uint16_t _TRACE_ALLWINNER_I2C_READ_DSTATE;
extern uint16_t _TRACE_ALLWINNER_I2C_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_CMD_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_READ_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_WRITE_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_SEND_DSTATE;
extern uint16_t _TRACE_ASPEED_I2C_BUS_RECV_DSTATE;
extern uint16_t _TRACE_MPC_I2C_READ_DSTATE;
extern uint16_t _TRACE_MPC_I2C_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_READ_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_WRITE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_START_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_SEND_ADDRESS_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_SEND_BYTE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_RECV_BYTE_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_STOP_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_NACK_DSTATE;
extern uint16_t _TRACE_NPCM7XX_SMBUS_RECV_FIFO_DSTATE;
extern uint16_t _TRACE_PCA954X_WRITE_BYTES_DSTATE;
extern uint16_t _TRACE_PCA954X_READ_DATA_DSTATE;
#define TRACE_BITBANG_I2C_STATE_ENABLED 1
#define TRACE_BITBANG_I2C_ADDR_ENABLED 1
#define TRACE_BITBANG_I2C_SEND_ENABLED 1
#define TRACE_BITBANG_I2C_RECV_ENABLED 1
#define TRACE_BITBANG_I2C_DATA_ENABLED 1
#define TRACE_I2C_EVENT_ENABLED 1
#define TRACE_I2C_SEND_ENABLED 1
#define TRACE_I2C_SEND_ASYNC_ENABLED 1
#define TRACE_I2C_RECV_ENABLED 1
#define TRACE_I2C_ACK_ENABLED 1
#define TRACE_SMBUS_IOPORT_READB_ENABLED 1
#define TRACE_SMBUS_IOPORT_WRITEB_ENABLED 1
#define TRACE_SMBUS_TRANSACTION_ENABLED 1
#define TRACE_ALLWINNER_I2C_READ_ENABLED 1
#define TRACE_ALLWINNER_I2C_WRITE_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_CMD_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_READ_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_WRITE_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_SEND_ENABLED 1
#define TRACE_ASPEED_I2C_BUS_RECV_ENABLED 1
#define TRACE_MPC_I2C_READ_ENABLED 1
#define TRACE_MPC_I2C_WRITE_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_READ_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_WRITE_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_START_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_SEND_ADDRESS_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_SEND_BYTE_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_RECV_BYTE_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_STOP_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_NACK_ENABLED 1
#define TRACE_NPCM7XX_SMBUS_RECV_FIFO_ENABLED 1
#define TRACE_PCA954X_WRITE_BYTES_ENABLED 1
#define TRACE_PCA954X_READ_DATA_ENABLED 1
#include "qemu/log-for-trace.h"
#include "qemu/error-report.h"


#define TRACE_BITBANG_I2C_STATE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BITBANG_I2C_STATE) || \
    false)

static inline void _nocheck__trace_bitbang_i2c_state(const char * old_state, const char * new_state)
{
    if (trace_event_get_state(TRACE_BITBANG_I2C_STATE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 4 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:bitbang_i2c_state " "state %s -> %s" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , old_state, new_state);
#line 130 "trace/trace-hw_i2c.h"
        } else {
#line 4 "../hw/i2c/trace-events"
            qemu_log("bitbang_i2c_state " "state %s -> %s" "\n", old_state, new_state);
#line 134 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_bitbang_i2c_state(const char * old_state, const char * new_state)
{
    if (true) {
        _nocheck__trace_bitbang_i2c_state(old_state, new_state);
    }
}

#define TRACE_BITBANG_I2C_ADDR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BITBANG_I2C_ADDR) || \
    false)

static inline void _nocheck__trace_bitbang_i2c_addr(uint8_t addr)
{
    if (trace_event_get_state(TRACE_BITBANG_I2C_ADDR) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 5 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:bitbang_i2c_addr " "Address 0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr);
#line 161 "trace/trace-hw_i2c.h"
        } else {
#line 5 "../hw/i2c/trace-events"
            qemu_log("bitbang_i2c_addr " "Address 0x%02x" "\n", addr);
#line 165 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_bitbang_i2c_addr(uint8_t addr)
{
    if (true) {
        _nocheck__trace_bitbang_i2c_addr(addr);
    }
}

#define TRACE_BITBANG_I2C_SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BITBANG_I2C_SEND) || \
    false)

static inline void _nocheck__trace_bitbang_i2c_send(uint8_t byte)
{
    if (trace_event_get_state(TRACE_BITBANG_I2C_SEND) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 6 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:bitbang_i2c_send " "TX byte 0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , byte);
#line 192 "trace/trace-hw_i2c.h"
        } else {
#line 6 "../hw/i2c/trace-events"
            qemu_log("bitbang_i2c_send " "TX byte 0x%02x" "\n", byte);
#line 196 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_bitbang_i2c_send(uint8_t byte)
{
    if (true) {
        _nocheck__trace_bitbang_i2c_send(byte);
    }
}

#define TRACE_BITBANG_I2C_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BITBANG_I2C_RECV) || \
    false)

static inline void _nocheck__trace_bitbang_i2c_recv(uint8_t byte)
{
    if (trace_event_get_state(TRACE_BITBANG_I2C_RECV) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 7 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:bitbang_i2c_recv " "RX byte 0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , byte);
#line 223 "trace/trace-hw_i2c.h"
        } else {
#line 7 "../hw/i2c/trace-events"
            qemu_log("bitbang_i2c_recv " "RX byte 0x%02x" "\n", byte);
#line 227 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_bitbang_i2c_recv(uint8_t byte)
{
    if (true) {
        _nocheck__trace_bitbang_i2c_recv(byte);
    }
}

#define TRACE_BITBANG_I2C_DATA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BITBANG_I2C_DATA) || \
    false)

static inline void _nocheck__trace_bitbang_i2c_data(unsigned clk, unsigned dat, unsigned old_out, unsigned new_out)
{
    if (trace_event_get_state(TRACE_BITBANG_I2C_DATA) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 8 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:bitbang_i2c_data " "clk %u dat %u out %u -> %u" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , clk, dat, old_out, new_out);
#line 254 "trace/trace-hw_i2c.h"
        } else {
#line 8 "../hw/i2c/trace-events"
            qemu_log("bitbang_i2c_data " "clk %u dat %u out %u -> %u" "\n", clk, dat, old_out, new_out);
#line 258 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_bitbang_i2c_data(unsigned clk, unsigned dat, unsigned old_out, unsigned new_out)
{
    if (true) {
        _nocheck__trace_bitbang_i2c_data(clk, dat, old_out, new_out);
    }
}

#define TRACE_I2C_EVENT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_EVENT) || \
    false)

static inline void _nocheck__trace_i2c_event(const char * event, uint8_t address)
{
    if (trace_event_get_state(TRACE_I2C_EVENT) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 12 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:i2c_event " "%s(addr:0x%02x)" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , event, address);
#line 285 "trace/trace-hw_i2c.h"
        } else {
#line 12 "../hw/i2c/trace-events"
            qemu_log("i2c_event " "%s(addr:0x%02x)" "\n", event, address);
#line 289 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_i2c_event(const char * event, uint8_t address)
{
    if (true) {
        _nocheck__trace_i2c_event(event, address);
    }
}

#define TRACE_I2C_SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_SEND) || \
    false)

static inline void _nocheck__trace_i2c_send(uint8_t address, uint8_t data)
{
    if (trace_event_get_state(TRACE_I2C_SEND) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 13 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:i2c_send " "send(addr:0x%02x) data:0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , address, data);
#line 316 "trace/trace-hw_i2c.h"
        } else {
#line 13 "../hw/i2c/trace-events"
            qemu_log("i2c_send " "send(addr:0x%02x) data:0x%02x" "\n", address, data);
#line 320 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_i2c_send(uint8_t address, uint8_t data)
{
    if (true) {
        _nocheck__trace_i2c_send(address, data);
    }
}

#define TRACE_I2C_SEND_ASYNC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_SEND_ASYNC) || \
    false)

static inline void _nocheck__trace_i2c_send_async(uint8_t address, uint8_t data)
{
    if (trace_event_get_state(TRACE_I2C_SEND_ASYNC) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 14 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:i2c_send_async " "send_async(addr:0x%02x) data:0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , address, data);
#line 347 "trace/trace-hw_i2c.h"
        } else {
#line 14 "../hw/i2c/trace-events"
            qemu_log("i2c_send_async " "send_async(addr:0x%02x) data:0x%02x" "\n", address, data);
#line 351 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_i2c_send_async(uint8_t address, uint8_t data)
{
    if (true) {
        _nocheck__trace_i2c_send_async(address, data);
    }
}

#define TRACE_I2C_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_RECV) || \
    false)

static inline void _nocheck__trace_i2c_recv(uint8_t address, uint8_t data)
{
    if (trace_event_get_state(TRACE_I2C_RECV) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 15 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:i2c_recv " "recv(addr:0x%02x) data:0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , address, data);
#line 378 "trace/trace-hw_i2c.h"
        } else {
#line 15 "../hw/i2c/trace-events"
            qemu_log("i2c_recv " "recv(addr:0x%02x) data:0x%02x" "\n", address, data);
#line 382 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_i2c_recv(uint8_t address, uint8_t data)
{
    if (true) {
        _nocheck__trace_i2c_recv(address, data);
    }
}

#define TRACE_I2C_ACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_I2C_ACK) || \
    false)

static inline void _nocheck__trace_i2c_ack(void)
{
    if (trace_event_get_state(TRACE_I2C_ACK) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 16 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:i2c_ack " "" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     );
#line 409 "trace/trace-hw_i2c.h"
        } else {
#line 16 "../hw/i2c/trace-events"
            qemu_log("i2c_ack " "" "\n");
#line 413 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_i2c_ack(void)
{
    if (true) {
        _nocheck__trace_i2c_ack();
    }
}

#define TRACE_SMBUS_IOPORT_READB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SMBUS_IOPORT_READB) || \
    false)

static inline void _nocheck__trace_smbus_ioport_readb(uint16_t addr, uint8_t data)
{
    if (trace_event_get_state(TRACE_SMBUS_IOPORT_READB) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 20 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:smbus_ioport_readb " "[0x%04" PRIx16 "] -> val=0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, data);
#line 440 "trace/trace-hw_i2c.h"
        } else {
#line 20 "../hw/i2c/trace-events"
            qemu_log("smbus_ioport_readb " "[0x%04" PRIx16 "] -> val=0x%02x" "\n", addr, data);
#line 444 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_smbus_ioport_readb(uint16_t addr, uint8_t data)
{
    if (true) {
        _nocheck__trace_smbus_ioport_readb(addr, data);
    }
}

#define TRACE_SMBUS_IOPORT_WRITEB_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SMBUS_IOPORT_WRITEB) || \
    false)

static inline void _nocheck__trace_smbus_ioport_writeb(uint16_t addr, uint8_t data)
{
    if (trace_event_get_state(TRACE_SMBUS_IOPORT_WRITEB) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 21 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:smbus_ioport_writeb " "[0x%04" PRIx16 "] <- val=0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, data);
#line 471 "trace/trace-hw_i2c.h"
        } else {
#line 21 "../hw/i2c/trace-events"
            qemu_log("smbus_ioport_writeb " "[0x%04" PRIx16 "] <- val=0x%02x" "\n", addr, data);
#line 475 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_smbus_ioport_writeb(uint16_t addr, uint8_t data)
{
    if (true) {
        _nocheck__trace_smbus_ioport_writeb(addr, data);
    }
}

#define TRACE_SMBUS_TRANSACTION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SMBUS_TRANSACTION) || \
    false)

static inline void _nocheck__trace_smbus_transaction(uint8_t addr, uint8_t prot)
{
    if (trace_event_get_state(TRACE_SMBUS_TRANSACTION) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 22 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:smbus_transaction " "addr=0x%02x prot=0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, prot);
#line 502 "trace/trace-hw_i2c.h"
        } else {
#line 22 "../hw/i2c/trace-events"
            qemu_log("smbus_transaction " "addr=0x%02x prot=0x%02x" "\n", addr, prot);
#line 506 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_smbus_transaction(uint8_t addr, uint8_t prot)
{
    if (true) {
        _nocheck__trace_smbus_transaction(addr, prot);
    }
}

#define TRACE_ALLWINNER_I2C_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_I2C_READ) || \
    false)

static inline void _nocheck__trace_allwinner_i2c_read(const char* reg_name, uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_ALLWINNER_I2C_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 26 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:allwinner_i2c_read " "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , reg_name, offset, value);
#line 533 "trace/trace-hw_i2c.h"
        } else {
#line 26 "../hw/i2c/trace-events"
            qemu_log("allwinner_i2c_read " "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64 "\n", reg_name, offset, value);
#line 537 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_allwinner_i2c_read(const char* reg_name, uint64_t offset, uint64_t value)
{
    if (true) {
        _nocheck__trace_allwinner_i2c_read(reg_name, offset, value);
    }
}

#define TRACE_ALLWINNER_I2C_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_I2C_WRITE) || \
    false)

static inline void _nocheck__trace_allwinner_i2c_write(const char* reg_name, uint64_t offset, uint64_t value)
{
    if (trace_event_get_state(TRACE_ALLWINNER_I2C_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 27 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:allwinner_i2c_write " "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , reg_name, offset, value);
#line 564 "trace/trace-hw_i2c.h"
        } else {
#line 27 "../hw/i2c/trace-events"
            qemu_log("allwinner_i2c_write " "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64 "\n", reg_name, offset, value);
#line 568 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_allwinner_i2c_write(const char* reg_name, uint64_t offset, uint64_t value)
{
    if (true) {
        _nocheck__trace_allwinner_i2c_write(reg_name, offset, value);
    }
}

#define TRACE_ASPEED_I2C_BUS_CMD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_CMD) || \
    false)

static inline void _nocheck__trace_aspeed_i2c_bus_cmd(uint32_t cmd, const char * cmd_flags, uint32_t count, uint32_t intr_status)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_CMD) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 31 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:aspeed_i2c_bus_cmd " "handling cmd=0x%x %s count=%d intr=0x%x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , cmd, cmd_flags, count, intr_status);
#line 595 "trace/trace-hw_i2c.h"
        } else {
#line 31 "../hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_cmd " "handling cmd=0x%x %s count=%d intr=0x%x" "\n", cmd, cmd_flags, count, intr_status);
#line 599 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_aspeed_i2c_bus_cmd(uint32_t cmd, const char * cmd_flags, uint32_t count, uint32_t intr_status)
{
    if (true) {
        _nocheck__trace_aspeed_i2c_bus_cmd(cmd, cmd_flags, count, intr_status);
    }
}

#define TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT) || \
    false)

static inline void _nocheck__trace_aspeed_i2c_bus_raise_interrupt(uint32_t intr_status, const char * s)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_RAISE_INTERRUPT) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 32 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:aspeed_i2c_bus_raise_interrupt " "handled intr=0x%x %s" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , intr_status, s);
#line 626 "trace/trace-hw_i2c.h"
        } else {
#line 32 "../hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_raise_interrupt " "handled intr=0x%x %s" "\n", intr_status, s);
#line 630 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_aspeed_i2c_bus_raise_interrupt(uint32_t intr_status, const char * s)
{
    if (true) {
        _nocheck__trace_aspeed_i2c_bus_raise_interrupt(intr_status, s);
    }
}

#define TRACE_ASPEED_I2C_BUS_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_READ) || \
    false)

static inline void _nocheck__trace_aspeed_i2c_bus_read(uint32_t busid, uint64_t offset, unsigned size, uint64_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 33 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:aspeed_i2c_bus_read " "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , busid, offset, size, value);
#line 657 "trace/trace-hw_i2c.h"
        } else {
#line 33 "../hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_read " "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 "\n", busid, offset, size, value);
#line 661 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_aspeed_i2c_bus_read(uint32_t busid, uint64_t offset, unsigned size, uint64_t value)
{
    if (true) {
        _nocheck__trace_aspeed_i2c_bus_read(busid, offset, size, value);
    }
}

#define TRACE_ASPEED_I2C_BUS_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_WRITE) || \
    false)

static inline void _nocheck__trace_aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t value)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 34 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:aspeed_i2c_bus_write " "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , busid, offset, size, value);
#line 688 "trace/trace-hw_i2c.h"
        } else {
#line 34 "../hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_write " "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64 "\n", busid, offset, size, value);
#line 692 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t value)
{
    if (true) {
        _nocheck__trace_aspeed_i2c_bus_write(busid, offset, size, value);
    }
}

#define TRACE_ASPEED_I2C_BUS_SEND_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_SEND) || \
    false)

static inline void _nocheck__trace_aspeed_i2c_bus_send(const char * mode, int i, int count, uint8_t byte)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_SEND) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 35 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:aspeed_i2c_bus_send " "%s send %d/%d 0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , mode, i, count, byte);
#line 719 "trace/trace-hw_i2c.h"
        } else {
#line 35 "../hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_send " "%s send %d/%d 0x%02x" "\n", mode, i, count, byte);
#line 723 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_aspeed_i2c_bus_send(const char * mode, int i, int count, uint8_t byte)
{
    if (true) {
        _nocheck__trace_aspeed_i2c_bus_send(mode, i, count, byte);
    }
}

#define TRACE_ASPEED_I2C_BUS_RECV_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I2C_BUS_RECV) || \
    false)

static inline void _nocheck__trace_aspeed_i2c_bus_recv(const char * mode, int i, int count, uint8_t byte)
{
    if (trace_event_get_state(TRACE_ASPEED_I2C_BUS_RECV) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 36 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:aspeed_i2c_bus_recv " "%s recv %d/%d 0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , mode, i, count, byte);
#line 750 "trace/trace-hw_i2c.h"
        } else {
#line 36 "../hw/i2c/trace-events"
            qemu_log("aspeed_i2c_bus_recv " "%s recv %d/%d 0x%02x" "\n", mode, i, count, byte);
#line 754 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_aspeed_i2c_bus_recv(const char * mode, int i, int count, uint8_t byte)
{
    if (true) {
        _nocheck__trace_aspeed_i2c_bus_recv(mode, i, count, byte);
    }
}

#define TRACE_MPC_I2C_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPC_I2C_READ) || \
    false)

static inline void _nocheck__trace_mpc_i2c_read(uint64_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_MPC_I2C_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 40 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:mpc_i2c_read " "[0x%" PRIx64 "] -> 0x%02" PRIx32 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, value);
#line 781 "trace/trace-hw_i2c.h"
        } else {
#line 40 "../hw/i2c/trace-events"
            qemu_log("mpc_i2c_read " "[0x%" PRIx64 "] -> 0x%02" PRIx32 "\n", addr, value);
#line 785 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_mpc_i2c_read(uint64_t addr, uint32_t value)
{
    if (true) {
        _nocheck__trace_mpc_i2c_read(addr, value);
    }
}

#define TRACE_MPC_I2C_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MPC_I2C_WRITE) || \
    false)

static inline void _nocheck__trace_mpc_i2c_write(uint64_t addr, uint32_t value)
{
    if (trace_event_get_state(TRACE_MPC_I2C_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 41 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:mpc_i2c_write " "[0x%" PRIx64 "] <- 0x%02" PRIx32 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, value);
#line 812 "trace/trace-hw_i2c.h"
        } else {
#line 41 "../hw/i2c/trace-events"
            qemu_log("mpc_i2c_write " "[0x%" PRIx64 "] <- 0x%02" PRIx32 "\n", addr, value);
#line 816 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_mpc_i2c_write(uint64_t addr, uint32_t value)
{
    if (true) {
        _nocheck__trace_mpc_i2c_write(addr, value);
    }
}

#define TRACE_NPCM7XX_SMBUS_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_READ) || \
    false)

static inline void _nocheck__trace_npcm7xx_smbus_read(const char * id, uint64_t offset, uint64_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 45 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_smbus_read " "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, offset, value, size);
#line 843 "trace/trace-hw_i2c.h"
        } else {
#line 45 "../hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_read " "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n", id, offset, value, size);
#line 847 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_npcm7xx_smbus_read(const char * id, uint64_t offset, uint64_t value, unsigned size)
{
    if (true) {
        _nocheck__trace_npcm7xx_smbus_read(id, offset, value, size);
    }
}

#define TRACE_NPCM7XX_SMBUS_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_WRITE) || \
    false)

static inline void _nocheck__trace_npcm7xx_smbus_write(const char * id, uint64_t offset, uint64_t value, unsigned size)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 46 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_smbus_write " "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, offset, value, size);
#line 874 "trace/trace-hw_i2c.h"
        } else {
#line 46 "../hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_write " "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n", id, offset, value, size);
#line 878 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_npcm7xx_smbus_write(const char * id, uint64_t offset, uint64_t value, unsigned size)
{
    if (true) {
        _nocheck__trace_npcm7xx_smbus_write(id, offset, value, size);
    }
}

#define TRACE_NPCM7XX_SMBUS_START_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_START) || \
    false)

static inline void _nocheck__trace_npcm7xx_smbus_start(const char * id, int success)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_START) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 47 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_smbus_start " "%s starting, success: %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, success);
#line 905 "trace/trace-hw_i2c.h"
        } else {
#line 47 "../hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_start " "%s starting, success: %d" "\n", id, success);
#line 909 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_npcm7xx_smbus_start(const char * id, int success)
{
    if (true) {
        _nocheck__trace_npcm7xx_smbus_start(id, success);
    }
}

#define TRACE_NPCM7XX_SMBUS_SEND_ADDRESS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_SEND_ADDRESS) || \
    false)

static inline void _nocheck__trace_npcm7xx_smbus_send_address(const char * id, uint8_t addr, int recv, int success)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_SEND_ADDRESS) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 48 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_smbus_send_address " "%s sending address: 0x%02x, recv: %d, success: %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, addr, recv, success);
#line 936 "trace/trace-hw_i2c.h"
        } else {
#line 48 "../hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_send_address " "%s sending address: 0x%02x, recv: %d, success: %d" "\n", id, addr, recv, success);
#line 940 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_npcm7xx_smbus_send_address(const char * id, uint8_t addr, int recv, int success)
{
    if (true) {
        _nocheck__trace_npcm7xx_smbus_send_address(id, addr, recv, success);
    }
}

#define TRACE_NPCM7XX_SMBUS_SEND_BYTE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_SEND_BYTE) || \
    false)

static inline void _nocheck__trace_npcm7xx_smbus_send_byte(const char * id, uint8_t value, int success)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_SEND_BYTE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 49 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_smbus_send_byte " "%s send byte: 0x%02x, success: %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, value, success);
#line 967 "trace/trace-hw_i2c.h"
        } else {
#line 49 "../hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_send_byte " "%s send byte: 0x%02x, success: %d" "\n", id, value, success);
#line 971 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_npcm7xx_smbus_send_byte(const char * id, uint8_t value, int success)
{
    if (true) {
        _nocheck__trace_npcm7xx_smbus_send_byte(id, value, success);
    }
}

#define TRACE_NPCM7XX_SMBUS_RECV_BYTE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_RECV_BYTE) || \
    false)

static inline void _nocheck__trace_npcm7xx_smbus_recv_byte(const char * id, uint8_t value)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_RECV_BYTE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 50 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_smbus_recv_byte " "%s recv byte: 0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, value);
#line 998 "trace/trace-hw_i2c.h"
        } else {
#line 50 "../hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_recv_byte " "%s recv byte: 0x%02x" "\n", id, value);
#line 1002 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_npcm7xx_smbus_recv_byte(const char * id, uint8_t value)
{
    if (true) {
        _nocheck__trace_npcm7xx_smbus_recv_byte(id, value);
    }
}

#define TRACE_NPCM7XX_SMBUS_STOP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_STOP) || \
    false)

static inline void _nocheck__trace_npcm7xx_smbus_stop(const char * id)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_STOP) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 51 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_smbus_stop " "%s stopping" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id);
#line 1029 "trace/trace-hw_i2c.h"
        } else {
#line 51 "../hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_stop " "%s stopping" "\n", id);
#line 1033 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_npcm7xx_smbus_stop(const char * id)
{
    if (true) {
        _nocheck__trace_npcm7xx_smbus_stop(id);
    }
}

#define TRACE_NPCM7XX_SMBUS_NACK_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_NACK) || \
    false)

static inline void _nocheck__trace_npcm7xx_smbus_nack(const char * id)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_NACK) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 52 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_smbus_nack " "%s nacking" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id);
#line 1060 "trace/trace-hw_i2c.h"
        } else {
#line 52 "../hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_nack " "%s nacking" "\n", id);
#line 1064 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_npcm7xx_smbus_nack(const char * id)
{
    if (true) {
        _nocheck__trace_npcm7xx_smbus_nack(id);
    }
}

#define TRACE_NPCM7XX_SMBUS_RECV_FIFO_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_SMBUS_RECV_FIFO) || \
    false)

static inline void _nocheck__trace_npcm7xx_smbus_recv_fifo(const char * id, uint8_t received, uint8_t expected)
{
    if (trace_event_get_state(TRACE_NPCM7XX_SMBUS_RECV_FIFO) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 53 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:npcm7xx_smbus_recv_fifo " "%s recv fifo: received %u, expected %u" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, received, expected);
#line 1091 "trace/trace-hw_i2c.h"
        } else {
#line 53 "../hw/i2c/trace-events"
            qemu_log("npcm7xx_smbus_recv_fifo " "%s recv fifo: received %u, expected %u" "\n", id, received, expected);
#line 1095 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_npcm7xx_smbus_recv_fifo(const char * id, uint8_t received, uint8_t expected)
{
    if (true) {
        _nocheck__trace_npcm7xx_smbus_recv_fifo(id, received, expected);
    }
}

#define TRACE_PCA954X_WRITE_BYTES_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCA954X_WRITE_BYTES) || \
    false)

static inline void _nocheck__trace_pca954x_write_bytes(uint8_t value)
{
    if (trace_event_get_state(TRACE_PCA954X_WRITE_BYTES) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 57 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:pca954x_write_bytes " "PCA954X write data: 0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , value);
#line 1122 "trace/trace-hw_i2c.h"
        } else {
#line 57 "../hw/i2c/trace-events"
            qemu_log("pca954x_write_bytes " "PCA954X write data: 0x%02x" "\n", value);
#line 1126 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_pca954x_write_bytes(uint8_t value)
{
    if (true) {
        _nocheck__trace_pca954x_write_bytes(value);
    }
}

#define TRACE_PCA954X_READ_DATA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PCA954X_READ_DATA) || \
    false)

static inline void _nocheck__trace_pca954x_read_data(uint8_t value)
{
    if (trace_event_get_state(TRACE_PCA954X_READ_DATA) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 58 "../hw/i2c/trace-events"
            qemu_log("%d@%zu.%06zu:pca954x_read_data " "PCA954X read data: 0x%02x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , value);
#line 1153 "trace/trace-hw_i2c.h"
        } else {
#line 58 "../hw/i2c/trace-events"
            qemu_log("pca954x_read_data " "PCA954X read data: 0x%02x" "\n", value);
#line 1157 "trace/trace-hw_i2c.h"
        }
    }
}

static inline void trace_pca954x_read_data(uint8_t value)
{
    if (true) {
        _nocheck__trace_pca954x_read_data(value);
    }
}
#endif /* TRACE_HW_I2C_GENERATED_TRACERS_H */