/* This file is autogenerated by tracetool, do not edit. */ #ifndef TRACE_HW_INTC_GENERATED_TRACERS_H #define TRACE_HW_INTC_GENERATED_TRACERS_H #include "trace/control.h" extern TraceEvent _TRACE_PIC_UPDATE_IRQ_EVENT; extern TraceEvent _TRACE_PIC_SET_IRQ_EVENT; extern TraceEvent _TRACE_PIC_INTERRUPT_EVENT; extern TraceEvent _TRACE_PIC_IOPORT_WRITE_EVENT; extern TraceEvent _TRACE_PIC_IOPORT_READ_EVENT; extern TraceEvent _TRACE_CPU_SET_APIC_BASE_EVENT; extern TraceEvent _TRACE_CPU_GET_APIC_BASE_EVENT; extern TraceEvent _TRACE_APIC_LOCAL_DELIVER_EVENT; extern TraceEvent _TRACE_APIC_DELIVER_IRQ_EVENT; extern TraceEvent _TRACE_APIC_REGISTER_READ_EVENT; extern TraceEvent _TRACE_APIC_REGISTER_WRITE_EVENT; extern TraceEvent _TRACE_IOAPIC_SET_REMOTE_IRR_EVENT; extern TraceEvent _TRACE_IOAPIC_CLEAR_REMOTE_IRR_EVENT; extern TraceEvent _TRACE_IOAPIC_EOI_BROADCAST_EVENT; extern TraceEvent _TRACE_IOAPIC_EOI_DELAYED_REASSERT_EVENT; extern TraceEvent _TRACE_IOAPIC_MEM_READ_EVENT; extern TraceEvent _TRACE_IOAPIC_MEM_WRITE_EVENT; extern TraceEvent _TRACE_IOAPIC_SET_IRQ_EVENT; extern TraceEvent _TRACE_KVM_REPORT_IRQ_DELIVERED_EVENT; extern TraceEvent _TRACE_KVM_RESET_IRQ_DELIVERED_EVENT; extern TraceEvent _TRACE_KVM_GET_IRQ_DELIVERED_EVENT; extern TraceEvent _TRACE_SLAVIO_INTCTL_MEM_READL_EVENT; extern TraceEvent _TRACE_SLAVIO_INTCTL_MEM_WRITEL_EVENT; extern TraceEvent _TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_EVENT; extern TraceEvent _TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_EVENT; extern TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_READL_EVENT; extern TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_EVENT; extern TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_EVENT; extern TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_EVENT; extern TraceEvent _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_EVENT; extern TraceEvent _TRACE_SLAVIO_CHECK_INTERRUPTS_EVENT; extern TraceEvent _TRACE_SLAVIO_SET_IRQ_EVENT; extern TraceEvent _TRACE_SLAVIO_SET_TIMER_IRQ_CPU_EVENT; extern TraceEvent _TRACE_GRLIB_IRQMP_CHECK_IRQS_EVENT; extern TraceEvent _TRACE_GRLIB_IRQMP_ACK_EVENT; extern TraceEvent _TRACE_GRLIB_IRQMP_SET_IRQ_EVENT; extern TraceEvent _TRACE_GRLIB_IRQMP_READL_UNKNOWN_EVENT; extern TraceEvent _TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_EVENT; extern TraceEvent _TRACE_XICS_ICP_CHECK_IPI_EVENT; extern TraceEvent _TRACE_XICS_ICP_ACCEPT_EVENT; extern TraceEvent _TRACE_XICS_ICP_EOI_EVENT; extern TraceEvent _TRACE_XICS_ICP_IRQ_EVENT; extern TraceEvent _TRACE_XICS_ICP_RAISE_EVENT; extern TraceEvent _TRACE_XICS_ICS_SET_IRQ_MSI_EVENT; extern TraceEvent _TRACE_XICS_MASKED_PENDING_EVENT; extern TraceEvent _TRACE_XICS_ICS_SET_IRQ_LSI_EVENT; extern TraceEvent _TRACE_XICS_ICS_WRITE_XIVE_EVENT; extern TraceEvent _TRACE_XICS_ICS_REJECT_EVENT; extern TraceEvent _TRACE_XICS_ICS_EOI_EVENT; extern TraceEvent _TRACE_FLIC_CREATE_DEVICE_EVENT; extern TraceEvent _TRACE_FLIC_RESET_FAILED_EVENT; extern TraceEvent _TRACE_QEMU_S390_AIRQ_SUPPRESSED_EVENT; extern TraceEvent _TRACE_QEMU_S390_SUPPRESS_AIRQ_EVENT; extern TraceEvent _TRACE_ASPEED_VIC_SET_IRQ_EVENT; extern TraceEvent _TRACE_ASPEED_VIC_UPDATE_FIQ_EVENT; extern TraceEvent _TRACE_ASPEED_VIC_UPDATE_IRQ_EVENT; extern TraceEvent _TRACE_ASPEED_VIC_READ_EVENT; extern TraceEvent _TRACE_ASPEED_VIC_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_READ_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_SET_IRQ_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_CLEAR_IRQ_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_UPDATE_IRQ_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_PENDING_IRQ_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_TRIGGER_IRQ_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_ALL_ISR_DONE_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_ENABLE_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_SELECT_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_MASK_EVENT; extern TraceEvent _TRACE_ASPEED_INTC_UNMASK_EVENT; extern TraceEvent _TRACE_GIC_ENABLE_IRQ_EVENT; extern TraceEvent _TRACE_GIC_DISABLE_IRQ_EVENT; extern TraceEvent _TRACE_GIC_SET_IRQ_EVENT; extern TraceEvent _TRACE_GIC_UPDATE_BESTIRQ_EVENT; extern TraceEvent _TRACE_GIC_UPDATE_SET_IRQ_EVENT; extern TraceEvent _TRACE_GIC_ACKNOWLEDGE_IRQ_EVENT; extern TraceEvent _TRACE_GIC_CPU_WRITE_EVENT; extern TraceEvent _TRACE_GIC_CPU_READ_EVENT; extern TraceEvent _TRACE_GIC_HYP_READ_EVENT; extern TraceEvent _TRACE_GIC_HYP_WRITE_EVENT; extern TraceEvent _TRACE_GIC_DIST_READ_EVENT; extern TraceEvent _TRACE_GIC_DIST_WRITE_EVENT; extern TraceEvent _TRACE_GIC_LR_ENTRY_EVENT; extern TraceEvent _TRACE_GIC_UPDATE_MAINTENANCE_IRQ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_PMR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_PMR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICC_BPR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_BPR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICC_AP_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_AP_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICC_IGRPEN_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_IGRPEN_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICC_IGRPEN1_EL3_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICC_CTLR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_CTLR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICC_CTLR_EL3_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_CTLR_EL3_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_CPUIF_UPDATE_EVENT; extern TraceEvent _TRACE_GICV3_CPUIF_SET_IRQS_EVENT; extern TraceEvent _TRACE_GICV3_ICC_GENERATE_SGI_EVENT; extern TraceEvent _TRACE_GICV3_ICC_IAR0_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_IAR1_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_NMIAR1_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_EOIR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICC_HPPIR0_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_HPPIR1_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICC_DIR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICC_RPR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICH_AP_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICH_AP_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICH_HCR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICH_HCR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICH_VMCR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICH_VMCR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICH_LR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICH_LR32_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICH_LRC_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICH_LR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICH_LR32_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICH_LRC_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICH_VTR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICH_MISR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICH_EISR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICH_ELRSR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICV_AP_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICV_AP_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICV_BPR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICV_BPR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICV_PMR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICV_PMR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICV_IGRPEN_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICV_IGRPEN_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICV_CTLR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICV_CTLR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICV_RPR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICV_HPPIR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICV_DIR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ICV_IAR_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICV_NMIAR1_READ_EVENT; extern TraceEvent _TRACE_GICV3_ICV_EOIR_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_CPUIF_VIRT_UPDATE_EVENT; extern TraceEvent _TRACE_GICV3_CPUIF_VIRT_SET_IRQS_EVENT; extern TraceEvent _TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ_EVENT; extern TraceEvent _TRACE_GICV3_DIST_READ_EVENT; extern TraceEvent _TRACE_GICV3_DIST_BADREAD_EVENT; extern TraceEvent _TRACE_GICV3_DIST_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_DIST_BADWRITE_EVENT; extern TraceEvent _TRACE_GICV3_DIST_SET_IRQ_EVENT; extern TraceEvent _TRACE_GICV3_REDIST_READ_EVENT; extern TraceEvent _TRACE_GICV3_REDIST_BADREAD_EVENT; extern TraceEvent _TRACE_GICV3_REDIST_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_REDIST_BADWRITE_EVENT; extern TraceEvent _TRACE_GICV3_REDIST_SET_IRQ_EVENT; extern TraceEvent _TRACE_GICV3_REDIST_SEND_SGI_EVENT; extern TraceEvent _TRACE_GICV3_ITS_READ_EVENT; extern TraceEvent _TRACE_GICV3_ITS_BADREAD_EVENT; extern TraceEvent _TRACE_GICV3_ITS_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ITS_BADWRITE_EVENT; extern TraceEvent _TRACE_GICV3_ITS_TRANSLATION_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ITS_PROCESS_COMMAND_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_INT_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_CLEAR_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_DISCARD_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_SYNC_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_MAPD_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_MAPC_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_MAPI_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_MAPTI_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_INV_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_INVALL_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_MOVALL_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_MOVI_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_VMAPI_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_VMAPTI_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_VMAPP_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_VMOVP_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_VSYNC_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_VMOVI_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_VINVALL_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CMD_UNKNOWN_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CTE_READ_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CTE_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ITS_CTE_READ_FAULT_EVENT; extern TraceEvent _TRACE_GICV3_ITS_ITE_READ_EVENT; extern TraceEvent _TRACE_GICV3_ITS_ITE_READ_FAULT_EVENT; extern TraceEvent _TRACE_GICV3_ITS_ITE_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ITS_DTE_READ_EVENT; extern TraceEvent _TRACE_GICV3_ITS_DTE_WRITE_EVENT; extern TraceEvent _TRACE_GICV3_ITS_DTE_READ_FAULT_EVENT; extern TraceEvent _TRACE_GICV3_ITS_VTE_READ_EVENT; extern TraceEvent _TRACE_GICV3_ITS_VTE_READ_FAULT_EVENT; extern TraceEvent _TRACE_GICV3_ITS_VTE_WRITE_EVENT; extern TraceEvent _TRACE_NVIC_RECOMPUTE_STATE_EVENT; extern TraceEvent _TRACE_NVIC_RECOMPUTE_STATE_SECURE_EVENT; extern TraceEvent _TRACE_NVIC_SET_PRIO_EVENT; extern TraceEvent _TRACE_NVIC_IRQ_UPDATE_EVENT; extern TraceEvent _TRACE_NVIC_ESCALATE_PRIO_EVENT; extern TraceEvent _TRACE_NVIC_ESCALATE_DISABLED_EVENT; extern TraceEvent _TRACE_NVIC_SET_PENDING_EVENT; extern TraceEvent _TRACE_NVIC_CLEAR_PENDING_EVENT; extern TraceEvent _TRACE_NVIC_ACKNOWLEDGE_IRQ_EVENT; extern TraceEvent _TRACE_NVIC_GET_PENDING_IRQ_INFO_EVENT; extern TraceEvent _TRACE_NVIC_COMPLETE_IRQ_EVENT; extern TraceEvent _TRACE_NVIC_SET_IRQ_LEVEL_EVENT; extern TraceEvent _TRACE_NVIC_SET_NMI_LEVEL_EVENT; extern TraceEvent _TRACE_NVIC_SYSREG_READ_EVENT; extern TraceEvent _TRACE_NVIC_SYSREG_WRITE_EVENT; extern TraceEvent _TRACE_HEATHROW_WRITE_EVENT; extern TraceEvent _TRACE_HEATHROW_READ_EVENT; extern TraceEvent _TRACE_HEATHROW_SET_IRQ_EVENT; extern TraceEvent _TRACE_BCM2835_IC_SET_GPU_IRQ_EVENT; extern TraceEvent _TRACE_BCM2835_IC_SET_CPU_IRQ_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_CLAIM_IRQ_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_FREE_IRQ_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_SET_IRQ_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_GET_SOURCE_INFO_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_GET_QUEUE_INFO_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_ESB_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_SYNC_EVENT; extern TraceEvent _TRACE_SPAPR_XIVE_RESET_EVENT; extern TraceEvent _TRACE_KVM_XIVE_CPU_CONNECT_EVENT; extern TraceEvent _TRACE_KVM_XIVE_SOURCE_RESET_EVENT; extern TraceEvent _TRACE_XIVE_TCTX_ACCEPT_EVENT; extern TraceEvent _TRACE_XIVE_TCTX_NOTIFY_EVENT; extern TraceEvent _TRACE_XIVE_TCTX_SET_CPPR_EVENT; extern TraceEvent _TRACE_XIVE_SOURCE_ESB_READ_EVENT; extern TraceEvent _TRACE_XIVE_SOURCE_ESB_WRITE_EVENT; extern TraceEvent _TRACE_XIVE_ROUTER_END_NOTIFY_EVENT; extern TraceEvent _TRACE_XIVE_ROUTER_END_ESCALATE_EVENT; extern TraceEvent _TRACE_XIVE_TCTX_TM_WRITE_EVENT; extern TraceEvent _TRACE_XIVE_TCTX_TM_READ_EVENT; extern TraceEvent _TRACE_XIVE_PRESENTER_NOTIFY_EVENT; extern TraceEvent _TRACE_XIVE_END_SOURCE_READ_EVENT; extern TraceEvent _TRACE_PNV_XIVE_IC_HW_TRIGGER_EVENT; extern TraceEvent _TRACE_GOLDFISH_IRQ_REQUEST_EVENT; extern TraceEvent _TRACE_GOLDFISH_PIC_READ_EVENT; extern TraceEvent _TRACE_GOLDFISH_PIC_WRITE_EVENT; extern TraceEvent _TRACE_GOLDFISH_PIC_RESET_EVENT; extern TraceEvent _TRACE_GOLDFISH_PIC_REALIZE_EVENT; extern TraceEvent _TRACE_GOLDFISH_PIC_INSTANCE_INIT_EVENT; extern TraceEvent _TRACE_SH_INTC_SOURCES_EVENT; extern TraceEvent _TRACE_SH_INTC_PENDING_EVENT; extern TraceEvent _TRACE_SH_INTC_REGISTER_EVENT; extern TraceEvent _TRACE_SH_INTC_READ_EVENT; extern TraceEvent _TRACE_SH_INTC_WRITE_EVENT; extern TraceEvent _TRACE_SH_INTC_SET_EVENT; extern TraceEvent _TRACE_LOONGSON_IPI_READ_EVENT; extern TraceEvent _TRACE_LOONGSON_IPI_WRITE_EVENT; extern TraceEvent _TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER_EVENT; extern TraceEvent _TRACE_LOONGARCH_PCH_PIC_LOW_READW_EVENT; extern TraceEvent _TRACE_LOONGARCH_PCH_PIC_LOW_WRITEW_EVENT; extern TraceEvent _TRACE_LOONGARCH_PCH_PIC_HIGH_READW_EVENT; extern TraceEvent _TRACE_LOONGARCH_PCH_PIC_HIGH_WRITEW_EVENT; extern TraceEvent _TRACE_LOONGARCH_PCH_PIC_READB_EVENT; extern TraceEvent _TRACE_LOONGARCH_PCH_PIC_WRITEB_EVENT; extern TraceEvent _TRACE_LOONGARCH_MSI_SET_IRQ_EVENT; extern TraceEvent _TRACE_LOONGARCH_EXTIOI_SETIRQ_EVENT; extern TraceEvent _TRACE_LOONGARCH_EXTIOI_READW_EVENT; extern TraceEvent _TRACE_LOONGARCH_EXTIOI_WRITEW_EVENT; extern uint16_t _TRACE_PIC_UPDATE_IRQ_DSTATE; extern uint16_t _TRACE_PIC_SET_IRQ_DSTATE; extern uint16_t _TRACE_PIC_INTERRUPT_DSTATE; extern uint16_t _TRACE_PIC_IOPORT_WRITE_DSTATE; extern uint16_t _TRACE_PIC_IOPORT_READ_DSTATE; extern uint16_t _TRACE_CPU_SET_APIC_BASE_DSTATE; extern uint16_t _TRACE_CPU_GET_APIC_BASE_DSTATE; extern uint16_t _TRACE_APIC_LOCAL_DELIVER_DSTATE; extern uint16_t _TRACE_APIC_DELIVER_IRQ_DSTATE; extern uint16_t _TRACE_APIC_REGISTER_READ_DSTATE; extern uint16_t _TRACE_APIC_REGISTER_WRITE_DSTATE; extern uint16_t _TRACE_IOAPIC_SET_REMOTE_IRR_DSTATE; extern uint16_t _TRACE_IOAPIC_CLEAR_REMOTE_IRR_DSTATE; extern uint16_t _TRACE_IOAPIC_EOI_BROADCAST_DSTATE; extern uint16_t _TRACE_IOAPIC_EOI_DELAYED_REASSERT_DSTATE; extern uint16_t _TRACE_IOAPIC_MEM_READ_DSTATE; extern uint16_t _TRACE_IOAPIC_MEM_WRITE_DSTATE; extern uint16_t _TRACE_IOAPIC_SET_IRQ_DSTATE; extern uint16_t _TRACE_KVM_REPORT_IRQ_DELIVERED_DSTATE; extern uint16_t _TRACE_KVM_RESET_IRQ_DELIVERED_DSTATE; extern uint16_t _TRACE_KVM_GET_IRQ_DELIVERED_DSTATE; extern uint16_t _TRACE_SLAVIO_INTCTL_MEM_READL_DSTATE; extern uint16_t _TRACE_SLAVIO_INTCTL_MEM_WRITEL_DSTATE; extern uint16_t _TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_DSTATE; extern uint16_t _TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_DSTATE; extern uint16_t _TRACE_SLAVIO_INTCTLM_MEM_READL_DSTATE; extern uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DSTATE; extern uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_DSTATE; extern uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_DSTATE; extern uint16_t _TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_DSTATE; extern uint16_t _TRACE_SLAVIO_CHECK_INTERRUPTS_DSTATE; extern uint16_t _TRACE_SLAVIO_SET_IRQ_DSTATE; extern uint16_t _TRACE_SLAVIO_SET_TIMER_IRQ_CPU_DSTATE; extern uint16_t _TRACE_GRLIB_IRQMP_CHECK_IRQS_DSTATE; extern uint16_t _TRACE_GRLIB_IRQMP_ACK_DSTATE; extern uint16_t _TRACE_GRLIB_IRQMP_SET_IRQ_DSTATE; extern uint16_t _TRACE_GRLIB_IRQMP_READL_UNKNOWN_DSTATE; extern uint16_t _TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_DSTATE; extern uint16_t _TRACE_XICS_ICP_CHECK_IPI_DSTATE; extern uint16_t _TRACE_XICS_ICP_ACCEPT_DSTATE; extern uint16_t _TRACE_XICS_ICP_EOI_DSTATE; extern uint16_t _TRACE_XICS_ICP_IRQ_DSTATE; extern uint16_t _TRACE_XICS_ICP_RAISE_DSTATE; extern uint16_t _TRACE_XICS_ICS_SET_IRQ_MSI_DSTATE; extern uint16_t _TRACE_XICS_MASKED_PENDING_DSTATE; extern uint16_t _TRACE_XICS_ICS_SET_IRQ_LSI_DSTATE; extern uint16_t _TRACE_XICS_ICS_WRITE_XIVE_DSTATE; extern uint16_t _TRACE_XICS_ICS_REJECT_DSTATE; extern uint16_t _TRACE_XICS_ICS_EOI_DSTATE; extern uint16_t _TRACE_FLIC_CREATE_DEVICE_DSTATE; extern uint16_t _TRACE_FLIC_RESET_FAILED_DSTATE; extern uint16_t _TRACE_QEMU_S390_AIRQ_SUPPRESSED_DSTATE; extern uint16_t _TRACE_QEMU_S390_SUPPRESS_AIRQ_DSTATE; extern uint16_t _TRACE_ASPEED_VIC_SET_IRQ_DSTATE; extern uint16_t _TRACE_ASPEED_VIC_UPDATE_FIQ_DSTATE; extern uint16_t _TRACE_ASPEED_VIC_UPDATE_IRQ_DSTATE; extern uint16_t _TRACE_ASPEED_VIC_READ_DSTATE; extern uint16_t _TRACE_ASPEED_VIC_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_READ_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_SET_IRQ_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_CLEAR_IRQ_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_UPDATE_IRQ_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_PENDING_IRQ_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_TRIGGER_IRQ_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_ALL_ISR_DONE_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_ENABLE_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_SELECT_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_MASK_DSTATE; extern uint16_t _TRACE_ASPEED_INTC_UNMASK_DSTATE; extern uint16_t _TRACE_GIC_ENABLE_IRQ_DSTATE; extern uint16_t _TRACE_GIC_DISABLE_IRQ_DSTATE; extern uint16_t _TRACE_GIC_SET_IRQ_DSTATE; extern uint16_t _TRACE_GIC_UPDATE_BESTIRQ_DSTATE; extern uint16_t _TRACE_GIC_UPDATE_SET_IRQ_DSTATE; extern uint16_t _TRACE_GIC_ACKNOWLEDGE_IRQ_DSTATE; extern uint16_t _TRACE_GIC_CPU_WRITE_DSTATE; extern uint16_t _TRACE_GIC_CPU_READ_DSTATE; extern uint16_t _TRACE_GIC_HYP_READ_DSTATE; extern uint16_t _TRACE_GIC_HYP_WRITE_DSTATE; extern uint16_t _TRACE_GIC_DIST_READ_DSTATE; extern uint16_t _TRACE_GIC_DIST_WRITE_DSTATE; extern uint16_t _TRACE_GIC_LR_ENTRY_DSTATE; extern uint16_t _TRACE_GIC_UPDATE_MAINTENANCE_IRQ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_PMR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_PMR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICC_BPR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_BPR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICC_AP_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_AP_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICC_IGRPEN_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_IGRPEN_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICC_IGRPEN1_EL3_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICC_CTLR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_CTLR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICC_CTLR_EL3_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_CTLR_EL3_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_CPUIF_UPDATE_DSTATE; extern uint16_t _TRACE_GICV3_CPUIF_SET_IRQS_DSTATE; extern uint16_t _TRACE_GICV3_ICC_GENERATE_SGI_DSTATE; extern uint16_t _TRACE_GICV3_ICC_IAR0_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_IAR1_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_NMIAR1_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_EOIR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICC_HPPIR0_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_HPPIR1_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICC_DIR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICC_RPR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICH_AP_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICH_AP_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICH_HCR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICH_HCR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICH_VMCR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICH_VMCR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICH_LR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICH_LR32_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICH_LRC_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICH_LR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICH_LR32_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICH_LRC_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICH_VTR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICH_MISR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICH_EISR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICH_ELRSR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICV_AP_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICV_AP_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICV_BPR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICV_BPR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICV_PMR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICV_PMR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICV_IGRPEN_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICV_IGRPEN_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICV_CTLR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICV_CTLR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICV_RPR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICV_HPPIR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICV_DIR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ICV_IAR_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICV_NMIAR1_READ_DSTATE; extern uint16_t _TRACE_GICV3_ICV_EOIR_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_CPUIF_VIRT_UPDATE_DSTATE; extern uint16_t _TRACE_GICV3_CPUIF_VIRT_SET_IRQS_DSTATE; extern uint16_t _TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ_DSTATE; extern uint16_t _TRACE_GICV3_DIST_READ_DSTATE; extern uint16_t _TRACE_GICV3_DIST_BADREAD_DSTATE; extern uint16_t _TRACE_GICV3_DIST_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_DIST_BADWRITE_DSTATE; extern uint16_t _TRACE_GICV3_DIST_SET_IRQ_DSTATE; extern uint16_t _TRACE_GICV3_REDIST_READ_DSTATE; extern uint16_t _TRACE_GICV3_REDIST_BADREAD_DSTATE; extern uint16_t _TRACE_GICV3_REDIST_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_REDIST_BADWRITE_DSTATE; extern uint16_t _TRACE_GICV3_REDIST_SET_IRQ_DSTATE; extern uint16_t _TRACE_GICV3_REDIST_SEND_SGI_DSTATE; extern uint16_t _TRACE_GICV3_ITS_READ_DSTATE; extern uint16_t _TRACE_GICV3_ITS_BADREAD_DSTATE; extern uint16_t _TRACE_GICV3_ITS_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ITS_BADWRITE_DSTATE; extern uint16_t _TRACE_GICV3_ITS_TRANSLATION_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ITS_PROCESS_COMMAND_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_INT_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_CLEAR_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_DISCARD_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_SYNC_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_MAPD_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_MAPC_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_MAPI_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_MAPTI_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_INV_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_INVALL_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_MOVALL_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_MOVI_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_VMAPI_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_VMAPTI_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_VMAPP_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_VMOVP_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_VSYNC_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_VMOVI_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_VINVALL_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CMD_UNKNOWN_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CTE_READ_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CTE_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ITS_CTE_READ_FAULT_DSTATE; extern uint16_t _TRACE_GICV3_ITS_ITE_READ_DSTATE; extern uint16_t _TRACE_GICV3_ITS_ITE_READ_FAULT_DSTATE; extern uint16_t _TRACE_GICV3_ITS_ITE_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ITS_DTE_READ_DSTATE; extern uint16_t _TRACE_GICV3_ITS_DTE_WRITE_DSTATE; extern uint16_t _TRACE_GICV3_ITS_DTE_READ_FAULT_DSTATE; extern uint16_t _TRACE_GICV3_ITS_VTE_READ_DSTATE; extern uint16_t _TRACE_GICV3_ITS_VTE_READ_FAULT_DSTATE; extern uint16_t _TRACE_GICV3_ITS_VTE_WRITE_DSTATE; extern uint16_t _TRACE_NVIC_RECOMPUTE_STATE_DSTATE; extern uint16_t _TRACE_NVIC_RECOMPUTE_STATE_SECURE_DSTATE; extern uint16_t _TRACE_NVIC_SET_PRIO_DSTATE; extern uint16_t _TRACE_NVIC_IRQ_UPDATE_DSTATE; extern uint16_t _TRACE_NVIC_ESCALATE_PRIO_DSTATE; extern uint16_t _TRACE_NVIC_ESCALATE_DISABLED_DSTATE; extern uint16_t _TRACE_NVIC_SET_PENDING_DSTATE; extern uint16_t _TRACE_NVIC_CLEAR_PENDING_DSTATE; extern uint16_t _TRACE_NVIC_ACKNOWLEDGE_IRQ_DSTATE; extern uint16_t _TRACE_NVIC_GET_PENDING_IRQ_INFO_DSTATE; extern uint16_t _TRACE_NVIC_COMPLETE_IRQ_DSTATE; extern uint16_t _TRACE_NVIC_SET_IRQ_LEVEL_DSTATE; extern uint16_t _TRACE_NVIC_SET_NMI_LEVEL_DSTATE; extern uint16_t _TRACE_NVIC_SYSREG_READ_DSTATE; extern uint16_t _TRACE_NVIC_SYSREG_WRITE_DSTATE; extern uint16_t _TRACE_HEATHROW_WRITE_DSTATE; extern uint16_t _TRACE_HEATHROW_READ_DSTATE; extern uint16_t _TRACE_HEATHROW_SET_IRQ_DSTATE; extern uint16_t _TRACE_BCM2835_IC_SET_GPU_IRQ_DSTATE; extern uint16_t _TRACE_BCM2835_IC_SET_CPU_IRQ_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_CLAIM_IRQ_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_FREE_IRQ_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_SET_IRQ_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_GET_SOURCE_INFO_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_GET_QUEUE_INFO_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_ESB_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_SYNC_DSTATE; extern uint16_t _TRACE_SPAPR_XIVE_RESET_DSTATE; extern uint16_t _TRACE_KVM_XIVE_CPU_CONNECT_DSTATE; extern uint16_t _TRACE_KVM_XIVE_SOURCE_RESET_DSTATE; extern uint16_t _TRACE_XIVE_TCTX_ACCEPT_DSTATE; extern uint16_t _TRACE_XIVE_TCTX_NOTIFY_DSTATE; extern uint16_t _TRACE_XIVE_TCTX_SET_CPPR_DSTATE; extern uint16_t _TRACE_XIVE_SOURCE_ESB_READ_DSTATE; extern uint16_t _TRACE_XIVE_SOURCE_ESB_WRITE_DSTATE; extern uint16_t _TRACE_XIVE_ROUTER_END_NOTIFY_DSTATE; extern uint16_t _TRACE_XIVE_ROUTER_END_ESCALATE_DSTATE; extern uint16_t _TRACE_XIVE_TCTX_TM_WRITE_DSTATE; extern uint16_t _TRACE_XIVE_TCTX_TM_READ_DSTATE; extern uint16_t _TRACE_XIVE_PRESENTER_NOTIFY_DSTATE; extern uint16_t _TRACE_XIVE_END_SOURCE_READ_DSTATE; extern uint16_t _TRACE_PNV_XIVE_IC_HW_TRIGGER_DSTATE; extern uint16_t _TRACE_GOLDFISH_IRQ_REQUEST_DSTATE; extern uint16_t _TRACE_GOLDFISH_PIC_READ_DSTATE; extern uint16_t _TRACE_GOLDFISH_PIC_WRITE_DSTATE; extern uint16_t _TRACE_GOLDFISH_PIC_RESET_DSTATE; extern uint16_t _TRACE_GOLDFISH_PIC_REALIZE_DSTATE; extern uint16_t _TRACE_GOLDFISH_PIC_INSTANCE_INIT_DSTATE; extern uint16_t _TRACE_SH_INTC_SOURCES_DSTATE; extern uint16_t _TRACE_SH_INTC_PENDING_DSTATE; extern uint16_t _TRACE_SH_INTC_REGISTER_DSTATE; extern uint16_t _TRACE_SH_INTC_READ_DSTATE; extern uint16_t _TRACE_SH_INTC_WRITE_DSTATE; extern uint16_t _TRACE_SH_INTC_SET_DSTATE; extern uint16_t _TRACE_LOONGSON_IPI_READ_DSTATE; extern uint16_t _TRACE_LOONGSON_IPI_WRITE_DSTATE; extern uint16_t _TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER_DSTATE; extern uint16_t _TRACE_LOONGARCH_PCH_PIC_LOW_READW_DSTATE; extern uint16_t _TRACE_LOONGARCH_PCH_PIC_LOW_WRITEW_DSTATE; extern uint16_t _TRACE_LOONGARCH_PCH_PIC_HIGH_READW_DSTATE; extern uint16_t _TRACE_LOONGARCH_PCH_PIC_HIGH_WRITEW_DSTATE; extern uint16_t _TRACE_LOONGARCH_PCH_PIC_READB_DSTATE; extern uint16_t _TRACE_LOONGARCH_PCH_PIC_WRITEB_DSTATE; extern uint16_t _TRACE_LOONGARCH_MSI_SET_IRQ_DSTATE; extern uint16_t _TRACE_LOONGARCH_EXTIOI_SETIRQ_DSTATE; extern uint16_t _TRACE_LOONGARCH_EXTIOI_READW_DSTATE; extern uint16_t _TRACE_LOONGARCH_EXTIOI_WRITEW_DSTATE; #define TRACE_PIC_UPDATE_IRQ_ENABLED 1 #define TRACE_PIC_SET_IRQ_ENABLED 1 #define TRACE_PIC_INTERRUPT_ENABLED 1 #define TRACE_PIC_IOPORT_WRITE_ENABLED 1 #define TRACE_PIC_IOPORT_READ_ENABLED 1 #define TRACE_CPU_SET_APIC_BASE_ENABLED 1 #define TRACE_CPU_GET_APIC_BASE_ENABLED 1 #define TRACE_APIC_LOCAL_DELIVER_ENABLED 1 #define TRACE_APIC_DELIVER_IRQ_ENABLED 1 #define TRACE_APIC_REGISTER_READ_ENABLED 1 #define TRACE_APIC_REGISTER_WRITE_ENABLED 1 #define TRACE_IOAPIC_SET_REMOTE_IRR_ENABLED 1 #define TRACE_IOAPIC_CLEAR_REMOTE_IRR_ENABLED 1 #define TRACE_IOAPIC_EOI_BROADCAST_ENABLED 1 #define TRACE_IOAPIC_EOI_DELAYED_REASSERT_ENABLED 1 #define TRACE_IOAPIC_MEM_READ_ENABLED 1 #define TRACE_IOAPIC_MEM_WRITE_ENABLED 1 #define TRACE_IOAPIC_SET_IRQ_ENABLED 1 #define TRACE_KVM_REPORT_IRQ_DELIVERED_ENABLED 1 #define TRACE_KVM_RESET_IRQ_DELIVERED_ENABLED 1 #define TRACE_KVM_GET_IRQ_DELIVERED_ENABLED 1 #define TRACE_SLAVIO_INTCTL_MEM_READL_ENABLED 1 #define TRACE_SLAVIO_INTCTL_MEM_WRITEL_ENABLED 1 #define TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_ENABLED 1 #define TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_ENABLED 1 #define TRACE_SLAVIO_INTCTLM_MEM_READL_ENABLED 1 #define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLED 1 #define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_ENABLED 1 #define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_ENABLED 1 #define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_ENABLED 1 #define TRACE_SLAVIO_CHECK_INTERRUPTS_ENABLED 1 #define TRACE_SLAVIO_SET_IRQ_ENABLED 1 #define TRACE_SLAVIO_SET_TIMER_IRQ_CPU_ENABLED 1 #define TRACE_GRLIB_IRQMP_CHECK_IRQS_ENABLED 1 #define TRACE_GRLIB_IRQMP_ACK_ENABLED 1 #define TRACE_GRLIB_IRQMP_SET_IRQ_ENABLED 1 #define TRACE_GRLIB_IRQMP_READL_UNKNOWN_ENABLED 1 #define TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_ENABLED 1 #define TRACE_XICS_ICP_CHECK_IPI_ENABLED 1 #define TRACE_XICS_ICP_ACCEPT_ENABLED 1 #define TRACE_XICS_ICP_EOI_ENABLED 1 #define TRACE_XICS_ICP_IRQ_ENABLED 1 #define TRACE_XICS_ICP_RAISE_ENABLED 1 #define TRACE_XICS_ICS_SET_IRQ_MSI_ENABLED 1 #define TRACE_XICS_MASKED_PENDING_ENABLED 1 #define TRACE_XICS_ICS_SET_IRQ_LSI_ENABLED 1 #define TRACE_XICS_ICS_WRITE_XIVE_ENABLED 1 #define TRACE_XICS_ICS_REJECT_ENABLED 1 #define TRACE_XICS_ICS_EOI_ENABLED 1 #define TRACE_FLIC_CREATE_DEVICE_ENABLED 1 #define TRACE_FLIC_RESET_FAILED_ENABLED 1 #define TRACE_QEMU_S390_AIRQ_SUPPRESSED_ENABLED 1 #define TRACE_QEMU_S390_SUPPRESS_AIRQ_ENABLED 1 #define TRACE_ASPEED_VIC_SET_IRQ_ENABLED 1 #define TRACE_ASPEED_VIC_UPDATE_FIQ_ENABLED 1 #define TRACE_ASPEED_VIC_UPDATE_IRQ_ENABLED 1 #define TRACE_ASPEED_VIC_READ_ENABLED 1 #define TRACE_ASPEED_VIC_WRITE_ENABLED 1 #define TRACE_ASPEED_INTC_READ_ENABLED 1 #define TRACE_ASPEED_INTC_WRITE_ENABLED 1 #define TRACE_ASPEED_INTC_SET_IRQ_ENABLED 1 #define TRACE_ASPEED_INTC_CLEAR_IRQ_ENABLED 1 #define TRACE_ASPEED_INTC_UPDATE_IRQ_ENABLED 1 #define TRACE_ASPEED_INTC_PENDING_IRQ_ENABLED 1 #define TRACE_ASPEED_INTC_TRIGGER_IRQ_ENABLED 1 #define TRACE_ASPEED_INTC_ALL_ISR_DONE_ENABLED 1 #define TRACE_ASPEED_INTC_ENABLE_ENABLED 1 #define TRACE_ASPEED_INTC_SELECT_ENABLED 1 #define TRACE_ASPEED_INTC_MASK_ENABLED 1 #define TRACE_ASPEED_INTC_UNMASK_ENABLED 1 #define TRACE_GIC_ENABLE_IRQ_ENABLED 1 #define TRACE_GIC_DISABLE_IRQ_ENABLED 1 #define TRACE_GIC_SET_IRQ_ENABLED 1 #define TRACE_GIC_UPDATE_BESTIRQ_ENABLED 1 #define TRACE_GIC_UPDATE_SET_IRQ_ENABLED 1 #define TRACE_GIC_ACKNOWLEDGE_IRQ_ENABLED 1 #define TRACE_GIC_CPU_WRITE_ENABLED 1 #define TRACE_GIC_CPU_READ_ENABLED 1 #define TRACE_GIC_HYP_READ_ENABLED 1 #define TRACE_GIC_HYP_WRITE_ENABLED 1 #define TRACE_GIC_DIST_READ_ENABLED 1 #define TRACE_GIC_DIST_WRITE_ENABLED 1 #define TRACE_GIC_LR_ENTRY_ENABLED 1 #define TRACE_GIC_UPDATE_MAINTENANCE_IRQ_ENABLED 1 #define TRACE_GICV3_ICC_PMR_READ_ENABLED 1 #define TRACE_GICV3_ICC_PMR_WRITE_ENABLED 1 #define TRACE_GICV3_ICC_BPR_READ_ENABLED 1 #define TRACE_GICV3_ICC_BPR_WRITE_ENABLED 1 #define TRACE_GICV3_ICC_AP_READ_ENABLED 1 #define TRACE_GICV3_ICC_AP_WRITE_ENABLED 1 #define TRACE_GICV3_ICC_IGRPEN_READ_ENABLED 1 #define TRACE_GICV3_ICC_IGRPEN_WRITE_ENABLED 1 #define TRACE_GICV3_ICC_IGRPEN1_EL3_READ_ENABLED 1 #define TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_ENABLED 1 #define TRACE_GICV3_ICC_CTLR_READ_ENABLED 1 #define TRACE_GICV3_ICC_CTLR_WRITE_ENABLED 1 #define TRACE_GICV3_ICC_CTLR_EL3_READ_ENABLED 1 #define TRACE_GICV3_ICC_CTLR_EL3_WRITE_ENABLED 1 #define TRACE_GICV3_CPUIF_UPDATE_ENABLED 1 #define TRACE_GICV3_CPUIF_SET_IRQS_ENABLED 1 #define TRACE_GICV3_ICC_GENERATE_SGI_ENABLED 1 #define TRACE_GICV3_ICC_IAR0_READ_ENABLED 1 #define TRACE_GICV3_ICC_IAR1_READ_ENABLED 1 #define TRACE_GICV3_ICC_NMIAR1_READ_ENABLED 1 #define TRACE_GICV3_ICC_EOIR_WRITE_ENABLED 1 #define TRACE_GICV3_ICC_HPPIR0_READ_ENABLED 1 #define TRACE_GICV3_ICC_HPPIR1_READ_ENABLED 1 #define TRACE_GICV3_ICC_DIR_WRITE_ENABLED 1 #define TRACE_GICV3_ICC_RPR_READ_ENABLED 1 #define TRACE_GICV3_ICH_AP_READ_ENABLED 1 #define TRACE_GICV3_ICH_AP_WRITE_ENABLED 1 #define TRACE_GICV3_ICH_HCR_READ_ENABLED 1 #define TRACE_GICV3_ICH_HCR_WRITE_ENABLED 1 #define TRACE_GICV3_ICH_VMCR_READ_ENABLED 1 #define TRACE_GICV3_ICH_VMCR_WRITE_ENABLED 1 #define TRACE_GICV3_ICH_LR_READ_ENABLED 1 #define TRACE_GICV3_ICH_LR32_READ_ENABLED 1 #define TRACE_GICV3_ICH_LRC_READ_ENABLED 1 #define TRACE_GICV3_ICH_LR_WRITE_ENABLED 1 #define TRACE_GICV3_ICH_LR32_WRITE_ENABLED 1 #define TRACE_GICV3_ICH_LRC_WRITE_ENABLED 1 #define TRACE_GICV3_ICH_VTR_READ_ENABLED 1 #define TRACE_GICV3_ICH_MISR_READ_ENABLED 1 #define TRACE_GICV3_ICH_EISR_READ_ENABLED 1 #define TRACE_GICV3_ICH_ELRSR_READ_ENABLED 1 #define TRACE_GICV3_ICV_AP_READ_ENABLED 1 #define TRACE_GICV3_ICV_AP_WRITE_ENABLED 1 #define TRACE_GICV3_ICV_BPR_READ_ENABLED 1 #define TRACE_GICV3_ICV_BPR_WRITE_ENABLED 1 #define TRACE_GICV3_ICV_PMR_READ_ENABLED 1 #define TRACE_GICV3_ICV_PMR_WRITE_ENABLED 1 #define TRACE_GICV3_ICV_IGRPEN_READ_ENABLED 1 #define TRACE_GICV3_ICV_IGRPEN_WRITE_ENABLED 1 #define TRACE_GICV3_ICV_CTLR_READ_ENABLED 1 #define TRACE_GICV3_ICV_CTLR_WRITE_ENABLED 1 #define TRACE_GICV3_ICV_RPR_READ_ENABLED 1 #define TRACE_GICV3_ICV_HPPIR_READ_ENABLED 1 #define TRACE_GICV3_ICV_DIR_WRITE_ENABLED 1 #define TRACE_GICV3_ICV_IAR_READ_ENABLED 1 #define TRACE_GICV3_ICV_NMIAR1_READ_ENABLED 1 #define TRACE_GICV3_ICV_EOIR_WRITE_ENABLED 1 #define TRACE_GICV3_CPUIF_VIRT_UPDATE_ENABLED 1 #define TRACE_GICV3_CPUIF_VIRT_SET_IRQS_ENABLED 1 #define TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ_ENABLED 1 #define TRACE_GICV3_DIST_READ_ENABLED 1 #define TRACE_GICV3_DIST_BADREAD_ENABLED 1 #define TRACE_GICV3_DIST_WRITE_ENABLED 1 #define TRACE_GICV3_DIST_BADWRITE_ENABLED 1 #define TRACE_GICV3_DIST_SET_IRQ_ENABLED 1 #define TRACE_GICV3_REDIST_READ_ENABLED 1 #define TRACE_GICV3_REDIST_BADREAD_ENABLED 1 #define TRACE_GICV3_REDIST_WRITE_ENABLED 1 #define TRACE_GICV3_REDIST_BADWRITE_ENABLED 1 #define TRACE_GICV3_REDIST_SET_IRQ_ENABLED 1 #define TRACE_GICV3_REDIST_SEND_SGI_ENABLED 1 #define TRACE_GICV3_ITS_READ_ENABLED 1 #define TRACE_GICV3_ITS_BADREAD_ENABLED 1 #define TRACE_GICV3_ITS_WRITE_ENABLED 1 #define TRACE_GICV3_ITS_BADWRITE_ENABLED 1 #define TRACE_GICV3_ITS_TRANSLATION_WRITE_ENABLED 1 #define TRACE_GICV3_ITS_PROCESS_COMMAND_ENABLED 1 #define TRACE_GICV3_ITS_CMD_INT_ENABLED 1 #define TRACE_GICV3_ITS_CMD_CLEAR_ENABLED 1 #define TRACE_GICV3_ITS_CMD_DISCARD_ENABLED 1 #define TRACE_GICV3_ITS_CMD_SYNC_ENABLED 1 #define TRACE_GICV3_ITS_CMD_MAPD_ENABLED 1 #define TRACE_GICV3_ITS_CMD_MAPC_ENABLED 1 #define TRACE_GICV3_ITS_CMD_MAPI_ENABLED 1 #define TRACE_GICV3_ITS_CMD_MAPTI_ENABLED 1 #define TRACE_GICV3_ITS_CMD_INV_ENABLED 1 #define TRACE_GICV3_ITS_CMD_INVALL_ENABLED 1 #define TRACE_GICV3_ITS_CMD_MOVALL_ENABLED 1 #define TRACE_GICV3_ITS_CMD_MOVI_ENABLED 1 #define TRACE_GICV3_ITS_CMD_VMAPI_ENABLED 1 #define TRACE_GICV3_ITS_CMD_VMAPTI_ENABLED 1 #define TRACE_GICV3_ITS_CMD_VMAPP_ENABLED 1 #define TRACE_GICV3_ITS_CMD_VMOVP_ENABLED 1 #define TRACE_GICV3_ITS_CMD_VSYNC_ENABLED 1 #define TRACE_GICV3_ITS_CMD_VMOVI_ENABLED 1 #define TRACE_GICV3_ITS_CMD_VINVALL_ENABLED 1 #define TRACE_GICV3_ITS_CMD_UNKNOWN_ENABLED 1 #define TRACE_GICV3_ITS_CTE_READ_ENABLED 1 #define TRACE_GICV3_ITS_CTE_WRITE_ENABLED 1 #define TRACE_GICV3_ITS_CTE_READ_FAULT_ENABLED 1 #define TRACE_GICV3_ITS_ITE_READ_ENABLED 1 #define TRACE_GICV3_ITS_ITE_READ_FAULT_ENABLED 1 #define TRACE_GICV3_ITS_ITE_WRITE_ENABLED 1 #define TRACE_GICV3_ITS_DTE_READ_ENABLED 1 #define TRACE_GICV3_ITS_DTE_WRITE_ENABLED 1 #define TRACE_GICV3_ITS_DTE_READ_FAULT_ENABLED 1 #define TRACE_GICV3_ITS_VTE_READ_ENABLED 1 #define TRACE_GICV3_ITS_VTE_READ_FAULT_ENABLED 1 #define TRACE_GICV3_ITS_VTE_WRITE_ENABLED 1 #define TRACE_NVIC_RECOMPUTE_STATE_ENABLED 1 #define TRACE_NVIC_RECOMPUTE_STATE_SECURE_ENABLED 1 #define TRACE_NVIC_SET_PRIO_ENABLED 1 #define TRACE_NVIC_IRQ_UPDATE_ENABLED 1 #define TRACE_NVIC_ESCALATE_PRIO_ENABLED 1 #define TRACE_NVIC_ESCALATE_DISABLED_ENABLED 1 #define TRACE_NVIC_SET_PENDING_ENABLED 1 #define TRACE_NVIC_CLEAR_PENDING_ENABLED 1 #define TRACE_NVIC_ACKNOWLEDGE_IRQ_ENABLED 1 #define TRACE_NVIC_GET_PENDING_IRQ_INFO_ENABLED 1 #define TRACE_NVIC_COMPLETE_IRQ_ENABLED 1 #define TRACE_NVIC_SET_IRQ_LEVEL_ENABLED 1 #define TRACE_NVIC_SET_NMI_LEVEL_ENABLED 1 #define TRACE_NVIC_SYSREG_READ_ENABLED 1 #define TRACE_NVIC_SYSREG_WRITE_ENABLED 1 #define TRACE_HEATHROW_WRITE_ENABLED 1 #define TRACE_HEATHROW_READ_ENABLED 1 #define TRACE_HEATHROW_SET_IRQ_ENABLED 1 #define TRACE_BCM2835_IC_SET_GPU_IRQ_ENABLED 1 #define TRACE_BCM2835_IC_SET_CPU_IRQ_ENABLED 1 #define TRACE_SPAPR_XIVE_CLAIM_IRQ_ENABLED 1 #define TRACE_SPAPR_XIVE_FREE_IRQ_ENABLED 1 #define TRACE_SPAPR_XIVE_SET_IRQ_ENABLED 1 #define TRACE_SPAPR_XIVE_GET_SOURCE_INFO_ENABLED 1 #define TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_ENABLED 1 #define TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_ENABLED 1 #define TRACE_SPAPR_XIVE_GET_QUEUE_INFO_ENABLED 1 #define TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_ENABLED 1 #define TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_ENABLED 1 #define TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_ENABLED 1 #define TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_ENABLED 1 #define TRACE_SPAPR_XIVE_ESB_ENABLED 1 #define TRACE_SPAPR_XIVE_SYNC_ENABLED 1 #define TRACE_SPAPR_XIVE_RESET_ENABLED 1 #define TRACE_KVM_XIVE_CPU_CONNECT_ENABLED 1 #define TRACE_KVM_XIVE_SOURCE_RESET_ENABLED 1 #define TRACE_XIVE_TCTX_ACCEPT_ENABLED 1 #define TRACE_XIVE_TCTX_NOTIFY_ENABLED 1 #define TRACE_XIVE_TCTX_SET_CPPR_ENABLED 1 #define TRACE_XIVE_SOURCE_ESB_READ_ENABLED 1 #define TRACE_XIVE_SOURCE_ESB_WRITE_ENABLED 1 #define TRACE_XIVE_ROUTER_END_NOTIFY_ENABLED 1 #define TRACE_XIVE_ROUTER_END_ESCALATE_ENABLED 1 #define TRACE_XIVE_TCTX_TM_WRITE_ENABLED 1 #define TRACE_XIVE_TCTX_TM_READ_ENABLED 1 #define TRACE_XIVE_PRESENTER_NOTIFY_ENABLED 1 #define TRACE_XIVE_END_SOURCE_READ_ENABLED 1 #define TRACE_PNV_XIVE_IC_HW_TRIGGER_ENABLED 1 #define TRACE_GOLDFISH_IRQ_REQUEST_ENABLED 1 #define TRACE_GOLDFISH_PIC_READ_ENABLED 1 #define TRACE_GOLDFISH_PIC_WRITE_ENABLED 1 #define TRACE_GOLDFISH_PIC_RESET_ENABLED 1 #define TRACE_GOLDFISH_PIC_REALIZE_ENABLED 1 #define TRACE_GOLDFISH_PIC_INSTANCE_INIT_ENABLED 1 #define TRACE_SH_INTC_SOURCES_ENABLED 1 #define TRACE_SH_INTC_PENDING_ENABLED 1 #define TRACE_SH_INTC_REGISTER_ENABLED 1 #define TRACE_SH_INTC_READ_ENABLED 1 #define TRACE_SH_INTC_WRITE_ENABLED 1 #define TRACE_SH_INTC_SET_ENABLED 1 #define TRACE_LOONGSON_IPI_READ_ENABLED 1 #define TRACE_LOONGSON_IPI_WRITE_ENABLED 1 #define TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER_ENABLED 1 #define TRACE_LOONGARCH_PCH_PIC_LOW_READW_ENABLED 1 #define TRACE_LOONGARCH_PCH_PIC_LOW_WRITEW_ENABLED 1 #define TRACE_LOONGARCH_PCH_PIC_HIGH_READW_ENABLED 1 #define TRACE_LOONGARCH_PCH_PIC_HIGH_WRITEW_ENABLED 1 #define TRACE_LOONGARCH_PCH_PIC_READB_ENABLED 1 #define TRACE_LOONGARCH_PCH_PIC_WRITEB_ENABLED 1 #define TRACE_LOONGARCH_MSI_SET_IRQ_ENABLED 1 #define TRACE_LOONGARCH_EXTIOI_SETIRQ_ENABLED 1 #define TRACE_LOONGARCH_EXTIOI_READW_ENABLED 1 #define TRACE_LOONGARCH_EXTIOI_WRITEW_ENABLED 1 #include "qemu/log-for-trace.h" #include "qemu/error-report.h" #define TRACE_PIC_UPDATE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_PIC_UPDATE_IRQ) || \ false) static inline void _nocheck__trace_pic_update_irq(bool master, uint8_t imr, uint8_t irr, uint8_t padd) { if (trace_event_get_state(TRACE_PIC_UPDATE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 4 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:pic_update_irq " "master %d imr %"PRIu8" irr %"PRIu8" padd %"PRIu8 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , master, imr, irr, padd); #line 826 "trace/trace-hw_intc.h" } else { #line 4 "../hw/intc/trace-events" qemu_log("pic_update_irq " "master %d imr %"PRIu8" irr %"PRIu8" padd %"PRIu8 "\n", master, imr, irr, padd); #line 830 "trace/trace-hw_intc.h" } } } static inline void trace_pic_update_irq(bool master, uint8_t imr, uint8_t irr, uint8_t padd) { if (true) { _nocheck__trace_pic_update_irq(master, imr, irr, padd); } } #define TRACE_PIC_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_PIC_SET_IRQ) || \ false) static inline void _nocheck__trace_pic_set_irq(bool master, int irq, int level) { if (trace_event_get_state(TRACE_PIC_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 5 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:pic_set_irq " "master %d irq %d level %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , master, irq, level); #line 857 "trace/trace-hw_intc.h" } else { #line 5 "../hw/intc/trace-events" qemu_log("pic_set_irq " "master %d irq %d level %d" "\n", master, irq, level); #line 861 "trace/trace-hw_intc.h" } } } static inline void trace_pic_set_irq(bool master, int irq, int level) { if (true) { _nocheck__trace_pic_set_irq(master, irq, level); } } #define TRACE_PIC_INTERRUPT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_PIC_INTERRUPT) || \ false) static inline void _nocheck__trace_pic_interrupt(int irq, int intno) { if (trace_event_get_state(TRACE_PIC_INTERRUPT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 6 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:pic_interrupt " "irq %d intno %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, intno); #line 888 "trace/trace-hw_intc.h" } else { #line 6 "../hw/intc/trace-events" qemu_log("pic_interrupt " "irq %d intno %d" "\n", irq, intno); #line 892 "trace/trace-hw_intc.h" } } } static inline void trace_pic_interrupt(int irq, int intno) { if (true) { _nocheck__trace_pic_interrupt(irq, intno); } } #define TRACE_PIC_IOPORT_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_PIC_IOPORT_WRITE) || \ false) static inline void _nocheck__trace_pic_ioport_write(bool master, uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_PIC_IOPORT_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 7 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:pic_ioport_write " "master %d addr 0x%"PRIx64" val 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , master, addr, val); #line 919 "trace/trace-hw_intc.h" } else { #line 7 "../hw/intc/trace-events" qemu_log("pic_ioport_write " "master %d addr 0x%"PRIx64" val 0x%"PRIx64 "\n", master, addr, val); #line 923 "trace/trace-hw_intc.h" } } } static inline void trace_pic_ioport_write(bool master, uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_pic_ioport_write(master, addr, val); } } #define TRACE_PIC_IOPORT_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_PIC_IOPORT_READ) || \ false) static inline void _nocheck__trace_pic_ioport_read(bool master, uint64_t addr, int val) { if (trace_event_get_state(TRACE_PIC_IOPORT_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 8 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:pic_ioport_read " "master %d addr 0x%"PRIx64" val 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , master, addr, val); #line 950 "trace/trace-hw_intc.h" } else { #line 8 "../hw/intc/trace-events" qemu_log("pic_ioport_read " "master %d addr 0x%"PRIx64" val 0x%x" "\n", master, addr, val); #line 954 "trace/trace-hw_intc.h" } } } static inline void trace_pic_ioport_read(bool master, uint64_t addr, int val) { if (true) { _nocheck__trace_pic_ioport_read(master, addr, val); } } #define TRACE_CPU_SET_APIC_BASE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_CPU_SET_APIC_BASE) || \ false) static inline void _nocheck__trace_cpu_set_apic_base(uint64_t val) { if (trace_event_get_state(TRACE_CPU_SET_APIC_BASE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 11 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:cpu_set_apic_base " "0x%016"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 981 "trace/trace-hw_intc.h" } else { #line 11 "../hw/intc/trace-events" qemu_log("cpu_set_apic_base " "0x%016"PRIx64 "\n", val); #line 985 "trace/trace-hw_intc.h" } } } static inline void trace_cpu_set_apic_base(uint64_t val) { if (true) { _nocheck__trace_cpu_set_apic_base(val); } } #define TRACE_CPU_GET_APIC_BASE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_CPU_GET_APIC_BASE) || \ false) static inline void _nocheck__trace_cpu_get_apic_base(uint64_t val) { if (trace_event_get_state(TRACE_CPU_GET_APIC_BASE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 12 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:cpu_get_apic_base " "0x%016"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 1012 "trace/trace-hw_intc.h" } else { #line 12 "../hw/intc/trace-events" qemu_log("cpu_get_apic_base " "0x%016"PRIx64 "\n", val); #line 1016 "trace/trace-hw_intc.h" } } } static inline void trace_cpu_get_apic_base(uint64_t val) { if (true) { _nocheck__trace_cpu_get_apic_base(val); } } #define TRACE_APIC_LOCAL_DELIVER_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_APIC_LOCAL_DELIVER) || \ false) static inline void _nocheck__trace_apic_local_deliver(int vector, uint32_t lvt) { if (trace_event_get_state(TRACE_APIC_LOCAL_DELIVER) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 15 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:apic_local_deliver " "vector %d delivery mode %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vector, lvt); #line 1043 "trace/trace-hw_intc.h" } else { #line 15 "../hw/intc/trace-events" qemu_log("apic_local_deliver " "vector %d delivery mode %d" "\n", vector, lvt); #line 1047 "trace/trace-hw_intc.h" } } } static inline void trace_apic_local_deliver(int vector, uint32_t lvt) { if (true) { _nocheck__trace_apic_local_deliver(vector, lvt); } } #define TRACE_APIC_DELIVER_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_APIC_DELIVER_IRQ) || \ false) static inline void _nocheck__trace_apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode) { if (trace_event_get_state(TRACE_APIC_DELIVER_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 16 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:apic_deliver_irq " "dest %d dest_mode %d delivery_mode %d vector %d trigger_mode %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dest, dest_mode, delivery_mode, vector_num, trigger_mode); #line 1074 "trace/trace-hw_intc.h" } else { #line 16 "../hw/intc/trace-events" qemu_log("apic_deliver_irq " "dest %d dest_mode %d delivery_mode %d vector %d trigger_mode %d" "\n", dest, dest_mode, delivery_mode, vector_num, trigger_mode); #line 1078 "trace/trace-hw_intc.h" } } } static inline void trace_apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode) { if (true) { _nocheck__trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, trigger_mode); } } #define TRACE_APIC_REGISTER_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_APIC_REGISTER_READ) || \ false) static inline void _nocheck__trace_apic_register_read(uint8_t reg, uint64_t val) { if (trace_event_get_state(TRACE_APIC_REGISTER_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 17 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:apic_register_read " "register 0x%02x = 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, val); #line 1105 "trace/trace-hw_intc.h" } else { #line 17 "../hw/intc/trace-events" qemu_log("apic_register_read " "register 0x%02x = 0x%"PRIx64 "\n", reg, val); #line 1109 "trace/trace-hw_intc.h" } } } static inline void trace_apic_register_read(uint8_t reg, uint64_t val) { if (true) { _nocheck__trace_apic_register_read(reg, val); } } #define TRACE_APIC_REGISTER_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_APIC_REGISTER_WRITE) || \ false) static inline void _nocheck__trace_apic_register_write(uint8_t reg, uint64_t val) { if (trace_event_get_state(TRACE_APIC_REGISTER_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 18 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:apic_register_write " "register 0x%02x = 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, val); #line 1136 "trace/trace-hw_intc.h" } else { #line 18 "../hw/intc/trace-events" qemu_log("apic_register_write " "register 0x%02x = 0x%"PRIx64 "\n", reg, val); #line 1140 "trace/trace-hw_intc.h" } } } static inline void trace_apic_register_write(uint8_t reg, uint64_t val) { if (true) { _nocheck__trace_apic_register_write(reg, val); } } #define TRACE_IOAPIC_SET_REMOTE_IRR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_SET_REMOTE_IRR) || \ false) static inline void _nocheck__trace_ioapic_set_remote_irr(int n) { if (trace_event_get_state(TRACE_IOAPIC_SET_REMOTE_IRR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 21 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:ioapic_set_remote_irr " "set remote irr for pin %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , n); #line 1167 "trace/trace-hw_intc.h" } else { #line 21 "../hw/intc/trace-events" qemu_log("ioapic_set_remote_irr " "set remote irr for pin %d" "\n", n); #line 1171 "trace/trace-hw_intc.h" } } } static inline void trace_ioapic_set_remote_irr(int n) { if (true) { _nocheck__trace_ioapic_set_remote_irr(n); } } #define TRACE_IOAPIC_CLEAR_REMOTE_IRR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_CLEAR_REMOTE_IRR) || \ false) static inline void _nocheck__trace_ioapic_clear_remote_irr(int n, int vector) { if (trace_event_get_state(TRACE_IOAPIC_CLEAR_REMOTE_IRR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 22 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:ioapic_clear_remote_irr " "clear remote irr for pin %d vector %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , n, vector); #line 1198 "trace/trace-hw_intc.h" } else { #line 22 "../hw/intc/trace-events" qemu_log("ioapic_clear_remote_irr " "clear remote irr for pin %d vector %d" "\n", n, vector); #line 1202 "trace/trace-hw_intc.h" } } } static inline void trace_ioapic_clear_remote_irr(int n, int vector) { if (true) { _nocheck__trace_ioapic_clear_remote_irr(n, vector); } } #define TRACE_IOAPIC_EOI_BROADCAST_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_EOI_BROADCAST) || \ false) static inline void _nocheck__trace_ioapic_eoi_broadcast(int vector) { if (trace_event_get_state(TRACE_IOAPIC_EOI_BROADCAST) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 23 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:ioapic_eoi_broadcast " "EOI broadcast for vector %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vector); #line 1229 "trace/trace-hw_intc.h" } else { #line 23 "../hw/intc/trace-events" qemu_log("ioapic_eoi_broadcast " "EOI broadcast for vector %d" "\n", vector); #line 1233 "trace/trace-hw_intc.h" } } } static inline void trace_ioapic_eoi_broadcast(int vector) { if (true) { _nocheck__trace_ioapic_eoi_broadcast(vector); } } #define TRACE_IOAPIC_EOI_DELAYED_REASSERT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_EOI_DELAYED_REASSERT) || \ false) static inline void _nocheck__trace_ioapic_eoi_delayed_reassert(int vector) { if (trace_event_get_state(TRACE_IOAPIC_EOI_DELAYED_REASSERT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 24 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:ioapic_eoi_delayed_reassert " "delayed reassert on EOI broadcast for vector %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vector); #line 1260 "trace/trace-hw_intc.h" } else { #line 24 "../hw/intc/trace-events" qemu_log("ioapic_eoi_delayed_reassert " "delayed reassert on EOI broadcast for vector %d" "\n", vector); #line 1264 "trace/trace-hw_intc.h" } } } static inline void trace_ioapic_eoi_delayed_reassert(int vector) { if (true) { _nocheck__trace_ioapic_eoi_delayed_reassert(vector); } } #define TRACE_IOAPIC_MEM_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_MEM_READ) || \ false) static inline void _nocheck__trace_ioapic_mem_read(uint8_t addr, uint8_t regsel, uint8_t size, uint32_t val) { if (trace_event_get_state(TRACE_IOAPIC_MEM_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 25 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:ioapic_mem_read " "ioapic mem read addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" retval 0x%"PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, regsel, size, val); #line 1291 "trace/trace-hw_intc.h" } else { #line 25 "../hw/intc/trace-events" qemu_log("ioapic_mem_read " "ioapic mem read addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" retval 0x%"PRIx32 "\n", addr, regsel, size, val); #line 1295 "trace/trace-hw_intc.h" } } } static inline void trace_ioapic_mem_read(uint8_t addr, uint8_t regsel, uint8_t size, uint32_t val) { if (true) { _nocheck__trace_ioapic_mem_read(addr, regsel, size, val); } } #define TRACE_IOAPIC_MEM_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_MEM_WRITE) || \ false) static inline void _nocheck__trace_ioapic_mem_write(uint8_t addr, uint8_t regsel, uint8_t size, uint32_t val) { if (trace_event_get_state(TRACE_IOAPIC_MEM_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 26 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:ioapic_mem_write " "ioapic mem write addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" val 0x%"PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, regsel, size, val); #line 1322 "trace/trace-hw_intc.h" } else { #line 26 "../hw/intc/trace-events" qemu_log("ioapic_mem_write " "ioapic mem write addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" val 0x%"PRIx32 "\n", addr, regsel, size, val); #line 1326 "trace/trace-hw_intc.h" } } } static inline void trace_ioapic_mem_write(uint8_t addr, uint8_t regsel, uint8_t size, uint32_t val) { if (true) { _nocheck__trace_ioapic_mem_write(addr, regsel, size, val); } } #define TRACE_IOAPIC_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOAPIC_SET_IRQ) || \ false) static inline void _nocheck__trace_ioapic_set_irq(int vector, int level) { if (trace_event_get_state(TRACE_IOAPIC_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 27 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:ioapic_set_irq " "vector: %d level: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vector, level); #line 1353 "trace/trace-hw_intc.h" } else { #line 27 "../hw/intc/trace-events" qemu_log("ioapic_set_irq " "vector: %d level: %d" "\n", vector, level); #line 1357 "trace/trace-hw_intc.h" } } } static inline void trace_ioapic_set_irq(int vector, int level) { if (true) { _nocheck__trace_ioapic_set_irq(vector, level); } } #define TRACE_KVM_REPORT_IRQ_DELIVERED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_KVM_REPORT_IRQ_DELIVERED) || \ false) static inline void _nocheck__trace_kvm_report_irq_delivered(int irq_delivered) { if (trace_event_get_state(TRACE_KVM_REPORT_IRQ_DELIVERED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 30 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:kvm_report_irq_delivered " "coalescing %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq_delivered); #line 1384 "trace/trace-hw_intc.h" } else { #line 30 "../hw/intc/trace-events" qemu_log("kvm_report_irq_delivered " "coalescing %d" "\n", irq_delivered); #line 1388 "trace/trace-hw_intc.h" } } } static inline void trace_kvm_report_irq_delivered(int irq_delivered) { if (true) { _nocheck__trace_kvm_report_irq_delivered(irq_delivered); } } #define TRACE_KVM_RESET_IRQ_DELIVERED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_KVM_RESET_IRQ_DELIVERED) || \ false) static inline void _nocheck__trace_kvm_reset_irq_delivered(int irq_delivered) { if (trace_event_get_state(TRACE_KVM_RESET_IRQ_DELIVERED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 31 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:kvm_reset_irq_delivered " "old coalescing %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq_delivered); #line 1415 "trace/trace-hw_intc.h" } else { #line 31 "../hw/intc/trace-events" qemu_log("kvm_reset_irq_delivered " "old coalescing %d" "\n", irq_delivered); #line 1419 "trace/trace-hw_intc.h" } } } static inline void trace_kvm_reset_irq_delivered(int irq_delivered) { if (true) { _nocheck__trace_kvm_reset_irq_delivered(irq_delivered); } } #define TRACE_KVM_GET_IRQ_DELIVERED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_KVM_GET_IRQ_DELIVERED) || \ false) static inline void _nocheck__trace_kvm_get_irq_delivered(int irq_delivered) { if (trace_event_get_state(TRACE_KVM_GET_IRQ_DELIVERED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 32 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:kvm_get_irq_delivered " "returning coalescing %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq_delivered); #line 1446 "trace/trace-hw_intc.h" } else { #line 32 "../hw/intc/trace-events" qemu_log("kvm_get_irq_delivered " "returning coalescing %d" "\n", irq_delivered); #line 1450 "trace/trace-hw_intc.h" } } } static inline void trace_kvm_get_irq_delivered(int irq_delivered) { if (true) { _nocheck__trace_kvm_get_irq_delivered(irq_delivered); } } #define TRACE_SLAVIO_INTCTL_MEM_READL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTL_MEM_READL) || \ false) static inline void _nocheck__trace_slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) { if (trace_event_get_state(TRACE_SLAVIO_INTCTL_MEM_READL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 35 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_intctl_mem_readl " "read cpu %d reg 0x%"PRIx64" = 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, addr, ret); #line 1477 "trace/trace-hw_intc.h" } else { #line 35 "../hw/intc/trace-events" qemu_log("slavio_intctl_mem_readl " "read cpu %d reg 0x%"PRIx64" = 0x%x" "\n", cpu, addr, ret); #line 1481 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) { if (true) { _nocheck__trace_slavio_intctl_mem_readl(cpu, addr, ret); } } #define TRACE_SLAVIO_INTCTL_MEM_WRITEL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTL_MEM_WRITEL) || \ false) static inline void _nocheck__trace_slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) { if (trace_event_get_state(TRACE_SLAVIO_INTCTL_MEM_WRITEL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 36 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_intctl_mem_writel " "write cpu %d reg 0x%"PRIx64" = 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, addr, val); #line 1508 "trace/trace-hw_intc.h" } else { #line 36 "../hw/intc/trace-events" qemu_log("slavio_intctl_mem_writel " "write cpu %d reg 0x%"PRIx64" = 0x%x" "\n", cpu, addr, val); #line 1512 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) { if (true) { _nocheck__trace_slavio_intctl_mem_writel(cpu, addr, val); } } #define TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR) || \ false) static inline void _nocheck__trace_slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) { if (trace_event_get_state(TRACE_SLAVIO_INTCTL_MEM_WRITEL_CLEAR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 37 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_intctl_mem_writel_clear " "Cleared cpu %d irq mask 0x%x, curmask 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val, intreg_pending); #line 1539 "trace/trace-hw_intc.h" } else { #line 37 "../hw/intc/trace-events" qemu_log("slavio_intctl_mem_writel_clear " "Cleared cpu %d irq mask 0x%x, curmask 0x%x" "\n", cpu, val, intreg_pending); #line 1543 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) { if (true) { _nocheck__trace_slavio_intctl_mem_writel_clear(cpu, val, intreg_pending); } } #define TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET) || \ false) static inline void _nocheck__trace_slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) { if (trace_event_get_state(TRACE_SLAVIO_INTCTL_MEM_WRITEL_SET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 38 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_intctl_mem_writel_set " "Set cpu %d irq mask 0x%x, curmask 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val, intreg_pending); #line 1570 "trace/trace-hw_intc.h" } else { #line 38 "../hw/intc/trace-events" qemu_log("slavio_intctl_mem_writel_set " "Set cpu %d irq mask 0x%x, curmask 0x%x" "\n", cpu, val, intreg_pending); #line 1574 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) { if (true) { _nocheck__trace_slavio_intctl_mem_writel_set(cpu, val, intreg_pending); } } #define TRACE_SLAVIO_INTCTLM_MEM_READL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTLM_MEM_READL) || \ false) static inline void _nocheck__trace_slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) { if (trace_event_get_state(TRACE_SLAVIO_INTCTLM_MEM_READL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 39 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_intctlm_mem_readl " "read system reg 0x%"PRIx64" = 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, ret); #line 1601 "trace/trace-hw_intc.h" } else { #line 39 "../hw/intc/trace-events" qemu_log("slavio_intctlm_mem_readl " "read system reg 0x%"PRIx64" = 0x%x" "\n", addr, ret); #line 1605 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) { if (true) { _nocheck__trace_slavio_intctlm_mem_readl(addr, ret); } } #define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTLM_MEM_WRITEL) || \ false) static inline void _nocheck__trace_slavio_intctlm_mem_writel(uint64_t addr, uint32_t val) { if (trace_event_get_state(TRACE_SLAVIO_INTCTLM_MEM_WRITEL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 40 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_intctlm_mem_writel " "write system reg 0x%"PRIx64" = 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 1632 "trace/trace-hw_intc.h" } else { #line 40 "../hw/intc/trace-events" qemu_log("slavio_intctlm_mem_writel " "write system reg 0x%"PRIx64" = 0x%x" "\n", addr, val); #line 1636 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_intctlm_mem_writel(uint64_t addr, uint32_t val) { if (true) { _nocheck__trace_slavio_intctlm_mem_writel(addr, val); } } #define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE) || \ false) static inline void _nocheck__trace_slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) { if (trace_event_get_state(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 41 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_intctlm_mem_writel_enable " "Enabled master irq mask 0x%x, curmask 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val, intregm_disabled); #line 1663 "trace/trace-hw_intc.h" } else { #line 41 "../hw/intc/trace-events" qemu_log("slavio_intctlm_mem_writel_enable " "Enabled master irq mask 0x%x, curmask 0x%x" "\n", val, intregm_disabled); #line 1667 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) { if (true) { _nocheck__trace_slavio_intctlm_mem_writel_enable(val, intregm_disabled); } } #define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE) || \ false) static inline void _nocheck__trace_slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) { if (trace_event_get_state(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_DISABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 42 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_intctlm_mem_writel_disable " "Disabled master irq mask 0x%x, curmask 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val, intregm_disabled); #line 1694 "trace/trace-hw_intc.h" } else { #line 42 "../hw/intc/trace-events" qemu_log("slavio_intctlm_mem_writel_disable " "Disabled master irq mask 0x%x, curmask 0x%x" "\n", val, intregm_disabled); #line 1698 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) { if (true) { _nocheck__trace_slavio_intctlm_mem_writel_disable(val, intregm_disabled); } } #define TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET) || \ false) static inline void _nocheck__trace_slavio_intctlm_mem_writel_target(uint32_t cpu) { if (trace_event_get_state(TRACE_SLAVIO_INTCTLM_MEM_WRITEL_TARGET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 43 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_intctlm_mem_writel_target " "Set master irq cpu %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu); #line 1725 "trace/trace-hw_intc.h" } else { #line 43 "../hw/intc/trace-events" qemu_log("slavio_intctlm_mem_writel_target " "Set master irq cpu %d" "\n", cpu); #line 1729 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_intctlm_mem_writel_target(uint32_t cpu) { if (true) { _nocheck__trace_slavio_intctlm_mem_writel_target(cpu); } } #define TRACE_SLAVIO_CHECK_INTERRUPTS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_CHECK_INTERRUPTS) || \ false) static inline void _nocheck__trace_slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) { if (trace_event_get_state(TRACE_SLAVIO_CHECK_INTERRUPTS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 44 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_check_interrupts " "pending 0x%x disabled 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , pending, intregm_disabled); #line 1756 "trace/trace-hw_intc.h" } else { #line 44 "../hw/intc/trace-events" qemu_log("slavio_check_interrupts " "pending 0x%x disabled 0x%x" "\n", pending, intregm_disabled); #line 1760 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) { if (true) { _nocheck__trace_slavio_check_interrupts(pending, intregm_disabled); } } #define TRACE_SLAVIO_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_SET_IRQ) || \ false) static inline void _nocheck__trace_slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) { if (trace_event_get_state(TRACE_SLAVIO_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 45 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_set_irq " "Set cpu %d irq %d -> pil %d level %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , target_cpu, irq, pil, level); #line 1787 "trace/trace-hw_intc.h" } else { #line 45 "../hw/intc/trace-events" qemu_log("slavio_set_irq " "Set cpu %d irq %d -> pil %d level %d" "\n", target_cpu, irq, pil, level); #line 1791 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) { if (true) { _nocheck__trace_slavio_set_irq(target_cpu, irq, pil, level); } } #define TRACE_SLAVIO_SET_TIMER_IRQ_CPU_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_SET_TIMER_IRQ_CPU) || \ false) static inline void _nocheck__trace_slavio_set_timer_irq_cpu(int cpu, int level) { if (trace_event_get_state(TRACE_SLAVIO_SET_TIMER_IRQ_CPU) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 46 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:slavio_set_timer_irq_cpu " "Set cpu %d local timer level %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, level); #line 1818 "trace/trace-hw_intc.h" } else { #line 46 "../hw/intc/trace-events" qemu_log("slavio_set_timer_irq_cpu " "Set cpu %d local timer level %d" "\n", cpu, level); #line 1822 "trace/trace-hw_intc.h" } } } static inline void trace_slavio_set_timer_irq_cpu(int cpu, int level) { if (true) { _nocheck__trace_slavio_set_timer_irq_cpu(cpu, level); } } #define TRACE_GRLIB_IRQMP_CHECK_IRQS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GRLIB_IRQMP_CHECK_IRQS) || \ false) static inline void _nocheck__trace_grlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2) { if (trace_event_get_state(TRACE_GRLIB_IRQMP_CHECK_IRQS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 49 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:grlib_irqmp_check_irqs " "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , pend, force, mask, lvl1, lvl2); #line 1849 "trace/trace-hw_intc.h" } else { #line 49 "../hw/intc/trace-events" qemu_log("grlib_irqmp_check_irqs " "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x" "\n", pend, force, mask, lvl1, lvl2); #line 1853 "trace/trace-hw_intc.h" } } } static inline void trace_grlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2) { if (true) { _nocheck__trace_grlib_irqmp_check_irqs(pend, force, mask, lvl1, lvl2); } } #define TRACE_GRLIB_IRQMP_ACK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GRLIB_IRQMP_ACK) || \ false) static inline void _nocheck__trace_grlib_irqmp_ack(int intno) { if (trace_event_get_state(TRACE_GRLIB_IRQMP_ACK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 50 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:grlib_irqmp_ack " "interrupt:%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , intno); #line 1880 "trace/trace-hw_intc.h" } else { #line 50 "../hw/intc/trace-events" qemu_log("grlib_irqmp_ack " "interrupt:%d" "\n", intno); #line 1884 "trace/trace-hw_intc.h" } } } static inline void trace_grlib_irqmp_ack(int intno) { if (true) { _nocheck__trace_grlib_irqmp_ack(intno); } } #define TRACE_GRLIB_IRQMP_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GRLIB_IRQMP_SET_IRQ) || \ false) static inline void _nocheck__trace_grlib_irqmp_set_irq(int irq) { if (trace_event_get_state(TRACE_GRLIB_IRQMP_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 51 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:grlib_irqmp_set_irq " "Raise CPU IRQ %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq); #line 1911 "trace/trace-hw_intc.h" } else { #line 51 "../hw/intc/trace-events" qemu_log("grlib_irqmp_set_irq " "Raise CPU IRQ %d" "\n", irq); #line 1915 "trace/trace-hw_intc.h" } } } static inline void trace_grlib_irqmp_set_irq(int irq) { if (true) { _nocheck__trace_grlib_irqmp_set_irq(irq); } } #define TRACE_GRLIB_IRQMP_READL_UNKNOWN_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GRLIB_IRQMP_READL_UNKNOWN) || \ false) static inline void _nocheck__trace_grlib_irqmp_readl_unknown(uint64_t addr) { if (trace_event_get_state(TRACE_GRLIB_IRQMP_READL_UNKNOWN) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 52 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:grlib_irqmp_readl_unknown " "addr 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr); #line 1942 "trace/trace-hw_intc.h" } else { #line 52 "../hw/intc/trace-events" qemu_log("grlib_irqmp_readl_unknown " "addr 0x%"PRIx64 "\n", addr); #line 1946 "trace/trace-hw_intc.h" } } } static inline void trace_grlib_irqmp_readl_unknown(uint64_t addr) { if (true) { _nocheck__trace_grlib_irqmp_readl_unknown(addr); } } #define TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN) || \ false) static inline void _nocheck__trace_grlib_irqmp_writel_unknown(uint64_t addr, uint32_t value) { if (trace_event_get_state(TRACE_GRLIB_IRQMP_WRITEL_UNKNOWN) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 53 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:grlib_irqmp_writel_unknown " "addr 0x%"PRIx64" value 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, value); #line 1973 "trace/trace-hw_intc.h" } else { #line 53 "../hw/intc/trace-events" qemu_log("grlib_irqmp_writel_unknown " "addr 0x%"PRIx64" value 0x%x" "\n", addr, value); #line 1977 "trace/trace-hw_intc.h" } } } static inline void trace_grlib_irqmp_writel_unknown(uint64_t addr, uint32_t value) { if (true) { _nocheck__trace_grlib_irqmp_writel_unknown(addr, value); } } #define TRACE_XICS_ICP_CHECK_IPI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XICS_ICP_CHECK_IPI) || \ false) static inline void _nocheck__trace_xics_icp_check_ipi(int server, uint8_t mfrr) { if (trace_event_get_state(TRACE_XICS_ICP_CHECK_IPI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 56 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xics_icp_check_ipi " "CPU %d can take IPI mfrr=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , server, mfrr); #line 2004 "trace/trace-hw_intc.h" } else { #line 56 "../hw/intc/trace-events" qemu_log("xics_icp_check_ipi " "CPU %d can take IPI mfrr=0x%x" "\n", server, mfrr); #line 2008 "trace/trace-hw_intc.h" } } } static inline void trace_xics_icp_check_ipi(int server, uint8_t mfrr) { if (true) { _nocheck__trace_xics_icp_check_ipi(server, mfrr); } } #define TRACE_XICS_ICP_ACCEPT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XICS_ICP_ACCEPT) || \ false) static inline void _nocheck__trace_xics_icp_accept(uint32_t old_xirr, uint32_t new_xirr) { if (trace_event_get_state(TRACE_XICS_ICP_ACCEPT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 57 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xics_icp_accept " "icp_accept: XIRR 0x%"PRIx32"->0x%"PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , old_xirr, new_xirr); #line 2035 "trace/trace-hw_intc.h" } else { #line 57 "../hw/intc/trace-events" qemu_log("xics_icp_accept " "icp_accept: XIRR 0x%"PRIx32"->0x%"PRIx32 "\n", old_xirr, new_xirr); #line 2039 "trace/trace-hw_intc.h" } } } static inline void trace_xics_icp_accept(uint32_t old_xirr, uint32_t new_xirr) { if (true) { _nocheck__trace_xics_icp_accept(old_xirr, new_xirr); } } #define TRACE_XICS_ICP_EOI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XICS_ICP_EOI) || \ false) static inline void _nocheck__trace_xics_icp_eoi(int server, uint32_t xirr, uint32_t new_xirr) { if (trace_event_get_state(TRACE_XICS_ICP_EOI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 58 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xics_icp_eoi " "icp_eoi: server %d given XIRR 0x%"PRIx32" new XIRR 0x%"PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , server, xirr, new_xirr); #line 2066 "trace/trace-hw_intc.h" } else { #line 58 "../hw/intc/trace-events" qemu_log("xics_icp_eoi " "icp_eoi: server %d given XIRR 0x%"PRIx32" new XIRR 0x%"PRIx32 "\n", server, xirr, new_xirr); #line 2070 "trace/trace-hw_intc.h" } } } static inline void trace_xics_icp_eoi(int server, uint32_t xirr, uint32_t new_xirr) { if (true) { _nocheck__trace_xics_icp_eoi(server, xirr, new_xirr); } } #define TRACE_XICS_ICP_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XICS_ICP_IRQ) || \ false) static inline void _nocheck__trace_xics_icp_irq(int server, int nr, uint8_t priority) { if (trace_event_get_state(TRACE_XICS_ICP_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 59 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xics_icp_irq " "cpu %d trying to deliver irq 0x%"PRIx32" priority 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , server, nr, priority); #line 2097 "trace/trace-hw_intc.h" } else { #line 59 "../hw/intc/trace-events" qemu_log("xics_icp_irq " "cpu %d trying to deliver irq 0x%"PRIx32" priority 0x%x" "\n", server, nr, priority); #line 2101 "trace/trace-hw_intc.h" } } } static inline void trace_xics_icp_irq(int server, int nr, uint8_t priority) { if (true) { _nocheck__trace_xics_icp_irq(server, nr, priority); } } #define TRACE_XICS_ICP_RAISE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XICS_ICP_RAISE) || \ false) static inline void _nocheck__trace_xics_icp_raise(uint32_t xirr, uint8_t pending_priority) { if (trace_event_get_state(TRACE_XICS_ICP_RAISE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 60 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xics_icp_raise " "raising IRQ new XIRR=0x%x new pending priority=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , xirr, pending_priority); #line 2128 "trace/trace-hw_intc.h" } else { #line 60 "../hw/intc/trace-events" qemu_log("xics_icp_raise " "raising IRQ new XIRR=0x%x new pending priority=0x%x" "\n", xirr, pending_priority); #line 2132 "trace/trace-hw_intc.h" } } } static inline void trace_xics_icp_raise(uint32_t xirr, uint8_t pending_priority) { if (true) { _nocheck__trace_xics_icp_raise(xirr, pending_priority); } } #define TRACE_XICS_ICS_SET_IRQ_MSI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XICS_ICS_SET_IRQ_MSI) || \ false) static inline void _nocheck__trace_xics_ics_set_irq_msi(int srcno, int nr) { if (trace_event_get_state(TRACE_XICS_ICS_SET_IRQ_MSI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 61 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xics_ics_set_irq_msi " "set_irq_msi: srcno %d [irq 0x%x]" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , srcno, nr); #line 2159 "trace/trace-hw_intc.h" } else { #line 61 "../hw/intc/trace-events" qemu_log("xics_ics_set_irq_msi " "set_irq_msi: srcno %d [irq 0x%x]" "\n", srcno, nr); #line 2163 "trace/trace-hw_intc.h" } } } static inline void trace_xics_ics_set_irq_msi(int srcno, int nr) { if (true) { _nocheck__trace_xics_ics_set_irq_msi(srcno, nr); } } #define TRACE_XICS_MASKED_PENDING_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XICS_MASKED_PENDING) || \ false) static inline void _nocheck__trace_xics_masked_pending(void) { if (trace_event_get_state(TRACE_XICS_MASKED_PENDING) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 62 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xics_masked_pending " "set_irq_msi: masked pending" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 2190 "trace/trace-hw_intc.h" } else { #line 62 "../hw/intc/trace-events" qemu_log("xics_masked_pending " "set_irq_msi: masked pending" "\n"); #line 2194 "trace/trace-hw_intc.h" } } } static inline void trace_xics_masked_pending(void) { if (true) { _nocheck__trace_xics_masked_pending(); } } #define TRACE_XICS_ICS_SET_IRQ_LSI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XICS_ICS_SET_IRQ_LSI) || \ false) static inline void _nocheck__trace_xics_ics_set_irq_lsi(int srcno, int nr) { if (trace_event_get_state(TRACE_XICS_ICS_SET_IRQ_LSI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 63 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xics_ics_set_irq_lsi " "set_irq_lsi: srcno %d [irq 0x%x]" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , srcno, nr); #line 2221 "trace/trace-hw_intc.h" } else { #line 63 "../hw/intc/trace-events" qemu_log("xics_ics_set_irq_lsi " "set_irq_lsi: srcno %d [irq 0x%x]" "\n", srcno, nr); #line 2225 "trace/trace-hw_intc.h" } } } static inline void trace_xics_ics_set_irq_lsi(int srcno, int nr) { if (true) { _nocheck__trace_xics_ics_set_irq_lsi(srcno, nr); } } #define TRACE_XICS_ICS_WRITE_XIVE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XICS_ICS_WRITE_XIVE) || \ false) static inline void _nocheck__trace_xics_ics_write_xive(int nr, int srcno, int server, uint8_t priority) { if (trace_event_get_state(TRACE_XICS_ICS_WRITE_XIVE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 64 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xics_ics_write_xive " "ics_write_xive: irq 0x%x [src %d] server 0x%x prio 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , nr, srcno, server, priority); #line 2252 "trace/trace-hw_intc.h" } else { #line 64 "../hw/intc/trace-events" qemu_log("xics_ics_write_xive " "ics_write_xive: irq 0x%x [src %d] server 0x%x prio 0x%x" "\n", nr, srcno, server, priority); #line 2256 "trace/trace-hw_intc.h" } } } static inline void trace_xics_ics_write_xive(int nr, int srcno, int server, uint8_t priority) { if (true) { _nocheck__trace_xics_ics_write_xive(nr, srcno, server, priority); } } #define TRACE_XICS_ICS_REJECT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XICS_ICS_REJECT) || \ false) static inline void _nocheck__trace_xics_ics_reject(int nr, int srcno) { if (trace_event_get_state(TRACE_XICS_ICS_REJECT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 65 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xics_ics_reject " "reject irq 0x%x [src %d]" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , nr, srcno); #line 2283 "trace/trace-hw_intc.h" } else { #line 65 "../hw/intc/trace-events" qemu_log("xics_ics_reject " "reject irq 0x%x [src %d]" "\n", nr, srcno); #line 2287 "trace/trace-hw_intc.h" } } } static inline void trace_xics_ics_reject(int nr, int srcno) { if (true) { _nocheck__trace_xics_ics_reject(nr, srcno); } } #define TRACE_XICS_ICS_EOI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XICS_ICS_EOI) || \ false) static inline void _nocheck__trace_xics_ics_eoi(int nr) { if (trace_event_get_state(TRACE_XICS_ICS_EOI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 66 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xics_ics_eoi " "ics_eoi: irq 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , nr); #line 2314 "trace/trace-hw_intc.h" } else { #line 66 "../hw/intc/trace-events" qemu_log("xics_ics_eoi " "ics_eoi: irq 0x%x" "\n", nr); #line 2318 "trace/trace-hw_intc.h" } } } static inline void trace_xics_ics_eoi(int nr) { if (true) { _nocheck__trace_xics_ics_eoi(nr); } } #define TRACE_FLIC_CREATE_DEVICE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_FLIC_CREATE_DEVICE) || \ false) static inline void _nocheck__trace_flic_create_device(int err) { if (trace_event_get_state(TRACE_FLIC_CREATE_DEVICE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 69 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:flic_create_device " "flic: create device failed %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , err); #line 2345 "trace/trace-hw_intc.h" } else { #line 69 "../hw/intc/trace-events" qemu_log("flic_create_device " "flic: create device failed %d" "\n", err); #line 2349 "trace/trace-hw_intc.h" } } } static inline void trace_flic_create_device(int err) { if (true) { _nocheck__trace_flic_create_device(err); } } #define TRACE_FLIC_RESET_FAILED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_FLIC_RESET_FAILED) || \ false) static inline void _nocheck__trace_flic_reset_failed(int err) { if (trace_event_get_state(TRACE_FLIC_RESET_FAILED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 70 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:flic_reset_failed " "flic: reset failed %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , err); #line 2376 "trace/trace-hw_intc.h" } else { #line 70 "../hw/intc/trace-events" qemu_log("flic_reset_failed " "flic: reset failed %d" "\n", err); #line 2380 "trace/trace-hw_intc.h" } } } static inline void trace_flic_reset_failed(int err) { if (true) { _nocheck__trace_flic_reset_failed(err); } } #define TRACE_QEMU_S390_AIRQ_SUPPRESSED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QEMU_S390_AIRQ_SUPPRESSED) || \ false) static inline void _nocheck__trace_qemu_s390_airq_suppressed(uint8_t type, uint8_t isc) { if (trace_event_get_state(TRACE_QEMU_S390_AIRQ_SUPPRESSED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 73 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:qemu_s390_airq_suppressed " "flic: adapter I/O interrupt suppressed (type 0x%x isc 0x%x)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , type, isc); #line 2407 "trace/trace-hw_intc.h" } else { #line 73 "../hw/intc/trace-events" qemu_log("qemu_s390_airq_suppressed " "flic: adapter I/O interrupt suppressed (type 0x%x isc 0x%x)" "\n", type, isc); #line 2411 "trace/trace-hw_intc.h" } } } static inline void trace_qemu_s390_airq_suppressed(uint8_t type, uint8_t isc) { if (true) { _nocheck__trace_qemu_s390_airq_suppressed(type, isc); } } #define TRACE_QEMU_S390_SUPPRESS_AIRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_QEMU_S390_SUPPRESS_AIRQ) || \ false) static inline void _nocheck__trace_qemu_s390_suppress_airq(uint8_t isc, const char * from, const char * to) { if (trace_event_get_state(TRACE_QEMU_S390_SUPPRESS_AIRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 74 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:qemu_s390_suppress_airq " "flic: for isc 0x%x, suppress airq by modifying ais mode from %s to %s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , isc, from, to); #line 2438 "trace/trace-hw_intc.h" } else { #line 74 "../hw/intc/trace-events" qemu_log("qemu_s390_suppress_airq " "flic: for isc 0x%x, suppress airq by modifying ais mode from %s to %s" "\n", isc, from, to); #line 2442 "trace/trace-hw_intc.h" } } } static inline void trace_qemu_s390_suppress_airq(uint8_t isc, const char * from, const char * to) { if (true) { _nocheck__trace_qemu_s390_suppress_airq(isc, from, to); } } #define TRACE_ASPEED_VIC_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_VIC_SET_IRQ) || \ false) static inline void _nocheck__trace_aspeed_vic_set_irq(int irq, int level) { if (trace_event_get_state(TRACE_ASPEED_VIC_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 77 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_vic_set_irq " "Enabling IRQ %d: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 2469 "trace/trace-hw_intc.h" } else { #line 77 "../hw/intc/trace-events" qemu_log("aspeed_vic_set_irq " "Enabling IRQ %d: %d" "\n", irq, level); #line 2473 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_vic_set_irq(int irq, int level) { if (true) { _nocheck__trace_aspeed_vic_set_irq(irq, level); } } #define TRACE_ASPEED_VIC_UPDATE_FIQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_VIC_UPDATE_FIQ) || \ false) static inline void _nocheck__trace_aspeed_vic_update_fiq(int flags) { if (trace_event_get_state(TRACE_ASPEED_VIC_UPDATE_FIQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 78 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_vic_update_fiq " "Raising FIQ: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags); #line 2500 "trace/trace-hw_intc.h" } else { #line 78 "../hw/intc/trace-events" qemu_log("aspeed_vic_update_fiq " "Raising FIQ: %d" "\n", flags); #line 2504 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_vic_update_fiq(int flags) { if (true) { _nocheck__trace_aspeed_vic_update_fiq(flags); } } #define TRACE_ASPEED_VIC_UPDATE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_VIC_UPDATE_IRQ) || \ false) static inline void _nocheck__trace_aspeed_vic_update_irq(int flags) { if (trace_event_get_state(TRACE_ASPEED_VIC_UPDATE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 79 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_vic_update_irq " "Raising IRQ: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags); #line 2531 "trace/trace-hw_intc.h" } else { #line 79 "../hw/intc/trace-events" qemu_log("aspeed_vic_update_irq " "Raising IRQ: %d" "\n", flags); #line 2535 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_vic_update_irq(int flags) { if (true) { _nocheck__trace_aspeed_vic_update_irq(flags); } } #define TRACE_ASPEED_VIC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_VIC_READ) || \ false) static inline void _nocheck__trace_aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) { if (trace_event_get_state(TRACE_ASPEED_VIC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 80 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_vic_read " "From 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, value); #line 2562 "trace/trace-hw_intc.h" } else { #line 80 "../hw/intc/trace-events" qemu_log("aspeed_vic_read " "From 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, value); #line 2566 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) { if (true) { _nocheck__trace_aspeed_vic_read(offset, size, value); } } #define TRACE_ASPEED_VIC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_VIC_WRITE) || \ false) static inline void _nocheck__trace_aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_VIC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 81 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_vic_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 2593 "trace/trace-hw_intc.h" } else { #line 81 "../hw/intc/trace-events" qemu_log("aspeed_vic_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 2597 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) { if (true) { _nocheck__trace_aspeed_vic_write(offset, size, data); } } #define TRACE_ASPEED_INTC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_READ) || \ false) static inline void _nocheck__trace_aspeed_intc_read(uint64_t offset, unsigned size, uint32_t value) { if (trace_event_get_state(TRACE_ASPEED_INTC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 83 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_read " "From 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, value); #line 2624 "trace/trace-hw_intc.h" } else { #line 83 "../hw/intc/trace-events" qemu_log("aspeed_intc_read " "From 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, value); #line 2628 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_read(uint64_t offset, unsigned size, uint32_t value) { if (true) { _nocheck__trace_aspeed_intc_read(offset, size, value); } } #define TRACE_ASPEED_INTC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_WRITE) || \ false) static inline void _nocheck__trace_aspeed_intc_write(uint64_t offset, unsigned size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_INTC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 84 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 2655 "trace/trace-hw_intc.h" } else { #line 84 "../hw/intc/trace-events" qemu_log("aspeed_intc_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 2659 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_write(uint64_t offset, unsigned size, uint32_t data) { if (true) { _nocheck__trace_aspeed_intc_write(offset, size, data); } } #define TRACE_ASPEED_INTC_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_SET_IRQ) || \ false) static inline void _nocheck__trace_aspeed_intc_set_irq(int irq, int level) { if (trace_event_get_state(TRACE_ASPEED_INTC_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 85 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_set_irq " "Set IRQ %d: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 2686 "trace/trace-hw_intc.h" } else { #line 85 "../hw/intc/trace-events" qemu_log("aspeed_intc_set_irq " "Set IRQ %d: %d" "\n", irq, level); #line 2690 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_set_irq(int irq, int level) { if (true) { _nocheck__trace_aspeed_intc_set_irq(irq, level); } } #define TRACE_ASPEED_INTC_CLEAR_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_CLEAR_IRQ) || \ false) static inline void _nocheck__trace_aspeed_intc_clear_irq(int irq, int level) { if (trace_event_get_state(TRACE_ASPEED_INTC_CLEAR_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 86 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_clear_irq " "Clear IRQ %d: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 2717 "trace/trace-hw_intc.h" } else { #line 86 "../hw/intc/trace-events" qemu_log("aspeed_intc_clear_irq " "Clear IRQ %d: %d" "\n", irq, level); #line 2721 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_clear_irq(int irq, int level) { if (true) { _nocheck__trace_aspeed_intc_clear_irq(irq, level); } } #define TRACE_ASPEED_INTC_UPDATE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_UPDATE_IRQ) || \ false) static inline void _nocheck__trace_aspeed_intc_update_irq(int irq, int level) { if (trace_event_get_state(TRACE_ASPEED_INTC_UPDATE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 87 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_update_irq " "Update IRQ: %d: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 2748 "trace/trace-hw_intc.h" } else { #line 87 "../hw/intc/trace-events" qemu_log("aspeed_intc_update_irq " "Update IRQ: %d: %d" "\n", irq, level); #line 2752 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_update_irq(int irq, int level) { if (true) { _nocheck__trace_aspeed_intc_update_irq(irq, level); } } #define TRACE_ASPEED_INTC_PENDING_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_PENDING_IRQ) || \ false) static inline void _nocheck__trace_aspeed_intc_pending_irq(int irq, uint32_t value) { if (trace_event_get_state(TRACE_ASPEED_INTC_PENDING_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 88 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_pending_irq " "Pending IRQ: %d: 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, value); #line 2779 "trace/trace-hw_intc.h" } else { #line 88 "../hw/intc/trace-events" qemu_log("aspeed_intc_pending_irq " "Pending IRQ: %d: 0x%x" "\n", irq, value); #line 2783 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_pending_irq(int irq, uint32_t value) { if (true) { _nocheck__trace_aspeed_intc_pending_irq(irq, value); } } #define TRACE_ASPEED_INTC_TRIGGER_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_TRIGGER_IRQ) || \ false) static inline void _nocheck__trace_aspeed_intc_trigger_irq(int irq, uint32_t value) { if (trace_event_get_state(TRACE_ASPEED_INTC_TRIGGER_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 89 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_trigger_irq " "Trigger IRQ: %d: 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, value); #line 2810 "trace/trace-hw_intc.h" } else { #line 89 "../hw/intc/trace-events" qemu_log("aspeed_intc_trigger_irq " "Trigger IRQ: %d: 0x%x" "\n", irq, value); #line 2814 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_trigger_irq(int irq, uint32_t value) { if (true) { _nocheck__trace_aspeed_intc_trigger_irq(irq, value); } } #define TRACE_ASPEED_INTC_ALL_ISR_DONE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_ALL_ISR_DONE) || \ false) static inline void _nocheck__trace_aspeed_intc_all_isr_done(int irq) { if (trace_event_get_state(TRACE_ASPEED_INTC_ALL_ISR_DONE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 90 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_all_isr_done " "All source ISR execution are done: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq); #line 2841 "trace/trace-hw_intc.h" } else { #line 90 "../hw/intc/trace-events" qemu_log("aspeed_intc_all_isr_done " "All source ISR execution are done: %d" "\n", irq); #line 2845 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_all_isr_done(int irq) { if (true) { _nocheck__trace_aspeed_intc_all_isr_done(irq); } } #define TRACE_ASPEED_INTC_ENABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_ENABLE) || \ false) static inline void _nocheck__trace_aspeed_intc_enable(uint32_t value) { if (trace_event_get_state(TRACE_ASPEED_INTC_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 91 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_enable " "Enable: 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , value); #line 2872 "trace/trace-hw_intc.h" } else { #line 91 "../hw/intc/trace-events" qemu_log("aspeed_intc_enable " "Enable: 0x%x" "\n", value); #line 2876 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_enable(uint32_t value) { if (true) { _nocheck__trace_aspeed_intc_enable(value); } } #define TRACE_ASPEED_INTC_SELECT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_SELECT) || \ false) static inline void _nocheck__trace_aspeed_intc_select(uint32_t value) { if (trace_event_get_state(TRACE_ASPEED_INTC_SELECT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 92 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_select " "Select: 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , value); #line 2903 "trace/trace-hw_intc.h" } else { #line 92 "../hw/intc/trace-events" qemu_log("aspeed_intc_select " "Select: 0x%x" "\n", value); #line 2907 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_select(uint32_t value) { if (true) { _nocheck__trace_aspeed_intc_select(value); } } #define TRACE_ASPEED_INTC_MASK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_MASK) || \ false) static inline void _nocheck__trace_aspeed_intc_mask(uint32_t change, uint32_t value) { if (trace_event_get_state(TRACE_ASPEED_INTC_MASK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 93 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_mask " "Mask: 0x%x: 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , change, value); #line 2934 "trace/trace-hw_intc.h" } else { #line 93 "../hw/intc/trace-events" qemu_log("aspeed_intc_mask " "Mask: 0x%x: 0x%x" "\n", change, value); #line 2938 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_mask(uint32_t change, uint32_t value) { if (true) { _nocheck__trace_aspeed_intc_mask(change, value); } } #define TRACE_ASPEED_INTC_UNMASK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_INTC_UNMASK) || \ false) static inline void _nocheck__trace_aspeed_intc_unmask(uint32_t change, uint32_t value) { if (trace_event_get_state(TRACE_ASPEED_INTC_UNMASK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 94 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_intc_unmask " "UnMask: 0x%x: 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , change, value); #line 2965 "trace/trace-hw_intc.h" } else { #line 94 "../hw/intc/trace-events" qemu_log("aspeed_intc_unmask " "UnMask: 0x%x: 0x%x" "\n", change, value); #line 2969 "trace/trace-hw_intc.h" } } } static inline void trace_aspeed_intc_unmask(uint32_t change, uint32_t value) { if (true) { _nocheck__trace_aspeed_intc_unmask(change, value); } } #define TRACE_GIC_ENABLE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_ENABLE_IRQ) || \ false) static inline void _nocheck__trace_gic_enable_irq(int irq) { if (trace_event_get_state(TRACE_GIC_ENABLE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 97 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_enable_irq " "irq %d enabled" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq); #line 2996 "trace/trace-hw_intc.h" } else { #line 97 "../hw/intc/trace-events" qemu_log("gic_enable_irq " "irq %d enabled" "\n", irq); #line 3000 "trace/trace-hw_intc.h" } } } static inline void trace_gic_enable_irq(int irq) { if (true) { _nocheck__trace_gic_enable_irq(irq); } } #define TRACE_GIC_DISABLE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_DISABLE_IRQ) || \ false) static inline void _nocheck__trace_gic_disable_irq(int irq) { if (trace_event_get_state(TRACE_GIC_DISABLE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 98 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_disable_irq " "irq %d disabled" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq); #line 3027 "trace/trace-hw_intc.h" } else { #line 98 "../hw/intc/trace-events" qemu_log("gic_disable_irq " "irq %d disabled" "\n", irq); #line 3031 "trace/trace-hw_intc.h" } } } static inline void trace_gic_disable_irq(int irq) { if (true) { _nocheck__trace_gic_disable_irq(irq); } } #define TRACE_GIC_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_SET_IRQ) || \ false) static inline void _nocheck__trace_gic_set_irq(int irq, int level, int cpumask, int target) { if (trace_event_get_state(TRACE_GIC_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 99 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_set_irq " "irq %d level %d cpumask 0x%x target 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level, cpumask, target); #line 3058 "trace/trace-hw_intc.h" } else { #line 99 "../hw/intc/trace-events" qemu_log("gic_set_irq " "irq %d level %d cpumask 0x%x target 0x%x" "\n", irq, level, cpumask, target); #line 3062 "trace/trace-hw_intc.h" } } } static inline void trace_gic_set_irq(int irq, int level, int cpumask, int target) { if (true) { _nocheck__trace_gic_set_irq(irq, level, cpumask, target); } } #define TRACE_GIC_UPDATE_BESTIRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_UPDATE_BESTIRQ) || \ false) static inline void _nocheck__trace_gic_update_bestirq(const char * s, int cpu, int irq, int prio, int priority_mask, int running_priority) { if (trace_event_get_state(TRACE_GIC_UPDATE_BESTIRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 100 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_update_bestirq " "%s %d irq %d priority %d cpu priority mask %d cpu running priority %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , s, cpu, irq, prio, priority_mask, running_priority); #line 3089 "trace/trace-hw_intc.h" } else { #line 100 "../hw/intc/trace-events" qemu_log("gic_update_bestirq " "%s %d irq %d priority %d cpu priority mask %d cpu running priority %d" "\n", s, cpu, irq, prio, priority_mask, running_priority); #line 3093 "trace/trace-hw_intc.h" } } } static inline void trace_gic_update_bestirq(const char * s, int cpu, int irq, int prio, int priority_mask, int running_priority) { if (true) { _nocheck__trace_gic_update_bestirq(s, cpu, irq, prio, priority_mask, running_priority); } } #define TRACE_GIC_UPDATE_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_UPDATE_SET_IRQ) || \ false) static inline void _nocheck__trace_gic_update_set_irq(int cpu, const char * name, int level) { if (trace_event_get_state(TRACE_GIC_UPDATE_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 101 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_update_set_irq " "cpu[%d]: %s = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, name, level); #line 3120 "trace/trace-hw_intc.h" } else { #line 101 "../hw/intc/trace-events" qemu_log("gic_update_set_irq " "cpu[%d]: %s = %d" "\n", cpu, name, level); #line 3124 "trace/trace-hw_intc.h" } } } static inline void trace_gic_update_set_irq(int cpu, const char * name, int level) { if (true) { _nocheck__trace_gic_update_set_irq(cpu, name, level); } } #define TRACE_GIC_ACKNOWLEDGE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_ACKNOWLEDGE_IRQ) || \ false) static inline void _nocheck__trace_gic_acknowledge_irq(const char * s, int cpu, int irq) { if (trace_event_get_state(TRACE_GIC_ACKNOWLEDGE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 102 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_acknowledge_irq " "%s %d acknowledged irq %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , s, cpu, irq); #line 3151 "trace/trace-hw_intc.h" } else { #line 102 "../hw/intc/trace-events" qemu_log("gic_acknowledge_irq " "%s %d acknowledged irq %d" "\n", s, cpu, irq); #line 3155 "trace/trace-hw_intc.h" } } } static inline void trace_gic_acknowledge_irq(const char * s, int cpu, int irq) { if (true) { _nocheck__trace_gic_acknowledge_irq(s, cpu, irq); } } #define TRACE_GIC_CPU_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_CPU_WRITE) || \ false) static inline void _nocheck__trace_gic_cpu_write(const char * s, int cpu, int addr, uint32_t val) { if (trace_event_get_state(TRACE_GIC_CPU_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 103 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_cpu_write " "%s %d iface write at 0x%08x 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , s, cpu, addr, val); #line 3182 "trace/trace-hw_intc.h" } else { #line 103 "../hw/intc/trace-events" qemu_log("gic_cpu_write " "%s %d iface write at 0x%08x 0x%08" PRIx32 "\n", s, cpu, addr, val); #line 3186 "trace/trace-hw_intc.h" } } } static inline void trace_gic_cpu_write(const char * s, int cpu, int addr, uint32_t val) { if (true) { _nocheck__trace_gic_cpu_write(s, cpu, addr, val); } } #define TRACE_GIC_CPU_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_CPU_READ) || \ false) static inline void _nocheck__trace_gic_cpu_read(const char * s, int cpu, int addr, uint32_t val) { if (trace_event_get_state(TRACE_GIC_CPU_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 104 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_cpu_read " "%s %d iface read at 0x%08x: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , s, cpu, addr, val); #line 3213 "trace/trace-hw_intc.h" } else { #line 104 "../hw/intc/trace-events" qemu_log("gic_cpu_read " "%s %d iface read at 0x%08x: 0x%08" PRIx32 "\n", s, cpu, addr, val); #line 3217 "trace/trace-hw_intc.h" } } } static inline void trace_gic_cpu_read(const char * s, int cpu, int addr, uint32_t val) { if (true) { _nocheck__trace_gic_cpu_read(s, cpu, addr, val); } } #define TRACE_GIC_HYP_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_HYP_READ) || \ false) static inline void _nocheck__trace_gic_hyp_read(int addr, uint32_t val) { if (trace_event_get_state(TRACE_GIC_HYP_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 105 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_hyp_read " "hyp read at 0x%08x: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 3244 "trace/trace-hw_intc.h" } else { #line 105 "../hw/intc/trace-events" qemu_log("gic_hyp_read " "hyp read at 0x%08x: 0x%08" PRIx32 "\n", addr, val); #line 3248 "trace/trace-hw_intc.h" } } } static inline void trace_gic_hyp_read(int addr, uint32_t val) { if (true) { _nocheck__trace_gic_hyp_read(addr, val); } } #define TRACE_GIC_HYP_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_HYP_WRITE) || \ false) static inline void _nocheck__trace_gic_hyp_write(int addr, uint32_t val) { if (trace_event_get_state(TRACE_GIC_HYP_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 106 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_hyp_write " "hyp write at 0x%08x: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 3275 "trace/trace-hw_intc.h" } else { #line 106 "../hw/intc/trace-events" qemu_log("gic_hyp_write " "hyp write at 0x%08x: 0x%08" PRIx32 "\n", addr, val); #line 3279 "trace/trace-hw_intc.h" } } } static inline void trace_gic_hyp_write(int addr, uint32_t val) { if (true) { _nocheck__trace_gic_hyp_write(addr, val); } } #define TRACE_GIC_DIST_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_DIST_READ) || \ false) static inline void _nocheck__trace_gic_dist_read(int addr, unsigned int size, uint32_t val) { if (trace_event_get_state(TRACE_GIC_DIST_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 107 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_dist_read " "dist read at 0x%08x size %u: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, size, val); #line 3306 "trace/trace-hw_intc.h" } else { #line 107 "../hw/intc/trace-events" qemu_log("gic_dist_read " "dist read at 0x%08x size %u: 0x%08" PRIx32 "\n", addr, size, val); #line 3310 "trace/trace-hw_intc.h" } } } static inline void trace_gic_dist_read(int addr, unsigned int size, uint32_t val) { if (true) { _nocheck__trace_gic_dist_read(addr, size, val); } } #define TRACE_GIC_DIST_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_DIST_WRITE) || \ false) static inline void _nocheck__trace_gic_dist_write(int addr, unsigned int size, uint32_t val) { if (trace_event_get_state(TRACE_GIC_DIST_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 108 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_dist_write " "dist write at 0x%08x size %u: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, size, val); #line 3337 "trace/trace-hw_intc.h" } else { #line 108 "../hw/intc/trace-events" qemu_log("gic_dist_write " "dist write at 0x%08x size %u: 0x%08" PRIx32 "\n", addr, size, val); #line 3341 "trace/trace-hw_intc.h" } } } static inline void trace_gic_dist_write(int addr, unsigned int size, uint32_t val) { if (true) { _nocheck__trace_gic_dist_write(addr, size, val); } } #define TRACE_GIC_LR_ENTRY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_LR_ENTRY) || \ false) static inline void _nocheck__trace_gic_lr_entry(int cpu, int entry, uint32_t val) { if (trace_event_get_state(TRACE_GIC_LR_ENTRY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 109 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_lr_entry " "cpu %d: new lr entry %d: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, entry, val); #line 3368 "trace/trace-hw_intc.h" } else { #line 109 "../hw/intc/trace-events" qemu_log("gic_lr_entry " "cpu %d: new lr entry %d: 0x%08" PRIx32 "\n", cpu, entry, val); #line 3372 "trace/trace-hw_intc.h" } } } static inline void trace_gic_lr_entry(int cpu, int entry, uint32_t val) { if (true) { _nocheck__trace_gic_lr_entry(cpu, entry, val); } } #define TRACE_GIC_UPDATE_MAINTENANCE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GIC_UPDATE_MAINTENANCE_IRQ) || \ false) static inline void _nocheck__trace_gic_update_maintenance_irq(int cpu, int val) { if (trace_event_get_state(TRACE_GIC_UPDATE_MAINTENANCE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 110 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gic_update_maintenance_irq " "cpu %d: maintenance = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 3399 "trace/trace-hw_intc.h" } else { #line 110 "../hw/intc/trace-events" qemu_log("gic_update_maintenance_irq " "cpu %d: maintenance = %d" "\n", cpu, val); #line 3403 "trace/trace-hw_intc.h" } } } static inline void trace_gic_update_maintenance_irq(int cpu, int val) { if (true) { _nocheck__trace_gic_update_maintenance_irq(cpu, val); } } #define TRACE_GICV3_ICC_PMR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_PMR_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_pmr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_PMR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 113 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_pmr_read " "GICv3 ICC_PMR read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 3430 "trace/trace-hw_intc.h" } else { #line 113 "../hw/intc/trace-events" qemu_log("gicv3_icc_pmr_read " "GICv3 ICC_PMR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 3434 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_pmr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_pmr_read(cpu, val); } } #define TRACE_GICV3_ICC_PMR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_PMR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icc_pmr_write(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_PMR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 114 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_pmr_write " "GICv3 ICC_PMR write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 3461 "trace/trace-hw_intc.h" } else { #line 114 "../hw/intc/trace-events" qemu_log("gicv3_icc_pmr_write " "GICv3 ICC_PMR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 3465 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_pmr_write(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_pmr_write(cpu, val); } } #define TRACE_GICV3_ICC_BPR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_BPR_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_bpr_read(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_BPR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 115 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_bpr_read " "GICv3 ICC_BPR%d read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 3492 "trace/trace-hw_intc.h" } else { #line 115 "../hw/intc/trace-events" qemu_log("gicv3_icc_bpr_read " "GICv3 ICC_BPR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 3496 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_bpr_read(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_bpr_read(grp, cpu, val); } } #define TRACE_GICV3_ICC_BPR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_BPR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icc_bpr_write(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_BPR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 116 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_bpr_write " "GICv3 ICC_BPR%d write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 3523 "trace/trace-hw_intc.h" } else { #line 116 "../hw/intc/trace-events" qemu_log("gicv3_icc_bpr_write " "GICv3 ICC_BPR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 3527 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_bpr_write(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_bpr_write(grp, cpu, val); } } #define TRACE_GICV3_ICC_AP_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_AP_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_AP_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 117 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_ap_read " "GICv3 ICC_AP%dR%d read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, regno, cpu, val); #line 3554 "trace/trace-hw_intc.h" } else { #line 117 "../hw/intc/trace-events" qemu_log("gicv3_icc_ap_read " "GICv3 ICC_AP%dR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val); #line 3558 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_ap_read(grp, regno, cpu, val); } } #define TRACE_GICV3_ICC_AP_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_AP_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icc_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_AP_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 118 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_ap_write " "GICv3 ICC_AP%dR%d write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, regno, cpu, val); #line 3585 "trace/trace-hw_intc.h" } else { #line 118 "../hw/intc/trace-events" qemu_log("gicv3_icc_ap_write " "GICv3 ICC_AP%dR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val); #line 3589 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_ap_write(grp, regno, cpu, val); } } #define TRACE_GICV3_ICC_IGRPEN_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IGRPEN_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_igrpen_read(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_IGRPEN_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 119 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_igrpen_read " "GICv3 ICC_IGRPEN%d read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 3616 "trace/trace-hw_intc.h" } else { #line 119 "../hw/intc/trace-events" qemu_log("gicv3_icc_igrpen_read " "GICv3 ICC_IGRPEN%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 3620 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_igrpen_read(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_igrpen_read(grp, cpu, val); } } #define TRACE_GICV3_ICC_IGRPEN_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IGRPEN_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icc_igrpen_write(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_IGRPEN_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 120 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_igrpen_write " "GICv3 ICC_IGRPEN%d write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 3647 "trace/trace-hw_intc.h" } else { #line 120 "../hw/intc/trace-events" qemu_log("gicv3_icc_igrpen_write " "GICv3 ICC_IGRPEN%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 3651 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_igrpen_write(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_igrpen_write(grp, cpu, val); } } #define TRACE_GICV3_ICC_IGRPEN1_EL3_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IGRPEN1_EL3_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_igrpen1_el3_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_IGRPEN1_EL3_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 121 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_igrpen1_el3_read " "GICv3 ICC_IGRPEN1_EL3 read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 3678 "trace/trace-hw_intc.h" } else { #line 121 "../hw/intc/trace-events" qemu_log("gicv3_icc_igrpen1_el3_read " "GICv3 ICC_IGRPEN1_EL3 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 3682 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_igrpen1_el3_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_igrpen1_el3_read(cpu, val); } } #define TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icc_igrpen1_el3_write(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_IGRPEN1_EL3_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 122 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_igrpen1_el3_write " "GICv3 ICC_IGRPEN1_EL3 write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 3709 "trace/trace-hw_intc.h" } else { #line 122 "../hw/intc/trace-events" qemu_log("gicv3_icc_igrpen1_el3_write " "GICv3 ICC_IGRPEN1_EL3 write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 3713 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_igrpen1_el3_write(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_igrpen1_el3_write(cpu, val); } } #define TRACE_GICV3_ICC_CTLR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_CTLR_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_ctlr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_CTLR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 123 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_ctlr_read " "GICv3 ICC_CTLR read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 3740 "trace/trace-hw_intc.h" } else { #line 123 "../hw/intc/trace-events" qemu_log("gicv3_icc_ctlr_read " "GICv3 ICC_CTLR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 3744 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_ctlr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_ctlr_read(cpu, val); } } #define TRACE_GICV3_ICC_CTLR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_CTLR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icc_ctlr_write(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_CTLR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 124 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_ctlr_write " "GICv3 ICC_CTLR write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 3771 "trace/trace-hw_intc.h" } else { #line 124 "../hw/intc/trace-events" qemu_log("gicv3_icc_ctlr_write " "GICv3 ICC_CTLR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 3775 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_ctlr_write(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_ctlr_write(cpu, val); } } #define TRACE_GICV3_ICC_CTLR_EL3_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_CTLR_EL3_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_ctlr_el3_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_CTLR_EL3_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 125 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_ctlr_el3_read " "GICv3 ICC_CTLR_EL3 read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 3802 "trace/trace-hw_intc.h" } else { #line 125 "../hw/intc/trace-events" qemu_log("gicv3_icc_ctlr_el3_read " "GICv3 ICC_CTLR_EL3 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 3806 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_ctlr_el3_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_ctlr_el3_read(cpu, val); } } #define TRACE_GICV3_ICC_CTLR_EL3_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_CTLR_EL3_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icc_ctlr_el3_write(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_CTLR_EL3_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 126 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_ctlr_el3_write " "GICv3 ICC_CTLR_EL3 write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 3833 "trace/trace-hw_intc.h" } else { #line 126 "../hw/intc/trace-events" qemu_log("gicv3_icc_ctlr_el3_write " "GICv3 ICC_CTLR_EL3 write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 3837 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_ctlr_el3_write(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_ctlr_el3_write(cpu, val); } } #define TRACE_GICV3_CPUIF_UPDATE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_CPUIF_UPDATE) || \ false) static inline void _nocheck__trace_gicv3_cpuif_update(uint32_t cpuid, int irq, int grp, int prio) { if (trace_event_get_state(TRACE_GICV3_CPUIF_UPDATE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 127 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_cpuif_update " "GICv3 CPU i/f 0x%x HPPI update: irq %d group %d prio %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpuid, irq, grp, prio); #line 3864 "trace/trace-hw_intc.h" } else { #line 127 "../hw/intc/trace-events" qemu_log("gicv3_cpuif_update " "GICv3 CPU i/f 0x%x HPPI update: irq %d group %d prio %d" "\n", cpuid, irq, grp, prio); #line 3868 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_cpuif_update(uint32_t cpuid, int irq, int grp, int prio) { if (true) { _nocheck__trace_gicv3_cpuif_update(cpuid, irq, grp, prio); } } #define TRACE_GICV3_CPUIF_SET_IRQS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_CPUIF_SET_IRQS) || \ false) static inline void _nocheck__trace_gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) { if (trace_event_get_state(TRACE_GICV3_CPUIF_SET_IRQS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 128 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_cpuif_set_irqs " "GICv3 CPU i/f 0x%x HPPI update: setting FIQ %d IRQ %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpuid, fiqlevel, irqlevel); #line 3895 "trace/trace-hw_intc.h" } else { #line 128 "../hw/intc/trace-events" qemu_log("gicv3_cpuif_set_irqs " "GICv3 CPU i/f 0x%x HPPI update: setting FIQ %d IRQ %d" "\n", cpuid, fiqlevel, irqlevel); #line 3899 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) { if (true) { _nocheck__trace_gicv3_cpuif_set_irqs(cpuid, fiqlevel, irqlevel); } } #define TRACE_GICV3_ICC_GENERATE_SGI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_GENERATE_SGI) || \ false) static inline void _nocheck__trace_gicv3_icc_generate_sgi(uint32_t cpuid, int irq, int irm, uint32_t aff, uint32_t targetlist) { if (trace_event_get_state(TRACE_GICV3_ICC_GENERATE_SGI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 129 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_generate_sgi " "GICv3 CPU i/f 0x%x generating SGI %d IRM %d target affinity 0x%xxx targetlist 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpuid, irq, irm, aff, targetlist); #line 3926 "trace/trace-hw_intc.h" } else { #line 129 "../hw/intc/trace-events" qemu_log("gicv3_icc_generate_sgi " "GICv3 CPU i/f 0x%x generating SGI %d IRM %d target affinity 0x%xxx targetlist 0x%x" "\n", cpuid, irq, irm, aff, targetlist); #line 3930 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_generate_sgi(uint32_t cpuid, int irq, int irm, uint32_t aff, uint32_t targetlist) { if (true) { _nocheck__trace_gicv3_icc_generate_sgi(cpuid, irq, irm, aff, targetlist); } } #define TRACE_GICV3_ICC_IAR0_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IAR0_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_iar0_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_IAR0_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 130 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_iar0_read " "GICv3 ICC_IAR0 read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 3957 "trace/trace-hw_intc.h" } else { #line 130 "../hw/intc/trace-events" qemu_log("gicv3_icc_iar0_read " "GICv3 ICC_IAR0 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 3961 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_iar0_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_iar0_read(cpu, val); } } #define TRACE_GICV3_ICC_IAR1_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_IAR1_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_iar1_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_IAR1_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 131 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_iar1_read " "GICv3 ICC_IAR1 read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 3988 "trace/trace-hw_intc.h" } else { #line 131 "../hw/intc/trace-events" qemu_log("gicv3_icc_iar1_read " "GICv3 ICC_IAR1 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 3992 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_iar1_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_iar1_read(cpu, val); } } #define TRACE_GICV3_ICC_NMIAR1_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_NMIAR1_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_nmiar1_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_NMIAR1_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 132 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_nmiar1_read " "GICv3 ICC_NMIAR1 read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4019 "trace/trace-hw_intc.h" } else { #line 132 "../hw/intc/trace-events" qemu_log("gicv3_icc_nmiar1_read " "GICv3 ICC_NMIAR1 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4023 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_nmiar1_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_nmiar1_read(cpu, val); } } #define TRACE_GICV3_ICC_EOIR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_EOIR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icc_eoir_write(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_EOIR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 133 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_eoir_write " "GICv3 ICC_EOIR%d write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 4050 "trace/trace-hw_intc.h" } else { #line 133 "../hw/intc/trace-events" qemu_log("gicv3_icc_eoir_write " "GICv3 ICC_EOIR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 4054 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_eoir_write(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_eoir_write(grp, cpu, val); } } #define TRACE_GICV3_ICC_HPPIR0_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_HPPIR0_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_hppir0_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_HPPIR0_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 134 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_hppir0_read " "GICv3 ICC_HPPIR0 read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4081 "trace/trace-hw_intc.h" } else { #line 134 "../hw/intc/trace-events" qemu_log("gicv3_icc_hppir0_read " "GICv3 ICC_HPPIR0 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4085 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_hppir0_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_hppir0_read(cpu, val); } } #define TRACE_GICV3_ICC_HPPIR1_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_HPPIR1_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_hppir1_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_HPPIR1_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 135 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_hppir1_read " "GICv3 ICC_HPPIR1 read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4112 "trace/trace-hw_intc.h" } else { #line 135 "../hw/intc/trace-events" qemu_log("gicv3_icc_hppir1_read " "GICv3 ICC_HPPIR1 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4116 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_hppir1_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_hppir1_read(cpu, val); } } #define TRACE_GICV3_ICC_DIR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_DIR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icc_dir_write(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_DIR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 136 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_dir_write " "GICv3 ICC_DIR write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4143 "trace/trace-hw_intc.h" } else { #line 136 "../hw/intc/trace-events" qemu_log("gicv3_icc_dir_write " "GICv3 ICC_DIR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4147 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_dir_write(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_dir_write(cpu, val); } } #define TRACE_GICV3_ICC_RPR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICC_RPR_READ) || \ false) static inline void _nocheck__trace_gicv3_icc_rpr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICC_RPR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 137 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icc_rpr_read " "GICv3 ICC_RPR read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4174 "trace/trace-hw_intc.h" } else { #line 137 "../hw/intc/trace-events" qemu_log("gicv3_icc_rpr_read " "GICv3 ICC_RPR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4178 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icc_rpr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icc_rpr_read(cpu, val); } } #define TRACE_GICV3_ICH_AP_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_AP_READ) || \ false) static inline void _nocheck__trace_gicv3_ich_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_AP_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 138 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_ap_read " "GICv3 ICH_AP%dR%d read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, regno, cpu, val); #line 4205 "trace/trace-hw_intc.h" } else { #line 138 "../hw/intc/trace-events" qemu_log("gicv3_ich_ap_read " "GICv3 ICH_AP%dR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val); #line 4209 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_ap_read(grp, regno, cpu, val); } } #define TRACE_GICV3_ICH_AP_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_AP_WRITE) || \ false) static inline void _nocheck__trace_gicv3_ich_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_AP_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 139 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_ap_write " "GICv3 ICH_AP%dR%d write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, regno, cpu, val); #line 4236 "trace/trace-hw_intc.h" } else { #line 139 "../hw/intc/trace-events" qemu_log("gicv3_ich_ap_write " "GICv3 ICH_AP%dR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val); #line 4240 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_ap_write(grp, regno, cpu, val); } } #define TRACE_GICV3_ICH_HCR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_HCR_READ) || \ false) static inline void _nocheck__trace_gicv3_ich_hcr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_HCR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 140 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_hcr_read " "GICv3 ICH_HCR_EL2 read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4267 "trace/trace-hw_intc.h" } else { #line 140 "../hw/intc/trace-events" qemu_log("gicv3_ich_hcr_read " "GICv3 ICH_HCR_EL2 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4271 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_hcr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_hcr_read(cpu, val); } } #define TRACE_GICV3_ICH_HCR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_HCR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_ich_hcr_write(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_HCR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 141 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_hcr_write " "GICv3 ICH_HCR_EL2 write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4298 "trace/trace-hw_intc.h" } else { #line 141 "../hw/intc/trace-events" qemu_log("gicv3_ich_hcr_write " "GICv3 ICH_HCR_EL2 write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4302 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_hcr_write(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_hcr_write(cpu, val); } } #define TRACE_GICV3_ICH_VMCR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_VMCR_READ) || \ false) static inline void _nocheck__trace_gicv3_ich_vmcr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_VMCR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 142 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_vmcr_read " "GICv3 ICH_VMCR_EL2 read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4329 "trace/trace-hw_intc.h" } else { #line 142 "../hw/intc/trace-events" qemu_log("gicv3_ich_vmcr_read " "GICv3 ICH_VMCR_EL2 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4333 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_vmcr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_vmcr_read(cpu, val); } } #define TRACE_GICV3_ICH_VMCR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_VMCR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_ich_vmcr_write(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_VMCR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 143 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_vmcr_write " "GICv3 ICH_VMCR_EL2 write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4360 "trace/trace-hw_intc.h" } else { #line 143 "../hw/intc/trace-events" qemu_log("gicv3_ich_vmcr_write " "GICv3 ICH_VMCR_EL2 write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4364 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_vmcr_write(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_vmcr_write(cpu, val); } } #define TRACE_GICV3_ICH_LR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LR_READ) || \ false) static inline void _nocheck__trace_gicv3_ich_lr_read(int regno, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_LR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 144 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_lr_read " "GICv3 ICH_LR%d_EL2 read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , regno, cpu, val); #line 4391 "trace/trace-hw_intc.h" } else { #line 144 "../hw/intc/trace-events" qemu_log("gicv3_ich_lr_read " "GICv3 ICH_LR%d_EL2 read cpu 0x%x value 0x%" PRIx64 "\n", regno, cpu, val); #line 4395 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_lr_read(int regno, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_lr_read(regno, cpu, val); } } #define TRACE_GICV3_ICH_LR32_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LR32_READ) || \ false) static inline void _nocheck__trace_gicv3_ich_lr32_read(int regno, uint32_t cpu, uint32_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_LR32_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 145 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_lr32_read " "GICv3 ICH_LR%d read cpu 0x%x value 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , regno, cpu, val); #line 4422 "trace/trace-hw_intc.h" } else { #line 145 "../hw/intc/trace-events" qemu_log("gicv3_ich_lr32_read " "GICv3 ICH_LR%d read cpu 0x%x value 0x%" PRIx32 "\n", regno, cpu, val); #line 4426 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_lr32_read(int regno, uint32_t cpu, uint32_t val) { if (true) { _nocheck__trace_gicv3_ich_lr32_read(regno, cpu, val); } } #define TRACE_GICV3_ICH_LRC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LRC_READ) || \ false) static inline void _nocheck__trace_gicv3_ich_lrc_read(int regno, uint32_t cpu, uint32_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_LRC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 146 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_lrc_read " "GICv3 ICH_LRC%d read cpu 0x%x value 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , regno, cpu, val); #line 4453 "trace/trace-hw_intc.h" } else { #line 146 "../hw/intc/trace-events" qemu_log("gicv3_ich_lrc_read " "GICv3 ICH_LRC%d read cpu 0x%x value 0x%" PRIx32 "\n", regno, cpu, val); #line 4457 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_lrc_read(int regno, uint32_t cpu, uint32_t val) { if (true) { _nocheck__trace_gicv3_ich_lrc_read(regno, cpu, val); } } #define TRACE_GICV3_ICH_LR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_ich_lr_write(int regno, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_LR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 147 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_lr_write " "GICv3 ICH_LR%d_EL2 write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , regno, cpu, val); #line 4484 "trace/trace-hw_intc.h" } else { #line 147 "../hw/intc/trace-events" qemu_log("gicv3_ich_lr_write " "GICv3 ICH_LR%d_EL2 write cpu 0x%x value 0x%" PRIx64 "\n", regno, cpu, val); #line 4488 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_lr_write(int regno, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_lr_write(regno, cpu, val); } } #define TRACE_GICV3_ICH_LR32_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LR32_WRITE) || \ false) static inline void _nocheck__trace_gicv3_ich_lr32_write(int regno, uint32_t cpu, uint32_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_LR32_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 148 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_lr32_write " "GICv3 ICH_LR%d write cpu 0x%x value 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , regno, cpu, val); #line 4515 "trace/trace-hw_intc.h" } else { #line 148 "../hw/intc/trace-events" qemu_log("gicv3_ich_lr32_write " "GICv3 ICH_LR%d write cpu 0x%x value 0x%" PRIx32 "\n", regno, cpu, val); #line 4519 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_lr32_write(int regno, uint32_t cpu, uint32_t val) { if (true) { _nocheck__trace_gicv3_ich_lr32_write(regno, cpu, val); } } #define TRACE_GICV3_ICH_LRC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_LRC_WRITE) || \ false) static inline void _nocheck__trace_gicv3_ich_lrc_write(int regno, uint32_t cpu, uint32_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_LRC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 149 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_lrc_write " "GICv3 ICH_LRC%d write cpu 0x%x value 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , regno, cpu, val); #line 4546 "trace/trace-hw_intc.h" } else { #line 149 "../hw/intc/trace-events" qemu_log("gicv3_ich_lrc_write " "GICv3 ICH_LRC%d write cpu 0x%x value 0x%" PRIx32 "\n", regno, cpu, val); #line 4550 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_lrc_write(int regno, uint32_t cpu, uint32_t val) { if (true) { _nocheck__trace_gicv3_ich_lrc_write(regno, cpu, val); } } #define TRACE_GICV3_ICH_VTR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_VTR_READ) || \ false) static inline void _nocheck__trace_gicv3_ich_vtr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_VTR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 150 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_vtr_read " "GICv3 ICH_VTR read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4577 "trace/trace-hw_intc.h" } else { #line 150 "../hw/intc/trace-events" qemu_log("gicv3_ich_vtr_read " "GICv3 ICH_VTR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4581 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_vtr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_vtr_read(cpu, val); } } #define TRACE_GICV3_ICH_MISR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_MISR_READ) || \ false) static inline void _nocheck__trace_gicv3_ich_misr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_MISR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 151 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_misr_read " "GICv3 ICH_MISR read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4608 "trace/trace-hw_intc.h" } else { #line 151 "../hw/intc/trace-events" qemu_log("gicv3_ich_misr_read " "GICv3 ICH_MISR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4612 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_misr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_misr_read(cpu, val); } } #define TRACE_GICV3_ICH_EISR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_EISR_READ) || \ false) static inline void _nocheck__trace_gicv3_ich_eisr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_EISR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 152 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_eisr_read " "GICv3 ICH_EISR read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4639 "trace/trace-hw_intc.h" } else { #line 152 "../hw/intc/trace-events" qemu_log("gicv3_ich_eisr_read " "GICv3 ICH_EISR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4643 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_eisr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_eisr_read(cpu, val); } } #define TRACE_GICV3_ICH_ELRSR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICH_ELRSR_READ) || \ false) static inline void _nocheck__trace_gicv3_ich_elrsr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICH_ELRSR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 153 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_ich_elrsr_read " "GICv3 ICH_ELRSR read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4670 "trace/trace-hw_intc.h" } else { #line 153 "../hw/intc/trace-events" qemu_log("gicv3_ich_elrsr_read " "GICv3 ICH_ELRSR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4674 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_ich_elrsr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_ich_elrsr_read(cpu, val); } } #define TRACE_GICV3_ICV_AP_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_AP_READ) || \ false) static inline void _nocheck__trace_gicv3_icv_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_AP_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 154 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_ap_read " "GICv3 ICV_AP%dR%d read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, regno, cpu, val); #line 4701 "trace/trace-hw_intc.h" } else { #line 154 "../hw/intc/trace-events" qemu_log("gicv3_icv_ap_read " "GICv3 ICV_AP%dR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val); #line 4705 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_ap_read(grp, regno, cpu, val); } } #define TRACE_GICV3_ICV_AP_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_AP_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icv_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_AP_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 155 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_ap_write " "GICv3 ICV_AP%dR%d write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, regno, cpu, val); #line 4732 "trace/trace-hw_intc.h" } else { #line 155 "../hw/intc/trace-events" qemu_log("gicv3_icv_ap_write " "GICv3 ICV_AP%dR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, regno, cpu, val); #line 4736 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_ap_write(grp, regno, cpu, val); } } #define TRACE_GICV3_ICV_BPR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_BPR_READ) || \ false) static inline void _nocheck__trace_gicv3_icv_bpr_read(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_BPR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 156 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_bpr_read " "GICv3 ICV_BPR%d read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 4763 "trace/trace-hw_intc.h" } else { #line 156 "../hw/intc/trace-events" qemu_log("gicv3_icv_bpr_read " "GICv3 ICV_BPR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 4767 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_bpr_read(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_bpr_read(grp, cpu, val); } } #define TRACE_GICV3_ICV_BPR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_BPR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icv_bpr_write(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_BPR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 157 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_bpr_write " "GICv3 ICV_BPR%d write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 4794 "trace/trace-hw_intc.h" } else { #line 157 "../hw/intc/trace-events" qemu_log("gicv3_icv_bpr_write " "GICv3 ICV_BPR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 4798 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_bpr_write(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_bpr_write(grp, cpu, val); } } #define TRACE_GICV3_ICV_PMR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_PMR_READ) || \ false) static inline void _nocheck__trace_gicv3_icv_pmr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_PMR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 158 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_pmr_read " "GICv3 ICV_PMR read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4825 "trace/trace-hw_intc.h" } else { #line 158 "../hw/intc/trace-events" qemu_log("gicv3_icv_pmr_read " "GICv3 ICV_PMR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4829 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_pmr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_pmr_read(cpu, val); } } #define TRACE_GICV3_ICV_PMR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_PMR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icv_pmr_write(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_PMR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 159 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_pmr_write " "GICv3 ICV_PMR write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4856 "trace/trace-hw_intc.h" } else { #line 159 "../hw/intc/trace-events" qemu_log("gicv3_icv_pmr_write " "GICv3 ICV_PMR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4860 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_pmr_write(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_pmr_write(cpu, val); } } #define TRACE_GICV3_ICV_IGRPEN_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_IGRPEN_READ) || \ false) static inline void _nocheck__trace_gicv3_icv_igrpen_read(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_IGRPEN_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 160 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_igrpen_read " "GICv3 ICV_IGRPEN%d read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 4887 "trace/trace-hw_intc.h" } else { #line 160 "../hw/intc/trace-events" qemu_log("gicv3_icv_igrpen_read " "GICv3 ICV_IGRPEN%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 4891 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_igrpen_read(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_igrpen_read(grp, cpu, val); } } #define TRACE_GICV3_ICV_IGRPEN_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_IGRPEN_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icv_igrpen_write(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_IGRPEN_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 161 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_igrpen_write " "GICv3 ICV_IGRPEN%d write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 4918 "trace/trace-hw_intc.h" } else { #line 161 "../hw/intc/trace-events" qemu_log("gicv3_icv_igrpen_write " "GICv3 ICV_IGRPEN%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 4922 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_igrpen_write(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_igrpen_write(grp, cpu, val); } } #define TRACE_GICV3_ICV_CTLR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_CTLR_READ) || \ false) static inline void _nocheck__trace_gicv3_icv_ctlr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_CTLR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 162 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_ctlr_read " "GICv3 ICV_CTLR read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4949 "trace/trace-hw_intc.h" } else { #line 162 "../hw/intc/trace-events" qemu_log("gicv3_icv_ctlr_read " "GICv3 ICV_CTLR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4953 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_ctlr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_ctlr_read(cpu, val); } } #define TRACE_GICV3_ICV_CTLR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_CTLR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icv_ctlr_write(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_CTLR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 163 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_ctlr_write " "GICv3 ICV_CTLR write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 4980 "trace/trace-hw_intc.h" } else { #line 163 "../hw/intc/trace-events" qemu_log("gicv3_icv_ctlr_write " "GICv3 ICV_CTLR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 4984 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_ctlr_write(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_ctlr_write(cpu, val); } } #define TRACE_GICV3_ICV_RPR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_RPR_READ) || \ false) static inline void _nocheck__trace_gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_RPR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 164 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_rpr_read " "GICv3 ICV_RPR read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 5011 "trace/trace-hw_intc.h" } else { #line 164 "../hw/intc/trace-events" qemu_log("gicv3_icv_rpr_read " "GICv3 ICV_RPR read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 5015 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_rpr_read(cpu, val); } } #define TRACE_GICV3_ICV_HPPIR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_HPPIR_READ) || \ false) static inline void _nocheck__trace_gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_HPPIR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 165 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_hppir_read " "GICv3 ICV_HPPIR%d read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 5042 "trace/trace-hw_intc.h" } else { #line 165 "../hw/intc/trace-events" qemu_log("gicv3_icv_hppir_read " "GICv3 ICV_HPPIR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 5046 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_hppir_read(grp, cpu, val); } } #define TRACE_GICV3_ICV_DIR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_DIR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icv_dir_write(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_DIR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 166 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_dir_write " "GICv3 ICV_DIR write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 5073 "trace/trace-hw_intc.h" } else { #line 166 "../hw/intc/trace-events" qemu_log("gicv3_icv_dir_write " "GICv3 ICV_DIR write cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 5077 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_dir_write(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_dir_write(cpu, val); } } #define TRACE_GICV3_ICV_IAR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_IAR_READ) || \ false) static inline void _nocheck__trace_gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_IAR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 167 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_iar_read " "GICv3 ICV_IAR%d read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 5104 "trace/trace-hw_intc.h" } else { #line 167 "../hw/intc/trace-events" qemu_log("gicv3_icv_iar_read " "GICv3 ICV_IAR%d read cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 5108 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_iar_read(grp, cpu, val); } } #define TRACE_GICV3_ICV_NMIAR1_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_NMIAR1_READ) || \ false) static inline void _nocheck__trace_gicv3_icv_nmiar1_read(uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_NMIAR1_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 168 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_nmiar1_read " "GICv3 ICV_NMIAR1 read cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, val); #line 5135 "trace/trace-hw_intc.h" } else { #line 168 "../hw/intc/trace-events" qemu_log("gicv3_icv_nmiar1_read " "GICv3 ICV_NMIAR1 read cpu 0x%x value 0x%" PRIx64 "\n", cpu, val); #line 5139 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_nmiar1_read(uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_nmiar1_read(cpu, val); } } #define TRACE_GICV3_ICV_EOIR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ICV_EOIR_WRITE) || \ false) static inline void _nocheck__trace_gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) { if (trace_event_get_state(TRACE_GICV3_ICV_EOIR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 169 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_icv_eoir_write " "GICv3 ICV_EOIR%d write cpu 0x%x value 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , grp, cpu, val); #line 5166 "trace/trace-hw_intc.h" } else { #line 169 "../hw/intc/trace-events" qemu_log("gicv3_icv_eoir_write " "GICv3 ICV_EOIR%d write cpu 0x%x value 0x%" PRIx64 "\n", grp, cpu, val); #line 5170 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) { if (true) { _nocheck__trace_gicv3_icv_eoir_write(grp, cpu, val); } } #define TRACE_GICV3_CPUIF_VIRT_UPDATE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_CPUIF_VIRT_UPDATE) || \ false) static inline void _nocheck__trace_gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hppvlpi, int grp, int prio) { if (trace_event_get_state(TRACE_GICV3_CPUIF_VIRT_UPDATE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 170 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_cpuif_virt_update " "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d grp %d prio %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpuid, idx, hppvlpi, grp, prio); #line 5197 "trace/trace-hw_intc.h" } else { #line 170 "../hw/intc/trace-events" qemu_log("gicv3_cpuif_virt_update " "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d grp %d prio %d" "\n", cpuid, idx, hppvlpi, grp, prio); #line 5201 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hppvlpi, int grp, int prio) { if (true) { _nocheck__trace_gicv3_cpuif_virt_update(cpuid, idx, hppvlpi, grp, prio); } } #define TRACE_GICV3_CPUIF_VIRT_SET_IRQS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_CPUIF_VIRT_SET_IRQS) || \ false) static inline void _nocheck__trace_gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) { if (trace_event_get_state(TRACE_GICV3_CPUIF_VIRT_SET_IRQS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 171 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_cpuif_virt_set_irqs " "GICv3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpuid, fiqlevel, irqlevel); #line 5228 "trace/trace-hw_intc.h" } else { #line 171 "../hw/intc/trace-events" qemu_log("gicv3_cpuif_virt_set_irqs " "GICv3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d" "\n", cpuid, fiqlevel, irqlevel); #line 5232 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) { if (true) { _nocheck__trace_gicv3_cpuif_virt_set_irqs(cpuid, fiqlevel, irqlevel); } } #define TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ) || \ false) static inline void _nocheck__trace_gicv3_cpuif_virt_set_maint_irq(uint32_t cpuid, int maintlevel) { if (trace_event_get_state(TRACE_GICV3_CPUIF_VIRT_SET_MAINT_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 172 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_cpuif_virt_set_maint_irq " "GICv3 CPU i/f 0x%x virt HPPI update: setting maintenance-irq %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpuid, maintlevel); #line 5259 "trace/trace-hw_intc.h" } else { #line 172 "../hw/intc/trace-events" qemu_log("gicv3_cpuif_virt_set_maint_irq " "GICv3 CPU i/f 0x%x virt HPPI update: setting maintenance-irq %d" "\n", cpuid, maintlevel); #line 5263 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_cpuif_virt_set_maint_irq(uint32_t cpuid, int maintlevel) { if (true) { _nocheck__trace_gicv3_cpuif_virt_set_maint_irq(cpuid, maintlevel); } } #define TRACE_GICV3_DIST_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_DIST_READ) || \ false) static inline void _nocheck__trace_gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) { if (trace_event_get_state(TRACE_GICV3_DIST_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 175 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_dist_read " "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size, secure); #line 5290 "trace/trace-hw_intc.h" } else { #line 175 "../hw/intc/trace-events" qemu_log("gicv3_dist_read " "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", offset, data, size, secure); #line 5294 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) { if (true) { _nocheck__trace_gicv3_dist_read(offset, data, size, secure); } } #define TRACE_GICV3_DIST_BADREAD_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_DIST_BADREAD) || \ false) static inline void _nocheck__trace_gicv3_dist_badread(uint64_t offset, unsigned size, bool secure) { if (trace_event_get_state(TRACE_GICV3_DIST_BADREAD) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 176 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_dist_badread " "GICv3 distributor read: offset 0x%" PRIx64 " size %u secure %d: error" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, secure); #line 5321 "trace/trace-hw_intc.h" } else { #line 176 "../hw/intc/trace-events" qemu_log("gicv3_dist_badread " "GICv3 distributor read: offset 0x%" PRIx64 " size %u secure %d: error" "\n", offset, size, secure); #line 5325 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_dist_badread(uint64_t offset, unsigned size, bool secure) { if (true) { _nocheck__trace_gicv3_dist_badread(offset, size, secure); } } #define TRACE_GICV3_DIST_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_DIST_WRITE) || \ false) static inline void _nocheck__trace_gicv3_dist_write(uint64_t offset, uint64_t data, unsigned size, bool secure) { if (trace_event_get_state(TRACE_GICV3_DIST_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 177 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_dist_write " "GICv3 distributor write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size, secure); #line 5352 "trace/trace-hw_intc.h" } else { #line 177 "../hw/intc/trace-events" qemu_log("gicv3_dist_write " "GICv3 distributor write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", offset, data, size, secure); #line 5356 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_dist_write(uint64_t offset, uint64_t data, unsigned size, bool secure) { if (true) { _nocheck__trace_gicv3_dist_write(offset, data, size, secure); } } #define TRACE_GICV3_DIST_BADWRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_DIST_BADWRITE) || \ false) static inline void _nocheck__trace_gicv3_dist_badwrite(uint64_t offset, uint64_t data, unsigned size, bool secure) { if (trace_event_get_state(TRACE_GICV3_DIST_BADWRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 178 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_dist_badwrite " "GICv3 distributor write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d: error" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size, secure); #line 5383 "trace/trace-hw_intc.h" } else { #line 178 "../hw/intc/trace-events" qemu_log("gicv3_dist_badwrite " "GICv3 distributor write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d: error" "\n", offset, data, size, secure); #line 5387 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_dist_badwrite(uint64_t offset, uint64_t data, unsigned size, bool secure) { if (true) { _nocheck__trace_gicv3_dist_badwrite(offset, data, size, secure); } } #define TRACE_GICV3_DIST_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_DIST_SET_IRQ) || \ false) static inline void _nocheck__trace_gicv3_dist_set_irq(int irq, int level) { if (trace_event_get_state(TRACE_GICV3_DIST_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 179 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_dist_set_irq " "GICv3 distributor interrupt %d level changed to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 5414 "trace/trace-hw_intc.h" } else { #line 179 "../hw/intc/trace-events" qemu_log("gicv3_dist_set_irq " "GICv3 distributor interrupt %d level changed to %d" "\n", irq, level); #line 5418 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_dist_set_irq(int irq, int level) { if (true) { _nocheck__trace_gicv3_dist_set_irq(irq, level); } } #define TRACE_GICV3_REDIST_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_READ) || \ false) static inline void _nocheck__trace_gicv3_redist_read(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) { if (trace_event_get_state(TRACE_GICV3_REDIST_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 182 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_redist_read " "GICv3 redistributor 0x%x read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, offset, data, size, secure); #line 5445 "trace/trace-hw_intc.h" } else { #line 182 "../hw/intc/trace-events" qemu_log("gicv3_redist_read " "GICv3 redistributor 0x%x read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", cpu, offset, data, size, secure); #line 5449 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_redist_read(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) { if (true) { _nocheck__trace_gicv3_redist_read(cpu, offset, data, size, secure); } } #define TRACE_GICV3_REDIST_BADREAD_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_BADREAD) || \ false) static inline void _nocheck__trace_gicv3_redist_badread(uint32_t cpu, uint64_t offset, unsigned size, bool secure) { if (trace_event_get_state(TRACE_GICV3_REDIST_BADREAD) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 183 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_redist_badread " "GICv3 redistributor 0x%x read: offset 0x%" PRIx64 " size %u secure %d: error" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, offset, size, secure); #line 5476 "trace/trace-hw_intc.h" } else { #line 183 "../hw/intc/trace-events" qemu_log("gicv3_redist_badread " "GICv3 redistributor 0x%x read: offset 0x%" PRIx64 " size %u secure %d: error" "\n", cpu, offset, size, secure); #line 5480 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_redist_badread(uint32_t cpu, uint64_t offset, unsigned size, bool secure) { if (true) { _nocheck__trace_gicv3_redist_badread(cpu, offset, size, secure); } } #define TRACE_GICV3_REDIST_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_WRITE) || \ false) static inline void _nocheck__trace_gicv3_redist_write(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) { if (trace_event_get_state(TRACE_GICV3_REDIST_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 184 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_redist_write " "GICv3 redistributor 0x%x write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, offset, data, size, secure); #line 5507 "trace/trace-hw_intc.h" } else { #line 184 "../hw/intc/trace-events" qemu_log("gicv3_redist_write " "GICv3 redistributor 0x%x write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", cpu, offset, data, size, secure); #line 5511 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_redist_write(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) { if (true) { _nocheck__trace_gicv3_redist_write(cpu, offset, data, size, secure); } } #define TRACE_GICV3_REDIST_BADWRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_BADWRITE) || \ false) static inline void _nocheck__trace_gicv3_redist_badwrite(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) { if (trace_event_get_state(TRACE_GICV3_REDIST_BADWRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 185 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_redist_badwrite " "GICv3 redistributor 0x%x write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d: error" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, offset, data, size, secure); #line 5538 "trace/trace-hw_intc.h" } else { #line 185 "../hw/intc/trace-events" qemu_log("gicv3_redist_badwrite " "GICv3 redistributor 0x%x write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d: error" "\n", cpu, offset, data, size, secure); #line 5542 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_redist_badwrite(uint32_t cpu, uint64_t offset, uint64_t data, unsigned size, bool secure) { if (true) { _nocheck__trace_gicv3_redist_badwrite(cpu, offset, data, size, secure); } } #define TRACE_GICV3_REDIST_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_SET_IRQ) || \ false) static inline void _nocheck__trace_gicv3_redist_set_irq(uint32_t cpu, int irq, int level) { if (trace_event_get_state(TRACE_GICV3_REDIST_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 186 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_redist_set_irq " "GICv3 redistributor 0x%x interrupt %d level changed to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, irq, level); #line 5569 "trace/trace-hw_intc.h" } else { #line 186 "../hw/intc/trace-events" qemu_log("gicv3_redist_set_irq " "GICv3 redistributor 0x%x interrupt %d level changed to %d" "\n", cpu, irq, level); #line 5573 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_redist_set_irq(uint32_t cpu, int irq, int level) { if (true) { _nocheck__trace_gicv3_redist_set_irq(cpu, irq, level); } } #define TRACE_GICV3_REDIST_SEND_SGI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_REDIST_SEND_SGI) || \ false) static inline void _nocheck__trace_gicv3_redist_send_sgi(uint32_t cpu, int irq) { if (trace_event_get_state(TRACE_GICV3_REDIST_SEND_SGI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 187 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_redist_send_sgi " "GICv3 redistributor 0x%x pending SGI %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu, irq); #line 5600 "trace/trace-hw_intc.h" } else { #line 187 "../hw/intc/trace-events" qemu_log("gicv3_redist_send_sgi " "GICv3 redistributor 0x%x pending SGI %d" "\n", cpu, irq); #line 5604 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_redist_send_sgi(uint32_t cpu, int irq) { if (true) { _nocheck__trace_gicv3_redist_send_sgi(cpu, irq); } } #define TRACE_GICV3_ITS_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_READ) || \ false) static inline void _nocheck__trace_gicv3_its_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_GICV3_ITS_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 190 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_read " "GICv3 ITS read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 5631 "trace/trace-hw_intc.h" } else { #line 190 "../hw/intc/trace-events" qemu_log("gicv3_its_read " "GICv3 ITS read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 5635 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_gicv3_its_read(offset, data, size); } } #define TRACE_GICV3_ITS_BADREAD_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_BADREAD) || \ false) static inline void _nocheck__trace_gicv3_its_badread(uint64_t offset, unsigned size) { if (trace_event_get_state(TRACE_GICV3_ITS_BADREAD) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 191 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_badread " "GICv3 ITS read: offset 0x%" PRIx64 " size %u: error" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size); #line 5662 "trace/trace-hw_intc.h" } else { #line 191 "../hw/intc/trace-events" qemu_log("gicv3_its_badread " "GICv3 ITS read: offset 0x%" PRIx64 " size %u: error" "\n", offset, size); #line 5666 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_badread(uint64_t offset, unsigned size) { if (true) { _nocheck__trace_gicv3_its_badread(offset, size); } } #define TRACE_GICV3_ITS_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_WRITE) || \ false) static inline void _nocheck__trace_gicv3_its_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_GICV3_ITS_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 192 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_write " "GICv3 ITS write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 5693 "trace/trace-hw_intc.h" } else { #line 192 "../hw/intc/trace-events" qemu_log("gicv3_its_write " "GICv3 ITS write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 5697 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_gicv3_its_write(offset, data, size); } } #define TRACE_GICV3_ITS_BADWRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_BADWRITE) || \ false) static inline void _nocheck__trace_gicv3_its_badwrite(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_GICV3_ITS_BADWRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 193 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_badwrite " "GICv3 ITS write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u: error" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 5724 "trace/trace-hw_intc.h" } else { #line 193 "../hw/intc/trace-events" qemu_log("gicv3_its_badwrite " "GICv3 ITS write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u: error" "\n", offset, data, size); #line 5728 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_badwrite(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_gicv3_its_badwrite(offset, data, size); } } #define TRACE_GICV3_ITS_TRANSLATION_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_TRANSLATION_WRITE) || \ false) static inline void _nocheck__trace_gicv3_its_translation_write(uint64_t offset, uint64_t data, unsigned size, uint32_t requester_id) { if (trace_event_get_state(TRACE_GICV3_ITS_TRANSLATION_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 194 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_translation_write " "GICv3 ITS TRANSLATER write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u requester_id 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size, requester_id); #line 5755 "trace/trace-hw_intc.h" } else { #line 194 "../hw/intc/trace-events" qemu_log("gicv3_its_translation_write " "GICv3 ITS TRANSLATER write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u requester_id 0x%x" "\n", offset, data, size, requester_id); #line 5759 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_translation_write(uint64_t offset, uint64_t data, unsigned size, uint32_t requester_id) { if (true) { _nocheck__trace_gicv3_its_translation_write(offset, data, size, requester_id); } } #define TRACE_GICV3_ITS_PROCESS_COMMAND_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_PROCESS_COMMAND) || \ false) static inline void _nocheck__trace_gicv3_its_process_command(uint32_t rd_offset, uint8_t cmd) { if (trace_event_get_state(TRACE_GICV3_ITS_PROCESS_COMMAND) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 195 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_process_command " "GICv3 ITS: processing command at offset 0x%x: 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , rd_offset, cmd); #line 5786 "trace/trace-hw_intc.h" } else { #line 195 "../hw/intc/trace-events" qemu_log("gicv3_its_process_command " "GICv3 ITS: processing command at offset 0x%x: 0x%x" "\n", rd_offset, cmd); #line 5790 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_process_command(uint32_t rd_offset, uint8_t cmd) { if (true) { _nocheck__trace_gicv3_its_process_command(rd_offset, cmd); } } #define TRACE_GICV3_ITS_CMD_INT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_INT) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_int(uint32_t devid, uint32_t eventid) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_INT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 196 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_int " "GICv3 ITS: command INT DeviceID 0x%x EventID 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, eventid); #line 5817 "trace/trace-hw_intc.h" } else { #line 196 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_int " "GICv3 ITS: command INT DeviceID 0x%x EventID 0x%x" "\n", devid, eventid); #line 5821 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_int(uint32_t devid, uint32_t eventid) { if (true) { _nocheck__trace_gicv3_its_cmd_int(devid, eventid); } } #define TRACE_GICV3_ITS_CMD_CLEAR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_CLEAR) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_clear(uint32_t devid, uint32_t eventid) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_CLEAR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 197 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_clear " "GICv3 ITS: command CLEAR DeviceID 0x%x EventID 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, eventid); #line 5848 "trace/trace-hw_intc.h" } else { #line 197 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_clear " "GICv3 ITS: command CLEAR DeviceID 0x%x EventID 0x%x" "\n", devid, eventid); #line 5852 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_clear(uint32_t devid, uint32_t eventid) { if (true) { _nocheck__trace_gicv3_its_cmd_clear(devid, eventid); } } #define TRACE_GICV3_ITS_CMD_DISCARD_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_DISCARD) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_discard(uint32_t devid, uint32_t eventid) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_DISCARD) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 198 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_discard " "GICv3 ITS: command DISCARD DeviceID 0x%x EventID 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, eventid); #line 5879 "trace/trace-hw_intc.h" } else { #line 198 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_discard " "GICv3 ITS: command DISCARD DeviceID 0x%x EventID 0x%x" "\n", devid, eventid); #line 5883 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_discard(uint32_t devid, uint32_t eventid) { if (true) { _nocheck__trace_gicv3_its_cmd_discard(devid, eventid); } } #define TRACE_GICV3_ITS_CMD_SYNC_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_SYNC) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_sync(void) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_SYNC) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 199 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_sync " "GICv3 ITS: command SYNC" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 5910 "trace/trace-hw_intc.h" } else { #line 199 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_sync " "GICv3 ITS: command SYNC" "\n"); #line 5914 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_sync(void) { if (true) { _nocheck__trace_gicv3_its_cmd_sync(); } } #define TRACE_GICV3_ITS_CMD_MAPD_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MAPD) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_mapd(uint32_t devid, uint32_t size, uint64_t ittaddr, int valid) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MAPD) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 200 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_mapd " "GICv3 ITS: command MAPD DeviceID 0x%x Size 0x%x ITT_addr 0x%" PRIx64 " V %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, size, ittaddr, valid); #line 5941 "trace/trace-hw_intc.h" } else { #line 200 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_mapd " "GICv3 ITS: command MAPD DeviceID 0x%x Size 0x%x ITT_addr 0x%" PRIx64 " V %d" "\n", devid, size, ittaddr, valid); #line 5945 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_mapd(uint32_t devid, uint32_t size, uint64_t ittaddr, int valid) { if (true) { _nocheck__trace_gicv3_its_cmd_mapd(devid, size, ittaddr, valid); } } #define TRACE_GICV3_ITS_CMD_MAPC_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MAPC) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_mapc(uint32_t icid, uint64_t rdbase, int valid) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MAPC) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 201 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_mapc " "GICv3 ITS: command MAPC ICID 0x%x RDbase 0x%" PRIx64 " V %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , icid, rdbase, valid); #line 5972 "trace/trace-hw_intc.h" } else { #line 201 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_mapc " "GICv3 ITS: command MAPC ICID 0x%x RDbase 0x%" PRIx64 " V %d" "\n", icid, rdbase, valid); #line 5976 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_mapc(uint32_t icid, uint64_t rdbase, int valid) { if (true) { _nocheck__trace_gicv3_its_cmd_mapc(icid, rdbase, valid); } } #define TRACE_GICV3_ITS_CMD_MAPI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MAPI) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_mapi(uint32_t devid, uint32_t eventid, uint32_t icid) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MAPI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 202 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_mapi " "GICv3 ITS: command MAPI DeviceID 0x%x EventID 0x%x ICID 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, eventid, icid); #line 6003 "trace/trace-hw_intc.h" } else { #line 202 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_mapi " "GICv3 ITS: command MAPI DeviceID 0x%x EventID 0x%x ICID 0x%x" "\n", devid, eventid, icid); #line 6007 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_mapi(uint32_t devid, uint32_t eventid, uint32_t icid) { if (true) { _nocheck__trace_gicv3_its_cmd_mapi(devid, eventid, icid); } } #define TRACE_GICV3_ITS_CMD_MAPTI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MAPTI) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_mapti(uint32_t devid, uint32_t eventid, uint32_t icid, uint32_t intid) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MAPTI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 203 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_mapti " "GICv3 ITS: command MAPTI DeviceID 0x%x EventID 0x%x ICID 0x%x pINTID 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, eventid, icid, intid); #line 6034 "trace/trace-hw_intc.h" } else { #line 203 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_mapti " "GICv3 ITS: command MAPTI DeviceID 0x%x EventID 0x%x ICID 0x%x pINTID 0x%x" "\n", devid, eventid, icid, intid); #line 6038 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_mapti(uint32_t devid, uint32_t eventid, uint32_t icid, uint32_t intid) { if (true) { _nocheck__trace_gicv3_its_cmd_mapti(devid, eventid, icid, intid); } } #define TRACE_GICV3_ITS_CMD_INV_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_INV) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_inv(uint32_t devid, uint32_t eventid) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_INV) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 204 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_inv " "GICv3 ITS: command INV DeviceID 0x%x EventID 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, eventid); #line 6065 "trace/trace-hw_intc.h" } else { #line 204 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_inv " "GICv3 ITS: command INV DeviceID 0x%x EventID 0x%x" "\n", devid, eventid); #line 6069 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_inv(uint32_t devid, uint32_t eventid) { if (true) { _nocheck__trace_gicv3_its_cmd_inv(devid, eventid); } } #define TRACE_GICV3_ITS_CMD_INVALL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_INVALL) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_invall(void) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_INVALL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 205 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_invall " "GICv3 ITS: command INVALL" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 6096 "trace/trace-hw_intc.h" } else { #line 205 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_invall " "GICv3 ITS: command INVALL" "\n"); #line 6100 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_invall(void) { if (true) { _nocheck__trace_gicv3_its_cmd_invall(); } } #define TRACE_GICV3_ITS_CMD_MOVALL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MOVALL) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MOVALL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 206 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_movall " "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " RDbase2 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , rd1, rd2); #line 6127 "trace/trace-hw_intc.h" } else { #line 206 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_movall " "GICv3 ITS: command MOVALL RDbase1 0x%" PRIx64 " RDbase2 0x%" PRIx64 "\n", rd1, rd2); #line 6131 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_movall(uint64_t rd1, uint64_t rd2) { if (true) { _nocheck__trace_gicv3_its_cmd_movall(rd1, rd2); } } #define TRACE_GICV3_ITS_CMD_MOVI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_MOVI) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_MOVI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 207 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_movi " "GICv3 ITS: command MOVI DeviceID 0x%x EventID 0x%x ICID 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, eventid, icid); #line 6158 "trace/trace-hw_intc.h" } else { #line 207 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_movi " "GICv3 ITS: command MOVI DeviceID 0x%x EventID 0x%x ICID 0x%x" "\n", devid, eventid, icid); #line 6162 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_movi(uint32_t devid, uint32_t eventid, uint32_t icid) { if (true) { _nocheck__trace_gicv3_its_cmd_movi(devid, eventid, icid); } } #define TRACE_GICV3_ITS_CMD_VMAPI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VMAPI) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_vmapi(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t doorbell) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VMAPI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 208 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_vmapi " "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x Dbell_pINTID 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, eventid, vpeid, doorbell); #line 6189 "trace/trace-hw_intc.h" } else { #line 208 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_vmapi " "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x Dbell_pINTID 0x%x" "\n", devid, eventid, vpeid, doorbell); #line 6193 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_vmapi(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t doorbell) { if (true) { _nocheck__trace_gicv3_its_cmd_vmapi(devid, eventid, vpeid, doorbell); } } #define TRACE_GICV3_ITS_CMD_VMAPTI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VMAPTI) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_vmapti(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t vintid, uint32_t doorbell) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VMAPTI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 209 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_vmapti " "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x vINTID 0x%x Dbell_pINTID 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, eventid, vpeid, vintid, doorbell); #line 6220 "trace/trace-hw_intc.h" } else { #line 209 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_vmapti " "GICv3 ITS: command VMAPI DeviceID 0x%x EventID 0x%x vPEID 0x%x vINTID 0x%x Dbell_pINTID 0x%x" "\n", devid, eventid, vpeid, vintid, doorbell); #line 6224 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_vmapti(uint32_t devid, uint32_t eventid, uint32_t vpeid, uint32_t vintid, uint32_t doorbell) { if (true) { _nocheck__trace_gicv3_its_cmd_vmapti(devid, eventid, vpeid, vintid, doorbell); } } #define TRACE_GICV3_ITS_CMD_VMAPP_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VMAPP) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_vmapp(uint32_t vpeid, uint64_t rdbase, int valid, uint64_t vptaddr, uint32_t vptsize) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VMAPP) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 210 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_vmapp " "GICv3 ITS: command VMAPP vPEID 0x%x RDbase 0x%" PRIx64 " V %d VPT_addr 0x%" PRIx64 " VPT_size 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vpeid, rdbase, valid, vptaddr, vptsize); #line 6251 "trace/trace-hw_intc.h" } else { #line 210 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_vmapp " "GICv3 ITS: command VMAPP vPEID 0x%x RDbase 0x%" PRIx64 " V %d VPT_addr 0x%" PRIx64 " VPT_size 0x%x" "\n", vpeid, rdbase, valid, vptaddr, vptsize); #line 6255 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_vmapp(uint32_t vpeid, uint64_t rdbase, int valid, uint64_t vptaddr, uint32_t vptsize) { if (true) { _nocheck__trace_gicv3_its_cmd_vmapp(vpeid, rdbase, valid, vptaddr, vptsize); } } #define TRACE_GICV3_ITS_CMD_VMOVP_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VMOVP) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_vmovp(uint32_t vpeid, uint64_t rdbase) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VMOVP) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 211 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_vmovp " "GICv3 ITS: command VMOVP vPEID 0x%x RDbase 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vpeid, rdbase); #line 6282 "trace/trace-hw_intc.h" } else { #line 211 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_vmovp " "GICv3 ITS: command VMOVP vPEID 0x%x RDbase 0x%" PRIx64 "\n", vpeid, rdbase); #line 6286 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_vmovp(uint32_t vpeid, uint64_t rdbase) { if (true) { _nocheck__trace_gicv3_its_cmd_vmovp(vpeid, rdbase); } } #define TRACE_GICV3_ITS_CMD_VSYNC_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VSYNC) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_vsync(void) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VSYNC) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 212 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_vsync " "GICv3 ITS: command VSYNC" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 6313 "trace/trace-hw_intc.h" } else { #line 212 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_vsync " "GICv3 ITS: command VSYNC" "\n"); #line 6317 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_vsync(void) { if (true) { _nocheck__trace_gicv3_its_cmd_vsync(); } } #define TRACE_GICV3_ITS_CMD_VMOVI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VMOVI) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_vmovi(uint32_t devid, uint32_t eventid, uint32_t vpeid, int dbvalid, uint32_t doorbell) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VMOVI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 213 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_vmovi " "GICv3 ITS: command VMOVI DeviceID 0x%x EventID 0x%x vPEID 0x%x D %d Dbell_pINTID 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, eventid, vpeid, dbvalid, doorbell); #line 6344 "trace/trace-hw_intc.h" } else { #line 213 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_vmovi " "GICv3 ITS: command VMOVI DeviceID 0x%x EventID 0x%x vPEID 0x%x D %d Dbell_pINTID 0x%x" "\n", devid, eventid, vpeid, dbvalid, doorbell); #line 6348 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_vmovi(uint32_t devid, uint32_t eventid, uint32_t vpeid, int dbvalid, uint32_t doorbell) { if (true) { _nocheck__trace_gicv3_its_cmd_vmovi(devid, eventid, vpeid, dbvalid, doorbell); } } #define TRACE_GICV3_ITS_CMD_VINVALL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_VINVALL) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_vinvall(uint32_t vpeid) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_VINVALL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 214 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_vinvall " "GICv3 ITS: command VINVALL vPEID 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vpeid); #line 6375 "trace/trace-hw_intc.h" } else { #line 214 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_vinvall " "GICv3 ITS: command VINVALL vPEID 0x%x" "\n", vpeid); #line 6379 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_vinvall(uint32_t vpeid) { if (true) { _nocheck__trace_gicv3_its_cmd_vinvall(vpeid); } } #define TRACE_GICV3_ITS_CMD_UNKNOWN_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CMD_UNKNOWN) || \ false) static inline void _nocheck__trace_gicv3_its_cmd_unknown(unsigned cmd) { if (trace_event_get_state(TRACE_GICV3_ITS_CMD_UNKNOWN) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 215 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cmd_unknown " "GICv3 ITS: unknown command 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cmd); #line 6406 "trace/trace-hw_intc.h" } else { #line 215 "../hw/intc/trace-events" qemu_log("gicv3_its_cmd_unknown " "GICv3 ITS: unknown command 0x%x" "\n", cmd); #line 6410 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cmd_unknown(unsigned cmd) { if (true) { _nocheck__trace_gicv3_its_cmd_unknown(cmd); } } #define TRACE_GICV3_ITS_CTE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CTE_READ) || \ false) static inline void _nocheck__trace_gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) { if (trace_event_get_state(TRACE_GICV3_ITS_CTE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 216 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cte_read " "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , icid, valid, rdbase); #line 6437 "trace/trace-hw_intc.h" } else { #line 216 "../hw/intc/trace-events" qemu_log("gicv3_its_cte_read " "GICv3 ITS: Collection Table read for ICID 0x%x: valid %d RDBase 0x%x" "\n", icid, valid, rdbase); #line 6441 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cte_read(uint32_t icid, int valid, uint32_t rdbase) { if (true) { _nocheck__trace_gicv3_its_cte_read(icid, valid, rdbase); } } #define TRACE_GICV3_ITS_CTE_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CTE_WRITE) || \ false) static inline void _nocheck__trace_gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) { if (trace_event_get_state(TRACE_GICV3_ITS_CTE_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 217 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cte_write " "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , icid, valid, rdbase); #line 6468 "trace/trace-hw_intc.h" } else { #line 217 "../hw/intc/trace-events" qemu_log("gicv3_its_cte_write " "GICv3 ITS: Collection Table write for ICID 0x%x: valid %d RDBase 0x%x" "\n", icid, valid, rdbase); #line 6472 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cte_write(uint32_t icid, int valid, uint32_t rdbase) { if (true) { _nocheck__trace_gicv3_its_cte_write(icid, valid, rdbase); } } #define TRACE_GICV3_ITS_CTE_READ_FAULT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_CTE_READ_FAULT) || \ false) static inline void _nocheck__trace_gicv3_its_cte_read_fault(uint32_t icid) { if (trace_event_get_state(TRACE_GICV3_ITS_CTE_READ_FAULT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 218 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_cte_read_fault " "GICv3 ITS: Collection Table read for ICID 0x%x: faulted" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , icid); #line 6499 "trace/trace-hw_intc.h" } else { #line 218 "../hw/intc/trace-events" qemu_log("gicv3_its_cte_read_fault " "GICv3 ITS: Collection Table read for ICID 0x%x: faulted" "\n", icid); #line 6503 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_cte_read_fault(uint32_t icid) { if (true) { _nocheck__trace_gicv3_its_cte_read_fault(icid); } } #define TRACE_GICV3_ITS_ITE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_ITE_READ) || \ false) static inline void _nocheck__trace_gicv3_its_ite_read(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell) { if (trace_event_get_state(TRACE_GICV3_ITS_ITE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 219 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_ite_read " "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ittaddr, eventid, valid, inttype, intid, icid, vpeid, doorbell); #line 6530 "trace/trace-hw_intc.h" } else { #line 219 "../hw/intc/trace-events" qemu_log("gicv3_its_ite_read " "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x" "\n", ittaddr, eventid, valid, inttype, intid, icid, vpeid, doorbell); #line 6534 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_ite_read(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell) { if (true) { _nocheck__trace_gicv3_its_ite_read(ittaddr, eventid, valid, inttype, intid, icid, vpeid, doorbell); } } #define TRACE_GICV3_ITS_ITE_READ_FAULT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_ITE_READ_FAULT) || \ false) static inline void _nocheck__trace_gicv3_its_ite_read_fault(uint64_t ittaddr, uint32_t eventid) { if (trace_event_get_state(TRACE_GICV3_ITS_ITE_READ_FAULT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 220 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_ite_read_fault " "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: faulted" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ittaddr, eventid); #line 6561 "trace/trace-hw_intc.h" } else { #line 220 "../hw/intc/trace-events" qemu_log("gicv3_its_ite_read_fault " "GICv3 ITS: Interrupt Table read for ITTaddr 0x%" PRIx64 " EventID 0x%x: faulted" "\n", ittaddr, eventid); #line 6565 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_ite_read_fault(uint64_t ittaddr, uint32_t eventid) { if (true) { _nocheck__trace_gicv3_its_ite_read_fault(ittaddr, eventid); } } #define TRACE_GICV3_ITS_ITE_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_ITE_WRITE) || \ false) static inline void _nocheck__trace_gicv3_its_ite_write(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell) { if (trace_event_get_state(TRACE_GICV3_ITS_ITE_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 221 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_ite_write " "GICv3 ITS: Interrupt Table write for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ittaddr, eventid, valid, inttype, intid, icid, vpeid, doorbell); #line 6592 "trace/trace-hw_intc.h" } else { #line 221 "../hw/intc/trace-events" qemu_log("gicv3_its_ite_write " "GICv3 ITS: Interrupt Table write for ITTaddr 0x%" PRIx64 " EventID 0x%x: valid %d inttype %d intid 0x%x ICID 0x%x vPEID 0x%x doorbell 0x%x" "\n", ittaddr, eventid, valid, inttype, intid, icid, vpeid, doorbell); #line 6596 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_ite_write(uint64_t ittaddr, uint32_t eventid, int valid, int inttype, uint32_t intid, uint32_t icid, uint32_t vpeid, uint32_t doorbell) { if (true) { _nocheck__trace_gicv3_its_ite_write(ittaddr, eventid, valid, inttype, intid, icid, vpeid, doorbell); } } #define TRACE_GICV3_ITS_DTE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_DTE_READ) || \ false) static inline void _nocheck__trace_gicv3_its_dte_read(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) { if (trace_event_get_state(TRACE_GICV3_ITS_DTE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 222 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_dte_read " "GICv3 ITS: Device Table read for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, valid, size, ittaddr); #line 6623 "trace/trace-hw_intc.h" } else { #line 222 "../hw/intc/trace-events" qemu_log("gicv3_its_dte_read " "GICv3 ITS: Device Table read for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 "\n", devid, valid, size, ittaddr); #line 6627 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_dte_read(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) { if (true) { _nocheck__trace_gicv3_its_dte_read(devid, valid, size, ittaddr); } } #define TRACE_GICV3_ITS_DTE_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_DTE_WRITE) || \ false) static inline void _nocheck__trace_gicv3_its_dte_write(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) { if (trace_event_get_state(TRACE_GICV3_ITS_DTE_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 223 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_dte_write " "GICv3 ITS: Device Table write for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid, valid, size, ittaddr); #line 6654 "trace/trace-hw_intc.h" } else { #line 223 "../hw/intc/trace-events" qemu_log("gicv3_its_dte_write " "GICv3 ITS: Device Table write for DeviceID 0x%x: valid %d size 0x%x ITTaddr 0x%" PRIx64 "\n", devid, valid, size, ittaddr); #line 6658 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_dte_write(uint32_t devid, int valid, uint32_t size, uint64_t ittaddr) { if (true) { _nocheck__trace_gicv3_its_dte_write(devid, valid, size, ittaddr); } } #define TRACE_GICV3_ITS_DTE_READ_FAULT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_DTE_READ_FAULT) || \ false) static inline void _nocheck__trace_gicv3_its_dte_read_fault(uint32_t devid) { if (trace_event_get_state(TRACE_GICV3_ITS_DTE_READ_FAULT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 224 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_dte_read_fault " "GICv3 ITS: Device Table read for DeviceID 0x%x: faulted" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , devid); #line 6685 "trace/trace-hw_intc.h" } else { #line 224 "../hw/intc/trace-events" qemu_log("gicv3_its_dte_read_fault " "GICv3 ITS: Device Table read for DeviceID 0x%x: faulted" "\n", devid); #line 6689 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_dte_read_fault(uint32_t devid) { if (true) { _nocheck__trace_gicv3_its_dte_read_fault(devid); } } #define TRACE_GICV3_ITS_VTE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_VTE_READ) || \ false) static inline void _nocheck__trace_gicv3_its_vte_read(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t vptaddr, uint32_t rdbase) { if (trace_event_get_state(TRACE_GICV3_ITS_VTE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 225 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_vte_read " "GICv3 ITS: vPE Table read for vPEID 0x%x: valid %d VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vpeid, valid, vptsize, vptaddr, rdbase); #line 6716 "trace/trace-hw_intc.h" } else { #line 225 "../hw/intc/trace-events" qemu_log("gicv3_its_vte_read " "GICv3 ITS: vPE Table read for vPEID 0x%x: valid %d VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x" "\n", vpeid, valid, vptsize, vptaddr, rdbase); #line 6720 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_vte_read(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t vptaddr, uint32_t rdbase) { if (true) { _nocheck__trace_gicv3_its_vte_read(vpeid, valid, vptsize, vptaddr, rdbase); } } #define TRACE_GICV3_ITS_VTE_READ_FAULT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_VTE_READ_FAULT) || \ false) static inline void _nocheck__trace_gicv3_its_vte_read_fault(uint32_t vpeid) { if (trace_event_get_state(TRACE_GICV3_ITS_VTE_READ_FAULT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 226 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_vte_read_fault " "GICv3 ITS: vPE Table read for vPEID 0x%x: faulted" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vpeid); #line 6747 "trace/trace-hw_intc.h" } else { #line 226 "../hw/intc/trace-events" qemu_log("gicv3_its_vte_read_fault " "GICv3 ITS: vPE Table read for vPEID 0x%x: faulted" "\n", vpeid); #line 6751 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_vte_read_fault(uint32_t vpeid) { if (true) { _nocheck__trace_gicv3_its_vte_read_fault(vpeid); } } #define TRACE_GICV3_ITS_VTE_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GICV3_ITS_VTE_WRITE) || \ false) static inline void _nocheck__trace_gicv3_its_vte_write(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t vptaddr, uint32_t rdbase) { if (trace_event_get_state(TRACE_GICV3_ITS_VTE_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 227 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:gicv3_its_vte_write " "GICv3 ITS: vPE Table write for vPEID 0x%x: valid %d VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vpeid, valid, vptsize, vptaddr, rdbase); #line 6778 "trace/trace-hw_intc.h" } else { #line 227 "../hw/intc/trace-events" qemu_log("gicv3_its_vte_write " "GICv3 ITS: vPE Table write for vPEID 0x%x: valid %d VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x" "\n", vpeid, valid, vptsize, vptaddr, rdbase); #line 6782 "trace/trace-hw_intc.h" } } } static inline void trace_gicv3_its_vte_write(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t vptaddr, uint32_t rdbase) { if (true) { _nocheck__trace_gicv3_its_vte_write(vpeid, valid, vptsize, vptaddr, rdbase); } } #define TRACE_NVIC_RECOMPUTE_STATE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_RECOMPUTE_STATE) || \ false) static inline void _nocheck__trace_nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) { if (trace_event_get_state(TRACE_NVIC_RECOMPUTE_STATE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 230 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_recompute_state " "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vectpending, vectpending_prio, exception_prio); #line 6809 "trace/trace-hw_intc.h" } else { #line 230 "../hw/intc/trace-events" qemu_log("nvic_recompute_state " "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d" "\n", vectpending, vectpending_prio, exception_prio); #line 6813 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) { if (true) { _nocheck__trace_nvic_recompute_state(vectpending, vectpending_prio, exception_prio); } } #define TRACE_NVIC_RECOMPUTE_STATE_SECURE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_RECOMPUTE_STATE_SECURE) || \ false) static inline void _nocheck__trace_nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) { if (trace_event_get_state(TRACE_NVIC_RECOMPUTE_STATE_SECURE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 231 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_recompute_state_secure " "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vectpending, vectpending_is_s_banked, vectpending_prio, exception_prio); #line 6840 "trace/trace-hw_intc.h" } else { #line 231 "../hw/intc/trace-events" qemu_log("nvic_recompute_state_secure " "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d" "\n", vectpending, vectpending_is_s_banked, vectpending_prio, exception_prio); #line 6844 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) { if (true) { _nocheck__trace_nvic_recompute_state_secure(vectpending, vectpending_is_s_banked, vectpending_prio, exception_prio); } } #define TRACE_NVIC_SET_PRIO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_SET_PRIO) || \ false) static inline void _nocheck__trace_nvic_set_prio(int irq, bool secure, uint8_t prio) { if (trace_event_get_state(TRACE_NVIC_SET_PRIO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 232 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_set_prio " "NVIC set irq %d secure-bank %d priority %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, secure, prio); #line 6871 "trace/trace-hw_intc.h" } else { #line 232 "../hw/intc/trace-events" qemu_log("nvic_set_prio " "NVIC set irq %d secure-bank %d priority %d" "\n", irq, secure, prio); #line 6875 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_set_prio(int irq, bool secure, uint8_t prio) { if (true) { _nocheck__trace_nvic_set_prio(irq, secure, prio); } } #define TRACE_NVIC_IRQ_UPDATE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_IRQ_UPDATE) || \ false) static inline void _nocheck__trace_nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) { if (trace_event_get_state(TRACE_NVIC_IRQ_UPDATE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 233 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_irq_update " "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , vectpending, pendprio, exception_prio, level); #line 6902 "trace/trace-hw_intc.h" } else { #line 233 "../hw/intc/trace-events" qemu_log("nvic_irq_update " "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d" "\n", vectpending, pendprio, exception_prio, level); #line 6906 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) { if (true) { _nocheck__trace_nvic_irq_update(vectpending, pendprio, exception_prio, level); } } #define TRACE_NVIC_ESCALATE_PRIO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_ESCALATE_PRIO) || \ false) static inline void _nocheck__trace_nvic_escalate_prio(int irq, int irqprio, int runprio) { if (trace_event_get_state(TRACE_NVIC_ESCALATE_PRIO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 234 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_escalate_prio " "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, irqprio, runprio); #line 6933 "trace/trace-hw_intc.h" } else { #line 234 "../hw/intc/trace-events" qemu_log("nvic_escalate_prio " "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d" "\n", irq, irqprio, runprio); #line 6937 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_escalate_prio(int irq, int irqprio, int runprio) { if (true) { _nocheck__trace_nvic_escalate_prio(irq, irqprio, runprio); } } #define TRACE_NVIC_ESCALATE_DISABLED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_ESCALATE_DISABLED) || \ false) static inline void _nocheck__trace_nvic_escalate_disabled(int irq) { if (trace_event_get_state(TRACE_NVIC_ESCALATE_DISABLED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 235 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_escalate_disabled " "NVIC escalating irq %d to HardFault: disabled" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq); #line 6964 "trace/trace-hw_intc.h" } else { #line 235 "../hw/intc/trace-events" qemu_log("nvic_escalate_disabled " "NVIC escalating irq %d to HardFault: disabled" "\n", irq); #line 6968 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_escalate_disabled(int irq) { if (true) { _nocheck__trace_nvic_escalate_disabled(irq); } } #define TRACE_NVIC_SET_PENDING_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_SET_PENDING) || \ false) static inline void _nocheck__trace_nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, int en, int prio) { if (trace_event_get_state(TRACE_NVIC_SET_PENDING) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 236 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_set_pending " "NVIC set pending irq %d secure-bank %d targets_secure %d derived %d (enabled: %d priority %d)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, secure, targets_secure, derived, en, prio); #line 6995 "trace/trace-hw_intc.h" } else { #line 236 "../hw/intc/trace-events" qemu_log("nvic_set_pending " "NVIC set pending irq %d secure-bank %d targets_secure %d derived %d (enabled: %d priority %d)" "\n", irq, secure, targets_secure, derived, en, prio); #line 6999 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, int en, int prio) { if (true) { _nocheck__trace_nvic_set_pending(irq, secure, targets_secure, derived, en, prio); } } #define TRACE_NVIC_CLEAR_PENDING_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_CLEAR_PENDING) || \ false) static inline void _nocheck__trace_nvic_clear_pending(int irq, bool secure, int en, int prio) { if (trace_event_get_state(TRACE_NVIC_CLEAR_PENDING) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 237 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_clear_pending " "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, secure, en, prio); #line 7026 "trace/trace-hw_intc.h" } else { #line 237 "../hw/intc/trace-events" qemu_log("nvic_clear_pending " "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)" "\n", irq, secure, en, prio); #line 7030 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_clear_pending(int irq, bool secure, int en, int prio) { if (true) { _nocheck__trace_nvic_clear_pending(irq, secure, en, prio); } } #define TRACE_NVIC_ACKNOWLEDGE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_ACKNOWLEDGE_IRQ) || \ false) static inline void _nocheck__trace_nvic_acknowledge_irq(int irq, int prio) { if (trace_event_get_state(TRACE_NVIC_ACKNOWLEDGE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 238 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_acknowledge_irq " "NVIC acknowledge IRQ: %d now active (prio %d)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, prio); #line 7057 "trace/trace-hw_intc.h" } else { #line 238 "../hw/intc/trace-events" qemu_log("nvic_acknowledge_irq " "NVIC acknowledge IRQ: %d now active (prio %d)" "\n", irq, prio); #line 7061 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_acknowledge_irq(int irq, int prio) { if (true) { _nocheck__trace_nvic_acknowledge_irq(irq, prio); } } #define TRACE_NVIC_GET_PENDING_IRQ_INFO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_GET_PENDING_IRQ_INFO) || \ false) static inline void _nocheck__trace_nvic_get_pending_irq_info(int irq, bool secure) { if (trace_event_get_state(TRACE_NVIC_GET_PENDING_IRQ_INFO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 239 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_get_pending_irq_info " "NVIC next IRQ %d: targets_secure: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, secure); #line 7088 "trace/trace-hw_intc.h" } else { #line 239 "../hw/intc/trace-events" qemu_log("nvic_get_pending_irq_info " "NVIC next IRQ %d: targets_secure: %d" "\n", irq, secure); #line 7092 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_get_pending_irq_info(int irq, bool secure) { if (true) { _nocheck__trace_nvic_get_pending_irq_info(irq, secure); } } #define TRACE_NVIC_COMPLETE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_COMPLETE_IRQ) || \ false) static inline void _nocheck__trace_nvic_complete_irq(int irq, bool secure) { if (trace_event_get_state(TRACE_NVIC_COMPLETE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 240 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_complete_irq " "NVIC complete IRQ %d (secure %d)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, secure); #line 7119 "trace/trace-hw_intc.h" } else { #line 240 "../hw/intc/trace-events" qemu_log("nvic_complete_irq " "NVIC complete IRQ %d (secure %d)" "\n", irq, secure); #line 7123 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_complete_irq(int irq, bool secure) { if (true) { _nocheck__trace_nvic_complete_irq(irq, secure); } } #define TRACE_NVIC_SET_IRQ_LEVEL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_SET_IRQ_LEVEL) || \ false) static inline void _nocheck__trace_nvic_set_irq_level(int irq, int level) { if (trace_event_get_state(TRACE_NVIC_SET_IRQ_LEVEL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 241 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_set_irq_level " "NVIC external irq %d level set to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 7150 "trace/trace-hw_intc.h" } else { #line 241 "../hw/intc/trace-events" qemu_log("nvic_set_irq_level " "NVIC external irq %d level set to %d" "\n", irq, level); #line 7154 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_set_irq_level(int irq, int level) { if (true) { _nocheck__trace_nvic_set_irq_level(irq, level); } } #define TRACE_NVIC_SET_NMI_LEVEL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_SET_NMI_LEVEL) || \ false) static inline void _nocheck__trace_nvic_set_nmi_level(int level) { if (trace_event_get_state(TRACE_NVIC_SET_NMI_LEVEL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 242 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_set_nmi_level " "NVIC external NMI level set to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , level); #line 7181 "trace/trace-hw_intc.h" } else { #line 242 "../hw/intc/trace-events" qemu_log("nvic_set_nmi_level " "NVIC external NMI level set to %d" "\n", level); #line 7185 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_set_nmi_level(int level) { if (true) { _nocheck__trace_nvic_set_nmi_level(level); } } #define TRACE_NVIC_SYSREG_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_SYSREG_READ) || \ false) static inline void _nocheck__trace_nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) { if (trace_event_get_state(TRACE_NVIC_SYSREG_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 243 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_sysreg_read " "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, value, size); #line 7212 "trace/trace-hw_intc.h" } else { #line 243 "../hw/intc/trace-events" qemu_log("nvic_sysreg_read " "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n", addr, value, size); #line 7216 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) { if (true) { _nocheck__trace_nvic_sysreg_read(addr, value, size); } } #define TRACE_NVIC_SYSREG_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NVIC_SYSREG_WRITE) || \ false) static inline void _nocheck__trace_nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) { if (trace_event_get_state(TRACE_NVIC_SYSREG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 244 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:nvic_sysreg_write " "NVIC sysreg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, value, size); #line 7243 "trace/trace-hw_intc.h" } else { #line 244 "../hw/intc/trace-events" qemu_log("nvic_sysreg_write " "NVIC sysreg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" "\n", addr, value, size); #line 7247 "trace/trace-hw_intc.h" } } } static inline void trace_nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) { if (true) { _nocheck__trace_nvic_sysreg_write(addr, value, size); } } #define TRACE_HEATHROW_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_HEATHROW_WRITE) || \ false) static inline void _nocheck__trace_heathrow_write(uint64_t addr, unsigned int n, uint64_t value) { if (trace_event_get_state(TRACE_HEATHROW_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 247 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:heathrow_write " "0x%"PRIx64" %u: 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, n, value); #line 7274 "trace/trace-hw_intc.h" } else { #line 247 "../hw/intc/trace-events" qemu_log("heathrow_write " "0x%"PRIx64" %u: 0x%"PRIx64 "\n", addr, n, value); #line 7278 "trace/trace-hw_intc.h" } } } static inline void trace_heathrow_write(uint64_t addr, unsigned int n, uint64_t value) { if (true) { _nocheck__trace_heathrow_write(addr, n, value); } } #define TRACE_HEATHROW_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_HEATHROW_READ) || \ false) static inline void _nocheck__trace_heathrow_read(uint64_t addr, unsigned int n, uint64_t value) { if (trace_event_get_state(TRACE_HEATHROW_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 248 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:heathrow_read " "0x%"PRIx64" %u: 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, n, value); #line 7305 "trace/trace-hw_intc.h" } else { #line 248 "../hw/intc/trace-events" qemu_log("heathrow_read " "0x%"PRIx64" %u: 0x%"PRIx64 "\n", addr, n, value); #line 7309 "trace/trace-hw_intc.h" } } } static inline void trace_heathrow_read(uint64_t addr, unsigned int n, uint64_t value) { if (true) { _nocheck__trace_heathrow_read(addr, n, value); } } #define TRACE_HEATHROW_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_HEATHROW_SET_IRQ) || \ false) static inline void _nocheck__trace_heathrow_set_irq(int num, int level) { if (trace_event_get_state(TRACE_HEATHROW_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 249 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:heathrow_set_irq " "set_irq: num=0x%02x level=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , num, level); #line 7336 "trace/trace-hw_intc.h" } else { #line 249 "../hw/intc/trace-events" qemu_log("heathrow_set_irq " "set_irq: num=0x%02x level=%d" "\n", num, level); #line 7340 "trace/trace-hw_intc.h" } } } static inline void trace_heathrow_set_irq(int num, int level) { if (true) { _nocheck__trace_heathrow_set_irq(num, level); } } #define TRACE_BCM2835_IC_SET_GPU_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_BCM2835_IC_SET_GPU_IRQ) || \ false) static inline void _nocheck__trace_bcm2835_ic_set_gpu_irq(int irq, int level) { if (trace_event_get_state(TRACE_BCM2835_IC_SET_GPU_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 252 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:bcm2835_ic_set_gpu_irq " "GPU irq #%d level %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 7367 "trace/trace-hw_intc.h" } else { #line 252 "../hw/intc/trace-events" qemu_log("bcm2835_ic_set_gpu_irq " "GPU irq #%d level %d" "\n", irq, level); #line 7371 "trace/trace-hw_intc.h" } } } static inline void trace_bcm2835_ic_set_gpu_irq(int irq, int level) { if (true) { _nocheck__trace_bcm2835_ic_set_gpu_irq(irq, level); } } #define TRACE_BCM2835_IC_SET_CPU_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_BCM2835_IC_SET_CPU_IRQ) || \ false) static inline void _nocheck__trace_bcm2835_ic_set_cpu_irq(int irq, int level) { if (trace_event_get_state(TRACE_BCM2835_IC_SET_CPU_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 253 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:bcm2835_ic_set_cpu_irq " "CPU irq #%d level %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 7398 "trace/trace-hw_intc.h" } else { #line 253 "../hw/intc/trace-events" qemu_log("bcm2835_ic_set_cpu_irq " "CPU irq #%d level %d" "\n", irq, level); #line 7402 "trace/trace-hw_intc.h" } } } static inline void trace_bcm2835_ic_set_cpu_irq(int irq, int level) { if (true) { _nocheck__trace_bcm2835_ic_set_cpu_irq(irq, level); } } #define TRACE_SPAPR_XIVE_CLAIM_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_CLAIM_IRQ) || \ false) static inline void _nocheck__trace_spapr_xive_claim_irq(uint32_t lisn, bool lsi) { if (trace_event_get_state(TRACE_SPAPR_XIVE_CLAIM_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 256 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_claim_irq " "lisn=0x%x lsi=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , lisn, lsi); #line 7429 "trace/trace-hw_intc.h" } else { #line 256 "../hw/intc/trace-events" qemu_log("spapr_xive_claim_irq " "lisn=0x%x lsi=%d" "\n", lisn, lsi); #line 7433 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_claim_irq(uint32_t lisn, bool lsi) { if (true) { _nocheck__trace_spapr_xive_claim_irq(lisn, lsi); } } #define TRACE_SPAPR_XIVE_FREE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_FREE_IRQ) || \ false) static inline void _nocheck__trace_spapr_xive_free_irq(uint32_t lisn) { if (trace_event_get_state(TRACE_SPAPR_XIVE_FREE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 257 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_free_irq " "lisn=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , lisn); #line 7460 "trace/trace-hw_intc.h" } else { #line 257 "../hw/intc/trace-events" qemu_log("spapr_xive_free_irq " "lisn=0x%x" "\n", lisn); #line 7464 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_free_irq(uint32_t lisn) { if (true) { _nocheck__trace_spapr_xive_free_irq(lisn); } } #define TRACE_SPAPR_XIVE_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_SET_IRQ) || \ false) static inline void _nocheck__trace_spapr_xive_set_irq(uint32_t lisn, uint32_t val) { if (trace_event_get_state(TRACE_SPAPR_XIVE_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 258 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_set_irq " "lisn=0x%x val=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , lisn, val); #line 7491 "trace/trace-hw_intc.h" } else { #line 258 "../hw/intc/trace-events" qemu_log("spapr_xive_set_irq " "lisn=0x%x val=%d" "\n", lisn, val); #line 7495 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_set_irq(uint32_t lisn, uint32_t val) { if (true) { _nocheck__trace_spapr_xive_set_irq(lisn, val); } } #define TRACE_SPAPR_XIVE_GET_SOURCE_INFO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_GET_SOURCE_INFO) || \ false) static inline void _nocheck__trace_spapr_xive_get_source_info(uint64_t flags, uint64_t lisn) { if (trace_event_get_state(TRACE_SPAPR_XIVE_GET_SOURCE_INFO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 259 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_get_source_info " "flags=0x%"PRIx64" lisn=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags, lisn); #line 7522 "trace/trace-hw_intc.h" } else { #line 259 "../hw/intc/trace-events" qemu_log("spapr_xive_get_source_info " "flags=0x%"PRIx64" lisn=0x%"PRIx64 "\n", flags, lisn); #line 7526 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_get_source_info(uint64_t flags, uint64_t lisn) { if (true) { _nocheck__trace_spapr_xive_get_source_info(flags, lisn); } } #define TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG) || \ false) static inline void _nocheck__trace_spapr_xive_set_source_config(uint64_t flags, uint64_t lisn, uint64_t target, uint64_t priority, uint64_t eisn) { if (trace_event_get_state(TRACE_SPAPR_XIVE_SET_SOURCE_CONFIG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 260 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_set_source_config " "flags=0x%"PRIx64" lisn=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64" eisn=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags, lisn, target, priority, eisn); #line 7553 "trace/trace-hw_intc.h" } else { #line 260 "../hw/intc/trace-events" qemu_log("spapr_xive_set_source_config " "flags=0x%"PRIx64" lisn=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64" eisn=0x%"PRIx64 "\n", flags, lisn, target, priority, eisn); #line 7557 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_set_source_config(uint64_t flags, uint64_t lisn, uint64_t target, uint64_t priority, uint64_t eisn) { if (true) { _nocheck__trace_spapr_xive_set_source_config(flags, lisn, target, priority, eisn); } } #define TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG) || \ false) static inline void _nocheck__trace_spapr_xive_get_source_config(uint64_t flags, uint64_t lisn) { if (trace_event_get_state(TRACE_SPAPR_XIVE_GET_SOURCE_CONFIG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 261 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_get_source_config " "flags=0x%"PRIx64" lisn=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags, lisn); #line 7584 "trace/trace-hw_intc.h" } else { #line 261 "../hw/intc/trace-events" qemu_log("spapr_xive_get_source_config " "flags=0x%"PRIx64" lisn=0x%"PRIx64 "\n", flags, lisn); #line 7588 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_get_source_config(uint64_t flags, uint64_t lisn) { if (true) { _nocheck__trace_spapr_xive_get_source_config(flags, lisn); } } #define TRACE_SPAPR_XIVE_GET_QUEUE_INFO_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_GET_QUEUE_INFO) || \ false) static inline void _nocheck__trace_spapr_xive_get_queue_info(uint64_t flags, uint64_t target, uint64_t priority) { if (trace_event_get_state(TRACE_SPAPR_XIVE_GET_QUEUE_INFO) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 262 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_get_queue_info " "flags=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags, target, priority); #line 7615 "trace/trace-hw_intc.h" } else { #line 262 "../hw/intc/trace-events" qemu_log("spapr_xive_get_queue_info " "flags=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64 "\n", flags, target, priority); #line 7619 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_get_queue_info(uint64_t flags, uint64_t target, uint64_t priority) { if (true) { _nocheck__trace_spapr_xive_get_queue_info(flags, target, priority); } } #define TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG) || \ false) static inline void _nocheck__trace_spapr_xive_set_queue_config(uint64_t flags, uint64_t target, uint64_t priority, uint64_t qpage, uint64_t qsize) { if (trace_event_get_state(TRACE_SPAPR_XIVE_SET_QUEUE_CONFIG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 263 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_set_queue_config " "flags=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64" qpage=0x%"PRIx64" qsize=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags, target, priority, qpage, qsize); #line 7646 "trace/trace-hw_intc.h" } else { #line 263 "../hw/intc/trace-events" qemu_log("spapr_xive_set_queue_config " "flags=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64" qpage=0x%"PRIx64" qsize=0x%"PRIx64 "\n", flags, target, priority, qpage, qsize); #line 7650 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_set_queue_config(uint64_t flags, uint64_t target, uint64_t priority, uint64_t qpage, uint64_t qsize) { if (true) { _nocheck__trace_spapr_xive_set_queue_config(flags, target, priority, qpage, qsize); } } #define TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG) || \ false) static inline void _nocheck__trace_spapr_xive_get_queue_config(uint64_t flags, uint64_t target, uint64_t priority) { if (trace_event_get_state(TRACE_SPAPR_XIVE_GET_QUEUE_CONFIG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 264 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_get_queue_config " "flags=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags, target, priority); #line 7677 "trace/trace-hw_intc.h" } else { #line 264 "../hw/intc/trace-events" qemu_log("spapr_xive_get_queue_config " "flags=0x%"PRIx64" target=0x%"PRIx64" priority=0x%"PRIx64 "\n", flags, target, priority); #line 7681 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_get_queue_config(uint64_t flags, uint64_t target, uint64_t priority) { if (true) { _nocheck__trace_spapr_xive_get_queue_config(flags, target, priority); } } #define TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE) || \ false) static inline void _nocheck__trace_spapr_xive_set_os_reporting_line(uint64_t flags) { if (trace_event_get_state(TRACE_SPAPR_XIVE_SET_OS_REPORTING_LINE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 265 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_set_os_reporting_line " "flags=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags); #line 7708 "trace/trace-hw_intc.h" } else { #line 265 "../hw/intc/trace-events" qemu_log("spapr_xive_set_os_reporting_line " "flags=0x%"PRIx64 "\n", flags); #line 7712 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_set_os_reporting_line(uint64_t flags) { if (true) { _nocheck__trace_spapr_xive_set_os_reporting_line(flags); } } #define TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE) || \ false) static inline void _nocheck__trace_spapr_xive_get_os_reporting_line(uint64_t flags) { if (trace_event_get_state(TRACE_SPAPR_XIVE_GET_OS_REPORTING_LINE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 266 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_get_os_reporting_line " "flags=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags); #line 7739 "trace/trace-hw_intc.h" } else { #line 266 "../hw/intc/trace-events" qemu_log("spapr_xive_get_os_reporting_line " "flags=0x%"PRIx64 "\n", flags); #line 7743 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_get_os_reporting_line(uint64_t flags) { if (true) { _nocheck__trace_spapr_xive_get_os_reporting_line(flags); } } #define TRACE_SPAPR_XIVE_ESB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_ESB) || \ false) static inline void _nocheck__trace_spapr_xive_esb(uint64_t flags, uint64_t lisn, uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_SPAPR_XIVE_ESB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 267 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_esb " "flags=0x%"PRIx64" lisn=0x%"PRIx64" offset=0x%"PRIx64" data=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags, lisn, offset, data); #line 7770 "trace/trace-hw_intc.h" } else { #line 267 "../hw/intc/trace-events" qemu_log("spapr_xive_esb " "flags=0x%"PRIx64" lisn=0x%"PRIx64" offset=0x%"PRIx64" data=0x%"PRIx64 "\n", flags, lisn, offset, data); #line 7774 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_esb(uint64_t flags, uint64_t lisn, uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_spapr_xive_esb(flags, lisn, offset, data); } } #define TRACE_SPAPR_XIVE_SYNC_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_SYNC) || \ false) static inline void _nocheck__trace_spapr_xive_sync(uint64_t flags, uint64_t lisn) { if (trace_event_get_state(TRACE_SPAPR_XIVE_SYNC) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 268 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_sync " "flags=0x%"PRIx64" lisn=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags, lisn); #line 7801 "trace/trace-hw_intc.h" } else { #line 268 "../hw/intc/trace-events" qemu_log("spapr_xive_sync " "flags=0x%"PRIx64" lisn=0x%"PRIx64 "\n", flags, lisn); #line 7805 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_sync(uint64_t flags, uint64_t lisn) { if (true) { _nocheck__trace_spapr_xive_sync(flags, lisn); } } #define TRACE_SPAPR_XIVE_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SPAPR_XIVE_RESET) || \ false) static inline void _nocheck__trace_spapr_xive_reset(uint64_t flags) { if (trace_event_get_state(TRACE_SPAPR_XIVE_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 269 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:spapr_xive_reset " "flags=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , flags); #line 7832 "trace/trace-hw_intc.h" } else { #line 269 "../hw/intc/trace-events" qemu_log("spapr_xive_reset " "flags=0x%"PRIx64 "\n", flags); #line 7836 "trace/trace-hw_intc.h" } } } static inline void trace_spapr_xive_reset(uint64_t flags) { if (true) { _nocheck__trace_spapr_xive_reset(flags); } } #define TRACE_KVM_XIVE_CPU_CONNECT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_KVM_XIVE_CPU_CONNECT) || \ false) static inline void _nocheck__trace_kvm_xive_cpu_connect(uint32_t id) { if (trace_event_get_state(TRACE_KVM_XIVE_CPU_CONNECT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 272 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:kvm_xive_cpu_connect " "connect CPU%d to KVM device" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , id); #line 7863 "trace/trace-hw_intc.h" } else { #line 272 "../hw/intc/trace-events" qemu_log("kvm_xive_cpu_connect " "connect CPU%d to KVM device" "\n", id); #line 7867 "trace/trace-hw_intc.h" } } } static inline void trace_kvm_xive_cpu_connect(uint32_t id) { if (true) { _nocheck__trace_kvm_xive_cpu_connect(id); } } #define TRACE_KVM_XIVE_SOURCE_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_KVM_XIVE_SOURCE_RESET) || \ false) static inline void _nocheck__trace_kvm_xive_source_reset(uint32_t srcno) { if (trace_event_get_state(TRACE_KVM_XIVE_SOURCE_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 273 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:kvm_xive_source_reset " "IRQ 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , srcno); #line 7894 "trace/trace-hw_intc.h" } else { #line 273 "../hw/intc/trace-events" qemu_log("kvm_xive_source_reset " "IRQ 0x%x" "\n", srcno); #line 7898 "trace/trace-hw_intc.h" } } } static inline void trace_kvm_xive_source_reset(uint32_t srcno) { if (true) { _nocheck__trace_kvm_xive_source_reset(srcno); } } #define TRACE_XIVE_TCTX_ACCEPT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XIVE_TCTX_ACCEPT) || \ false) static inline void _nocheck__trace_xive_tctx_accept(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr) { if (trace_event_get_state(TRACE_XIVE_TCTX_ACCEPT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 276 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xive_tctx_accept " "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x CPPR=0x%02x NSR=0x%02x ACK" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, ring, ipb, pipr, cppr, nsr); #line 7925 "trace/trace-hw_intc.h" } else { #line 276 "../hw/intc/trace-events" qemu_log("xive_tctx_accept " "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x CPPR=0x%02x NSR=0x%02x ACK" "\n", index, ring, ipb, pipr, cppr, nsr); #line 7929 "trace/trace-hw_intc.h" } } } static inline void trace_xive_tctx_accept(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr) { if (true) { _nocheck__trace_xive_tctx_accept(index, ring, ipb, pipr, cppr, nsr); } } #define TRACE_XIVE_TCTX_NOTIFY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XIVE_TCTX_NOTIFY) || \ false) static inline void _nocheck__trace_xive_tctx_notify(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr) { if (trace_event_get_state(TRACE_XIVE_TCTX_NOTIFY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 277 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xive_tctx_notify " "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x CPPR=0x%02x NSR=0x%02x raise !" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, ring, ipb, pipr, cppr, nsr); #line 7956 "trace/trace-hw_intc.h" } else { #line 277 "../hw/intc/trace-events" qemu_log("xive_tctx_notify " "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x CPPR=0x%02x NSR=0x%02x raise !" "\n", index, ring, ipb, pipr, cppr, nsr); #line 7960 "trace/trace-hw_intc.h" } } } static inline void trace_xive_tctx_notify(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr) { if (true) { _nocheck__trace_xive_tctx_notify(index, ring, ipb, pipr, cppr, nsr); } } #define TRACE_XIVE_TCTX_SET_CPPR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XIVE_TCTX_SET_CPPR) || \ false) static inline void _nocheck__trace_xive_tctx_set_cppr(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr) { if (trace_event_get_state(TRACE_XIVE_TCTX_SET_CPPR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 278 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xive_tctx_set_cppr " "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x new CPPR=0x%02x NSR=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, ring, ipb, pipr, cppr, nsr); #line 7987 "trace/trace-hw_intc.h" } else { #line 278 "../hw/intc/trace-events" qemu_log("xive_tctx_set_cppr " "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x new CPPR=0x%02x NSR=0x%02x" "\n", index, ring, ipb, pipr, cppr, nsr); #line 7991 "trace/trace-hw_intc.h" } } } static inline void trace_xive_tctx_set_cppr(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, uint8_t cppr, uint8_t nsr) { if (true) { _nocheck__trace_xive_tctx_set_cppr(index, ring, ipb, pipr, cppr, nsr); } } #define TRACE_XIVE_SOURCE_ESB_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XIVE_SOURCE_ESB_READ) || \ false) static inline void _nocheck__trace_xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) { if (trace_event_get_state(TRACE_XIVE_SOURCE_ESB_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 279 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xive_source_esb_read " "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, srcno, value); #line 8018 "trace/trace-hw_intc.h" } else { #line 279 "../hw/intc/trace-events" qemu_log("xive_source_esb_read " "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64 "\n", addr, srcno, value); #line 8022 "trace/trace-hw_intc.h" } } } static inline void trace_xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) { if (true) { _nocheck__trace_xive_source_esb_read(addr, srcno, value); } } #define TRACE_XIVE_SOURCE_ESB_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XIVE_SOURCE_ESB_WRITE) || \ false) static inline void _nocheck__trace_xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) { if (trace_event_get_state(TRACE_XIVE_SOURCE_ESB_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 280 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xive_source_esb_write " "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, srcno, value); #line 8049 "trace/trace-hw_intc.h" } else { #line 280 "../hw/intc/trace-events" qemu_log("xive_source_esb_write " "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64 "\n", addr, srcno, value); #line 8053 "trace/trace-hw_intc.h" } } } static inline void trace_xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) { if (true) { _nocheck__trace_xive_source_esb_write(addr, srcno, value); } } #define TRACE_XIVE_ROUTER_END_NOTIFY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XIVE_ROUTER_END_NOTIFY) || \ false) static inline void _nocheck__trace_xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data) { if (trace_event_get_state(TRACE_XIVE_ROUTER_END_NOTIFY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 281 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xive_router_end_notify " "END 0x%02x/0x%04x -> enqueue 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , end_blk, end_idx, end_data); #line 8080 "trace/trace-hw_intc.h" } else { #line 281 "../hw/intc/trace-events" qemu_log("xive_router_end_notify " "END 0x%02x/0x%04x -> enqueue 0x%08x" "\n", end_blk, end_idx, end_data); #line 8084 "trace/trace-hw_intc.h" } } } static inline void trace_xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data) { if (true) { _nocheck__trace_xive_router_end_notify(end_blk, end_idx, end_data); } } #define TRACE_XIVE_ROUTER_END_ESCALATE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XIVE_ROUTER_END_ESCALATE) || \ false) static inline void _nocheck__trace_xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t end_data) { if (trace_event_get_state(TRACE_XIVE_ROUTER_END_ESCALATE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 282 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xive_router_end_escalate " "END 0x%02x/0x%04x -> escalate END 0x%02x/0x%04x data 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , end_blk, end_idx, esc_blk, esc_idx, end_data); #line 8111 "trace/trace-hw_intc.h" } else { #line 282 "../hw/intc/trace-events" qemu_log("xive_router_end_escalate " "END 0x%02x/0x%04x -> escalate END 0x%02x/0x%04x data 0x%08x" "\n", end_blk, end_idx, esc_blk, esc_idx, end_data); #line 8115 "trace/trace-hw_intc.h" } } } static inline void trace_xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t end_data) { if (true) { _nocheck__trace_xive_router_end_escalate(end_blk, end_idx, esc_blk, esc_idx, end_data); } } #define TRACE_XIVE_TCTX_TM_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XIVE_TCTX_TM_WRITE) || \ false) static inline void _nocheck__trace_xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) { if (trace_event_get_state(TRACE_XIVE_TCTX_TM_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 283 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xive_tctx_tm_write " "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, offset, size, value); #line 8142 "trace/trace-hw_intc.h" } else { #line 283 "../hw/intc/trace-events" qemu_log("xive_tctx_tm_write " "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64 "\n", index, offset, size, value); #line 8146 "trace/trace-hw_intc.h" } } } static inline void trace_xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) { if (true) { _nocheck__trace_xive_tctx_tm_write(index, offset, size, value); } } #define TRACE_XIVE_TCTX_TM_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XIVE_TCTX_TM_READ) || \ false) static inline void _nocheck__trace_xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) { if (trace_event_get_state(TRACE_XIVE_TCTX_TM_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 284 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xive_tctx_tm_read " "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, offset, size, value); #line 8173 "trace/trace-hw_intc.h" } else { #line 284 "../hw/intc/trace-events" qemu_log("xive_tctx_tm_read " "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64 "\n", index, offset, size, value); #line 8177 "trace/trace-hw_intc.h" } } } static inline void trace_xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) { if (true) { _nocheck__trace_xive_tctx_tm_read(index, offset, size, value); } } #define TRACE_XIVE_PRESENTER_NOTIFY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XIVE_PRESENTER_NOTIFY) || \ false) static inline void _nocheck__trace_xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) { if (trace_event_get_state(TRACE_XIVE_PRESENTER_NOTIFY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 285 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xive_presenter_notify " "found NVT 0x%x/0x%x ring=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , nvt_blk, nvt_idx, ring); #line 8204 "trace/trace-hw_intc.h" } else { #line 285 "../hw/intc/trace-events" qemu_log("xive_presenter_notify " "found NVT 0x%x/0x%x ring=0x%x" "\n", nvt_blk, nvt_idx, ring); #line 8208 "trace/trace-hw_intc.h" } } } static inline void trace_xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) { if (true) { _nocheck__trace_xive_presenter_notify(nvt_blk, nvt_idx, ring); } } #define TRACE_XIVE_END_SOURCE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_XIVE_END_SOURCE_READ) || \ false) static inline void _nocheck__trace_xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) { if (trace_event_get_state(TRACE_XIVE_END_SOURCE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 286 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:xive_end_source_read " "END 0x%x/0x%x @0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , end_blk, end_idx, addr); #line 8235 "trace/trace-hw_intc.h" } else { #line 286 "../hw/intc/trace-events" qemu_log("xive_end_source_read " "END 0x%x/0x%x @0x%"PRIx64 "\n", end_blk, end_idx, addr); #line 8239 "trace/trace-hw_intc.h" } } } static inline void trace_xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) { if (true) { _nocheck__trace_xive_end_source_read(end_blk, end_idx, addr); } } #define TRACE_PNV_XIVE_IC_HW_TRIGGER_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_PNV_XIVE_IC_HW_TRIGGER) || \ false) static inline void _nocheck__trace_pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_PNV_XIVE_IC_HW_TRIGGER) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 289 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:pnv_xive_ic_hw_trigger " "@0x%"PRIx64" val=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 8266 "trace/trace-hw_intc.h" } else { #line 289 "../hw/intc/trace-events" qemu_log("pnv_xive_ic_hw_trigger " "@0x%"PRIx64" val=0x%"PRIx64 "\n", addr, val); #line 8270 "trace/trace-hw_intc.h" } } } static inline void trace_pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_pnv_xive_ic_hw_trigger(addr, val); } } #define TRACE_GOLDFISH_IRQ_REQUEST_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_IRQ_REQUEST) || \ false) static inline void _nocheck__trace_goldfish_irq_request(void * dev, int idx, int irq, int level) { if (trace_event_get_state(TRACE_GOLDFISH_IRQ_REQUEST) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 292 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:goldfish_irq_request " "pic: %p goldfish-irq.%d irq: %d level: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dev, idx, irq, level); #line 8297 "trace/trace-hw_intc.h" } else { #line 292 "../hw/intc/trace-events" qemu_log("goldfish_irq_request " "pic: %p goldfish-irq.%d irq: %d level: %d" "\n", dev, idx, irq, level); #line 8301 "trace/trace-hw_intc.h" } } } static inline void trace_goldfish_irq_request(void * dev, int idx, int irq, int level) { if (true) { _nocheck__trace_goldfish_irq_request(dev, idx, irq, level); } } #define TRACE_GOLDFISH_PIC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_PIC_READ) || \ false) static inline void _nocheck__trace_goldfish_pic_read(void * dev, int idx, unsigned int addr, unsigned int size, uint64_t value) { if (trace_event_get_state(TRACE_GOLDFISH_PIC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 293 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:goldfish_pic_read " "pic: %p goldfish-irq.%d reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dev, idx, addr, size, value); #line 8328 "trace/trace-hw_intc.h" } else { #line 293 "../hw/intc/trace-events" qemu_log("goldfish_pic_read " "pic: %p goldfish-irq.%d reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", dev, idx, addr, size, value); #line 8332 "trace/trace-hw_intc.h" } } } static inline void trace_goldfish_pic_read(void * dev, int idx, unsigned int addr, unsigned int size, uint64_t value) { if (true) { _nocheck__trace_goldfish_pic_read(dev, idx, addr, size, value); } } #define TRACE_GOLDFISH_PIC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_PIC_WRITE) || \ false) static inline void _nocheck__trace_goldfish_pic_write(void * dev, int idx, unsigned int addr, unsigned int size, uint64_t value) { if (trace_event_get_state(TRACE_GOLDFISH_PIC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 294 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:goldfish_pic_write " "pic: %p goldfish-irq.%d reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dev, idx, addr, size, value); #line 8359 "trace/trace-hw_intc.h" } else { #line 294 "../hw/intc/trace-events" qemu_log("goldfish_pic_write " "pic: %p goldfish-irq.%d reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", dev, idx, addr, size, value); #line 8363 "trace/trace-hw_intc.h" } } } static inline void trace_goldfish_pic_write(void * dev, int idx, unsigned int addr, unsigned int size, uint64_t value) { if (true) { _nocheck__trace_goldfish_pic_write(dev, idx, addr, size, value); } } #define TRACE_GOLDFISH_PIC_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_PIC_RESET) || \ false) static inline void _nocheck__trace_goldfish_pic_reset(void * dev, int idx) { if (trace_event_get_state(TRACE_GOLDFISH_PIC_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 295 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:goldfish_pic_reset " "pic: %p goldfish-irq.%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dev, idx); #line 8390 "trace/trace-hw_intc.h" } else { #line 295 "../hw/intc/trace-events" qemu_log("goldfish_pic_reset " "pic: %p goldfish-irq.%d" "\n", dev, idx); #line 8394 "trace/trace-hw_intc.h" } } } static inline void trace_goldfish_pic_reset(void * dev, int idx) { if (true) { _nocheck__trace_goldfish_pic_reset(dev, idx); } } #define TRACE_GOLDFISH_PIC_REALIZE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_PIC_REALIZE) || \ false) static inline void _nocheck__trace_goldfish_pic_realize(void * dev, int idx) { if (trace_event_get_state(TRACE_GOLDFISH_PIC_REALIZE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 296 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:goldfish_pic_realize " "pic: %p goldfish-irq.%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dev, idx); #line 8421 "trace/trace-hw_intc.h" } else { #line 296 "../hw/intc/trace-events" qemu_log("goldfish_pic_realize " "pic: %p goldfish-irq.%d" "\n", dev, idx); #line 8425 "trace/trace-hw_intc.h" } } } static inline void trace_goldfish_pic_realize(void * dev, int idx) { if (true) { _nocheck__trace_goldfish_pic_realize(dev, idx); } } #define TRACE_GOLDFISH_PIC_INSTANCE_INIT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GOLDFISH_PIC_INSTANCE_INIT) || \ false) static inline void _nocheck__trace_goldfish_pic_instance_init(void * dev) { if (trace_event_get_state(TRACE_GOLDFISH_PIC_INSTANCE_INIT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 297 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:goldfish_pic_instance_init " "pic: %p goldfish-irq" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dev); #line 8452 "trace/trace-hw_intc.h" } else { #line 297 "../hw/intc/trace-events" qemu_log("goldfish_pic_instance_init " "pic: %p goldfish-irq" "\n", dev); #line 8456 "trace/trace-hw_intc.h" } } } static inline void trace_goldfish_pic_instance_init(void * dev) { if (true) { _nocheck__trace_goldfish_pic_instance_init(dev); } } #define TRACE_SH_INTC_SOURCES_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_SOURCES) || \ false) static inline void _nocheck__trace_sh_intc_sources(int p, int a, int c, int m, unsigned short v, const char * s1, const char * s2, const char * s3) { if (trace_event_get_state(TRACE_SH_INTC_SOURCES) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 300 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:sh_intc_sources " "(%d/%d/%d/%d) interrupt source 0x%x %s%s%s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , p, a, c, m, v, s1, s2, s3); #line 8483 "trace/trace-hw_intc.h" } else { #line 300 "../hw/intc/trace-events" qemu_log("sh_intc_sources " "(%d/%d/%d/%d) interrupt source 0x%x %s%s%s" "\n", p, a, c, m, v, s1, s2, s3); #line 8487 "trace/trace-hw_intc.h" } } } static inline void trace_sh_intc_sources(int p, int a, int c, int m, unsigned short v, const char * s1, const char * s2, const char * s3) { if (true) { _nocheck__trace_sh_intc_sources(p, a, c, m, v, s1, s2, s3); } } #define TRACE_SH_INTC_PENDING_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_PENDING) || \ false) static inline void _nocheck__trace_sh_intc_pending(int p, unsigned short v) { if (trace_event_get_state(TRACE_SH_INTC_PENDING) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 301 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:sh_intc_pending " "(%d) returning interrupt source 0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , p, v); #line 8514 "trace/trace-hw_intc.h" } else { #line 301 "../hw/intc/trace-events" qemu_log("sh_intc_pending " "(%d) returning interrupt source 0x%x" "\n", p, v); #line 8518 "trace/trace-hw_intc.h" } } } static inline void trace_sh_intc_pending(int p, unsigned short v) { if (true) { _nocheck__trace_sh_intc_pending(p, v); } } #define TRACE_SH_INTC_REGISTER_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_REGISTER) || \ false) static inline void _nocheck__trace_sh_intc_register(const char * s, int id, unsigned short v, int c, int m) { if (trace_event_get_state(TRACE_SH_INTC_REGISTER) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 302 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:sh_intc_register " "%s %u -> 0x%04x (%d/%d)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , s, id, v, c, m); #line 8545 "trace/trace-hw_intc.h" } else { #line 302 "../hw/intc/trace-events" qemu_log("sh_intc_register " "%s %u -> 0x%04x (%d/%d)" "\n", s, id, v, c, m); #line 8549 "trace/trace-hw_intc.h" } } } static inline void trace_sh_intc_register(const char * s, int id, unsigned short v, int c, int m) { if (true) { _nocheck__trace_sh_intc_register(s, id, v, c, m); } } #define TRACE_SH_INTC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_READ) || \ false) static inline void _nocheck__trace_sh_intc_read(unsigned size, uint64_t offset, unsigned long val) { if (trace_event_get_state(TRACE_SH_INTC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 303 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:sh_intc_read " "size %u 0x%" PRIx64 " -> 0x%lx" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, offset, val); #line 8576 "trace/trace-hw_intc.h" } else { #line 303 "../hw/intc/trace-events" qemu_log("sh_intc_read " "size %u 0x%" PRIx64 " -> 0x%lx" "\n", size, offset, val); #line 8580 "trace/trace-hw_intc.h" } } } static inline void trace_sh_intc_read(unsigned size, uint64_t offset, unsigned long val) { if (true) { _nocheck__trace_sh_intc_read(size, offset, val); } } #define TRACE_SH_INTC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_WRITE) || \ false) static inline void _nocheck__trace_sh_intc_write(unsigned size, uint64_t offset, unsigned long val) { if (trace_event_get_state(TRACE_SH_INTC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 304 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:sh_intc_write " "size %u 0x%" PRIx64 " <- 0x%lx" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, offset, val); #line 8607 "trace/trace-hw_intc.h" } else { #line 304 "../hw/intc/trace-events" qemu_log("sh_intc_write " "size %u 0x%" PRIx64 " <- 0x%lx" "\n", size, offset, val); #line 8611 "trace/trace-hw_intc.h" } } } static inline void trace_sh_intc_write(unsigned size, uint64_t offset, unsigned long val) { if (true) { _nocheck__trace_sh_intc_write(size, offset, val); } } #define TRACE_SH_INTC_SET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SH_INTC_SET) || \ false) static inline void _nocheck__trace_sh_intc_set(int id, int enable) { if (trace_event_get_state(TRACE_SH_INTC_SET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 305 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:sh_intc_set " "setting interrupt group %d to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , id, enable); #line 8638 "trace/trace-hw_intc.h" } else { #line 305 "../hw/intc/trace-events" qemu_log("sh_intc_set " "setting interrupt group %d to %d" "\n", id, enable); #line 8642 "trace/trace-hw_intc.h" } } } static inline void trace_sh_intc_set(int id, int enable) { if (true) { _nocheck__trace_sh_intc_set(id, enable); } } #define TRACE_LOONGSON_IPI_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGSON_IPI_READ) || \ false) static inline void _nocheck__trace_loongson_ipi_read(unsigned size, uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_LOONGSON_IPI_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 308 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongson_ipi_read " "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, val); #line 8669 "trace/trace-hw_intc.h" } else { #line 308 "../hw/intc/trace-events" qemu_log("loongson_ipi_read " "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64 "\n", size, addr, val); #line 8673 "trace/trace-hw_intc.h" } } } static inline void trace_loongson_ipi_read(unsigned size, uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_loongson_ipi_read(size, addr, val); } } #define TRACE_LOONGSON_IPI_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGSON_IPI_WRITE) || \ false) static inline void _nocheck__trace_loongson_ipi_write(unsigned size, uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_LOONGSON_IPI_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 309 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongson_ipi_write " "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, val); #line 8700 "trace/trace-hw_intc.h" } else { #line 309 "../hw/intc/trace-events" qemu_log("loongson_ipi_write " "size: %u addr: 0x%"PRIx64 "val: 0x%"PRIx64 "\n", size, addr, val); #line 8704 "trace/trace-hw_intc.h" } } } static inline void trace_loongson_ipi_write(unsigned size, uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_loongson_ipi_write(size, addr, val); } } #define TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER) || \ false) static inline void _nocheck__trace_loongarch_pch_pic_irq_handler(int irq, int level) { if (trace_event_get_state(TRACE_LOONGARCH_PCH_PIC_IRQ_HANDLER) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 311 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongarch_pch_pic_irq_handler " "irq %d level %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 8731 "trace/trace-hw_intc.h" } else { #line 311 "../hw/intc/trace-events" qemu_log("loongarch_pch_pic_irq_handler " "irq %d level %d" "\n", irq, level); #line 8735 "trace/trace-hw_intc.h" } } } static inline void trace_loongarch_pch_pic_irq_handler(int irq, int level) { if (true) { _nocheck__trace_loongarch_pch_pic_irq_handler(irq, level); } } #define TRACE_LOONGARCH_PCH_PIC_LOW_READW_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_PCH_PIC_LOW_READW) || \ false) static inline void _nocheck__trace_loongarch_pch_pic_low_readw(unsigned size, uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_LOONGARCH_PCH_PIC_LOW_READW) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 312 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongarch_pch_pic_low_readw " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, val); #line 8762 "trace/trace-hw_intc.h" } else { #line 312 "../hw/intc/trace-events" qemu_log("loongarch_pch_pic_low_readw " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", size, addr, val); #line 8766 "trace/trace-hw_intc.h" } } } static inline void trace_loongarch_pch_pic_low_readw(unsigned size, uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_loongarch_pch_pic_low_readw(size, addr, val); } } #define TRACE_LOONGARCH_PCH_PIC_LOW_WRITEW_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_PCH_PIC_LOW_WRITEW) || \ false) static inline void _nocheck__trace_loongarch_pch_pic_low_writew(unsigned size, uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_LOONGARCH_PCH_PIC_LOW_WRITEW) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 313 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongarch_pch_pic_low_writew " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, val); #line 8793 "trace/trace-hw_intc.h" } else { #line 313 "../hw/intc/trace-events" qemu_log("loongarch_pch_pic_low_writew " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", size, addr, val); #line 8797 "trace/trace-hw_intc.h" } } } static inline void trace_loongarch_pch_pic_low_writew(unsigned size, uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_loongarch_pch_pic_low_writew(size, addr, val); } } #define TRACE_LOONGARCH_PCH_PIC_HIGH_READW_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_PCH_PIC_HIGH_READW) || \ false) static inline void _nocheck__trace_loongarch_pch_pic_high_readw(unsigned size, uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_LOONGARCH_PCH_PIC_HIGH_READW) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 314 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongarch_pch_pic_high_readw " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, val); #line 8824 "trace/trace-hw_intc.h" } else { #line 314 "../hw/intc/trace-events" qemu_log("loongarch_pch_pic_high_readw " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", size, addr, val); #line 8828 "trace/trace-hw_intc.h" } } } static inline void trace_loongarch_pch_pic_high_readw(unsigned size, uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_loongarch_pch_pic_high_readw(size, addr, val); } } #define TRACE_LOONGARCH_PCH_PIC_HIGH_WRITEW_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_PCH_PIC_HIGH_WRITEW) || \ false) static inline void _nocheck__trace_loongarch_pch_pic_high_writew(unsigned size, uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_LOONGARCH_PCH_PIC_HIGH_WRITEW) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 315 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongarch_pch_pic_high_writew " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, val); #line 8855 "trace/trace-hw_intc.h" } else { #line 315 "../hw/intc/trace-events" qemu_log("loongarch_pch_pic_high_writew " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", size, addr, val); #line 8859 "trace/trace-hw_intc.h" } } } static inline void trace_loongarch_pch_pic_high_writew(unsigned size, uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_loongarch_pch_pic_high_writew(size, addr, val); } } #define TRACE_LOONGARCH_PCH_PIC_READB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_PCH_PIC_READB) || \ false) static inline void _nocheck__trace_loongarch_pch_pic_readb(unsigned size, uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_LOONGARCH_PCH_PIC_READB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 316 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongarch_pch_pic_readb " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, val); #line 8886 "trace/trace-hw_intc.h" } else { #line 316 "../hw/intc/trace-events" qemu_log("loongarch_pch_pic_readb " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", size, addr, val); #line 8890 "trace/trace-hw_intc.h" } } } static inline void trace_loongarch_pch_pic_readb(unsigned size, uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_loongarch_pch_pic_readb(size, addr, val); } } #define TRACE_LOONGARCH_PCH_PIC_WRITEB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_PCH_PIC_WRITEB) || \ false) static inline void _nocheck__trace_loongarch_pch_pic_writeb(unsigned size, uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_LOONGARCH_PCH_PIC_WRITEB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 317 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongarch_pch_pic_writeb " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, val); #line 8917 "trace/trace-hw_intc.h" } else { #line 317 "../hw/intc/trace-events" qemu_log("loongarch_pch_pic_writeb " "size: %u addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", size, addr, val); #line 8921 "trace/trace-hw_intc.h" } } } static inline void trace_loongarch_pch_pic_writeb(unsigned size, uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_loongarch_pch_pic_writeb(size, addr, val); } } #define TRACE_LOONGARCH_MSI_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_MSI_SET_IRQ) || \ false) static inline void _nocheck__trace_loongarch_msi_set_irq(int irq_num) { if (trace_event_get_state(TRACE_LOONGARCH_MSI_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 320 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongarch_msi_set_irq " "set msi irq %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq_num); #line 8948 "trace/trace-hw_intc.h" } else { #line 320 "../hw/intc/trace-events" qemu_log("loongarch_msi_set_irq " "set msi irq %d" "\n", irq_num); #line 8952 "trace/trace-hw_intc.h" } } } static inline void trace_loongarch_msi_set_irq(int irq_num) { if (true) { _nocheck__trace_loongarch_msi_set_irq(irq_num); } } #define TRACE_LOONGARCH_EXTIOI_SETIRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_EXTIOI_SETIRQ) || \ false) static inline void _nocheck__trace_loongarch_extioi_setirq(int irq, int level) { if (trace_event_get_state(TRACE_LOONGARCH_EXTIOI_SETIRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 323 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongarch_extioi_setirq " "set extirq irq %d level %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 8979 "trace/trace-hw_intc.h" } else { #line 323 "../hw/intc/trace-events" qemu_log("loongarch_extioi_setirq " "set extirq irq %d level %d" "\n", irq, level); #line 8983 "trace/trace-hw_intc.h" } } } static inline void trace_loongarch_extioi_setirq(int irq, int level) { if (true) { _nocheck__trace_loongarch_extioi_setirq(irq, level); } } #define TRACE_LOONGARCH_EXTIOI_READW_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_EXTIOI_READW) || \ false) static inline void _nocheck__trace_loongarch_extioi_readw(uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_LOONGARCH_EXTIOI_READW) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 324 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongarch_extioi_readw " "addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 9010 "trace/trace-hw_intc.h" } else { #line 324 "../hw/intc/trace-events" qemu_log("loongarch_extioi_readw " "addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", addr, val); #line 9014 "trace/trace-hw_intc.h" } } } static inline void trace_loongarch_extioi_readw(uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_loongarch_extioi_readw(addr, val); } } #define TRACE_LOONGARCH_EXTIOI_WRITEW_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LOONGARCH_EXTIOI_WRITEW) || \ false) static inline void _nocheck__trace_loongarch_extioi_writew(uint64_t addr, uint64_t val) { if (trace_event_get_state(TRACE_LOONGARCH_EXTIOI_WRITEW) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 325 "../hw/intc/trace-events" qemu_log("%d@%zu.%06zu:loongarch_extioi_writew " "addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 9041 "trace/trace-hw_intc.h" } else { #line 325 "../hw/intc/trace-events" qemu_log("loongarch_extioi_writew " "addr: 0x%"PRIx64 "val: 0x%" PRIx64 "\n", addr, val); #line 9045 "trace/trace-hw_intc.h" } } } static inline void trace_loongarch_extioi_writew(uint64_t addr, uint64_t val) { if (true) { _nocheck__trace_loongarch_extioi_writew(addr, val); } } #endif /* TRACE_HW_INTC_GENERATED_TRACERS_H */