/* This file is autogenerated by tracetool, do not edit. */ #ifndef TRACE_HW_MISC_GENERATED_TRACERS_H #define TRACE_HW_MISC_GENERATED_TRACERS_H #include "trace/control.h" extern TraceEvent _TRACE_ALLWINNER_CPUCFG_CPU_RESET_EVENT; extern TraceEvent _TRACE_ALLWINNER_CPUCFG_READ_EVENT; extern TraceEvent _TRACE_ALLWINNER_CPUCFG_WRITE_EVENT; extern TraceEvent _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_EVENT; extern TraceEvent _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_EVENT; extern TraceEvent _TRACE_ALLWINNER_H3_DRAMCOM_READ_EVENT; extern TraceEvent _TRACE_ALLWINNER_H3_DRAMCOM_WRITE_EVENT; extern TraceEvent _TRACE_ALLWINNER_H3_DRAMCTL_READ_EVENT; extern TraceEvent _TRACE_ALLWINNER_H3_DRAMCTL_WRITE_EVENT; extern TraceEvent _TRACE_ALLWINNER_H3_DRAMPHY_READ_EVENT; extern TraceEvent _TRACE_ALLWINNER_H3_DRAMPHY_WRITE_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMCOM_READ_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMCOM_WRITE_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMCTL_READ_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMCTL_WRITE_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMPHY_READ_EVENT; extern TraceEvent _TRACE_ALLWINNER_R40_DRAMPHY_WRITE_EVENT; extern TraceEvent _TRACE_ALLWINNER_SID_READ_EVENT; extern TraceEvent _TRACE_ALLWINNER_SID_WRITE_EVENT; extern TraceEvent _TRACE_ALLWINNER_SRAMC_READ_EVENT; extern TraceEvent _TRACE_ALLWINNER_SRAMC_WRITE_EVENT; extern TraceEvent _TRACE_AVR_POWER_READ_EVENT; extern TraceEvent _TRACE_AVR_POWER_WRITE_EVENT; extern TraceEvent _TRACE_AXP2XX_RX_EVENT; extern TraceEvent _TRACE_AXP2XX_SELECT_EVENT; extern TraceEvent _TRACE_AXP2XX_TX_EVENT; extern TraceEvent _TRACE_ECC_MEM_WRITEL_MER_EVENT; extern TraceEvent _TRACE_ECC_MEM_WRITEL_MDR_EVENT; extern TraceEvent _TRACE_ECC_MEM_WRITEL_MFSR_EVENT; extern TraceEvent _TRACE_ECC_MEM_WRITEL_VCR_EVENT; extern TraceEvent _TRACE_ECC_MEM_WRITEL_DR_EVENT; extern TraceEvent _TRACE_ECC_MEM_WRITEL_ECR0_EVENT; extern TraceEvent _TRACE_ECC_MEM_WRITEL_ECR1_EVENT; extern TraceEvent _TRACE_ECC_MEM_READL_MER_EVENT; extern TraceEvent _TRACE_ECC_MEM_READL_MDR_EVENT; extern TraceEvent _TRACE_ECC_MEM_READL_MFSR_EVENT; extern TraceEvent _TRACE_ECC_MEM_READL_VCR_EVENT; extern TraceEvent _TRACE_ECC_MEM_READL_MFAR0_EVENT; extern TraceEvent _TRACE_ECC_MEM_READL_MFAR1_EVENT; extern TraceEvent _TRACE_ECC_MEM_READL_DR_EVENT; extern TraceEvent _TRACE_ECC_MEM_READL_ECR0_EVENT; extern TraceEvent _TRACE_ECC_MEM_READL_ECR1_EVENT; extern TraceEvent _TRACE_ECC_DIAG_MEM_WRITEB_EVENT; extern TraceEvent _TRACE_ECC_DIAG_MEM_READB_EVENT; extern TraceEvent _TRACE_EMPTY_SLOT_WRITE_EVENT; extern TraceEvent _TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_EVENT; extern TraceEvent _TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_EVENT; extern TraceEvent _TRACE_SLAVIO_SET_POWER_FAIL_EVENT; extern TraceEvent _TRACE_SLAVIO_CFG_MEM_WRITEB_EVENT; extern TraceEvent _TRACE_SLAVIO_CFG_MEM_READB_EVENT; extern TraceEvent _TRACE_SLAVIO_DIAG_MEM_WRITEB_EVENT; extern TraceEvent _TRACE_SLAVIO_DIAG_MEM_READB_EVENT; extern TraceEvent _TRACE_SLAVIO_MDM_MEM_WRITEB_EVENT; extern TraceEvent _TRACE_SLAVIO_MDM_MEM_READB_EVENT; extern TraceEvent _TRACE_SLAVIO_AUX1_MEM_WRITEB_EVENT; extern TraceEvent _TRACE_SLAVIO_AUX1_MEM_READB_EVENT; extern TraceEvent _TRACE_SLAVIO_AUX2_MEM_WRITEB_EVENT; extern TraceEvent _TRACE_SLAVIO_AUX2_MEM_READB_EVENT; extern TraceEvent _TRACE_APC_MEM_WRITEB_EVENT; extern TraceEvent _TRACE_APC_MEM_READB_EVENT; extern TraceEvent _TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_EVENT; extern TraceEvent _TRACE_SLAVIO_SYSCTRL_MEM_READL_EVENT; extern TraceEvent _TRACE_SLAVIO_LED_MEM_WRITEW_EVENT; extern TraceEvent _TRACE_SLAVIO_LED_MEM_READW_EVENT; extern TraceEvent _TRACE_ASPEED_SCU_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_SCU_READ_EVENT; extern TraceEvent _TRACE_ASPEED_AST2700_SCU_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_AST2700_SCU_READ_EVENT; extern TraceEvent _TRACE_ASPEED_AST2700_SCUIO_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_AST2700_SCUIO_READ_EVENT; extern TraceEvent _TRACE_MPS2_SCC_READ_EVENT; extern TraceEvent _TRACE_MPS2_SCC_WRITE_EVENT; extern TraceEvent _TRACE_MPS2_SCC_RESET_EVENT; extern TraceEvent _TRACE_MPS2_SCC_CFG_WRITE_EVENT; extern TraceEvent _TRACE_MPS2_SCC_CFG_READ_EVENT; extern TraceEvent _TRACE_MPS2_FPGAIO_READ_EVENT; extern TraceEvent _TRACE_MPS2_FPGAIO_WRITE_EVENT; extern TraceEvent _TRACE_MPS2_FPGAIO_RESET_EVENT; extern TraceEvent _TRACE_MSF2_SYSREG_WRITE_EVENT; extern TraceEvent _TRACE_MSF2_SYSREG_READ_EVENT; extern TraceEvent _TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_EVENT; extern TraceEvent _TRACE_IMX7_GPR_READ_EVENT; extern TraceEvent _TRACE_IMX7_GPR_WRITE_EVENT; extern TraceEvent _TRACE_IMX7_SNVS_READ_EVENT; extern TraceEvent _TRACE_IMX7_SNVS_WRITE_EVENT; extern TraceEvent _TRACE_MOS6522_SET_COUNTER_EVENT; extern TraceEvent _TRACE_MOS6522_GET_NEXT_IRQ_TIME_EVENT; extern TraceEvent _TRACE_MOS6522_SET_SR_INT_EVENT; extern TraceEvent _TRACE_MOS6522_WRITE_EVENT; extern TraceEvent _TRACE_MOS6522_READ_EVENT; extern TraceEvent _TRACE_NPCM7XX_CLK_READ_EVENT; extern TraceEvent _TRACE_NPCM7XX_CLK_WRITE_EVENT; extern TraceEvent _TRACE_NPCM7XX_GCR_READ_EVENT; extern TraceEvent _TRACE_NPCM7XX_GCR_WRITE_EVENT; extern TraceEvent _TRACE_NPCM7XX_MFT_READ_EVENT; extern TraceEvent _TRACE_NPCM7XX_MFT_WRITE_EVENT; extern TraceEvent _TRACE_NPCM7XX_MFT_RPM_EVENT; extern TraceEvent _TRACE_NPCM7XX_MFT_CAPTURE_EVENT; extern TraceEvent _TRACE_NPCM7XX_MFT_UPDATE_CLOCK_EVENT; extern TraceEvent _TRACE_NPCM7XX_MFT_SET_DUTY_EVENT; extern TraceEvent _TRACE_NPCM7XX_RNG_READ_EVENT; extern TraceEvent _TRACE_NPCM7XX_RNG_WRITE_EVENT; extern TraceEvent _TRACE_NPCM7XX_PWM_READ_EVENT; extern TraceEvent _TRACE_NPCM7XX_PWM_WRITE_EVENT; extern TraceEvent _TRACE_NPCM7XX_PWM_UPDATE_FREQ_EVENT; extern TraceEvent _TRACE_NPCM7XX_PWM_UPDATE_DUTY_EVENT; extern TraceEvent _TRACE_STM32_RCC_READ_EVENT; extern TraceEvent _TRACE_STM32_RCC_WRITE_EVENT; extern TraceEvent _TRACE_STM32_RCC_PULSE_ENABLE_EVENT; extern TraceEvent _TRACE_STM32_RCC_PULSE_RESET_EVENT; extern TraceEvent _TRACE_STM32F4XX_SYSCFG_SET_IRQ_EVENT; extern TraceEvent _TRACE_STM32F4XX_PULSE_EXTI_EVENT; extern TraceEvent _TRACE_STM32F4XX_SYSCFG_READ_EVENT; extern TraceEvent _TRACE_STM32F4XX_SYSCFG_WRITE_EVENT; extern TraceEvent _TRACE_STM32F4XX_EXTI_SET_IRQ_EVENT; extern TraceEvent _TRACE_STM32F4XX_EXTI_READ_EVENT; extern TraceEvent _TRACE_STM32F4XX_EXTI_WRITE_EVENT; extern TraceEvent _TRACE_STM32L4X5_SYSCFG_SET_IRQ_EVENT; extern TraceEvent _TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_EVENT; extern TraceEvent _TRACE_STM32L4X5_SYSCFG_READ_EVENT; extern TraceEvent _TRACE_STM32L4X5_SYSCFG_WRITE_EVENT; extern TraceEvent _TRACE_STM32L4X5_EXTI_SET_IRQ_EVENT; extern TraceEvent _TRACE_STM32L4X5_EXTI_READ_EVENT; extern TraceEvent _TRACE_STM32L4X5_EXTI_WRITE_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_READ_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_WRITE_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_MUX_ENABLE_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_MUX_DISABLE_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_MUX_SET_SRC_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_MUX_UPDATE_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_EVENT; extern TraceEvent _TRACE_STM32L4X5_RCC_PLL_UPDATE_EVENT; extern TraceEvent _TRACE_TZ_MPC_REG_READ_EVENT; extern TraceEvent _TRACE_TZ_MPC_REG_WRITE_EVENT; extern TraceEvent _TRACE_TZ_MPC_MEM_BLOCKED_READ_EVENT; extern TraceEvent _TRACE_TZ_MPC_MEM_BLOCKED_WRITE_EVENT; extern TraceEvent _TRACE_TZ_MPC_TRANSLATE_EVENT; extern TraceEvent _TRACE_TZ_MPC_IOMMU_NOTIFY_EVENT; extern TraceEvent _TRACE_TZ_MSC_RESET_EVENT; extern TraceEvent _TRACE_TZ_MSC_CFG_NONSEC_EVENT; extern TraceEvent _TRACE_TZ_MSC_CFG_SEC_RESP_EVENT; extern TraceEvent _TRACE_TZ_MSC_IRQ_CLEAR_EVENT; extern TraceEvent _TRACE_TZ_MSC_UPDATE_IRQ_EVENT; extern TraceEvent _TRACE_TZ_MSC_ACCESS_BLOCKED_EVENT; extern TraceEvent _TRACE_TZ_PPC_RESET_EVENT; extern TraceEvent _TRACE_TZ_PPC_CFG_NONSEC_EVENT; extern TraceEvent _TRACE_TZ_PPC_CFG_AP_EVENT; extern TraceEvent _TRACE_TZ_PPC_CFG_SEC_RESP_EVENT; extern TraceEvent _TRACE_TZ_PPC_IRQ_ENABLE_EVENT; extern TraceEvent _TRACE_TZ_PPC_IRQ_CLEAR_EVENT; extern TraceEvent _TRACE_TZ_PPC_UPDATE_IRQ_EVENT; extern TraceEvent _TRACE_TZ_PPC_READ_BLOCKED_EVENT; extern TraceEvent _TRACE_TZ_PPC_WRITE_BLOCKED_EVENT; extern TraceEvent _TRACE_IOTKIT_SECCTL_S_READ_EVENT; extern TraceEvent _TRACE_IOTKIT_SECCTL_S_WRITE_EVENT; extern TraceEvent _TRACE_IOTKIT_SECCTL_NS_READ_EVENT; extern TraceEvent _TRACE_IOTKIT_SECCTL_NS_WRITE_EVENT; extern TraceEvent _TRACE_IMX6_ANALOG_GET_PERIPH_CLK_EVENT; extern TraceEvent _TRACE_IMX6_ANALOG_GET_PLL2_CLK_EVENT; extern TraceEvent _TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_EVENT; extern TraceEvent _TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_EVENT; extern TraceEvent _TRACE_IMX6_ANALOG_READ_EVENT; extern TraceEvent _TRACE_IMX6_ANALOG_WRITE_EVENT; extern TraceEvent _TRACE_IMX6_CCM_GET_AHB_CLK_EVENT; extern TraceEvent _TRACE_IMX6_CCM_GET_IPG_CLK_EVENT; extern TraceEvent _TRACE_IMX6_CCM_GET_PER_CLK_EVENT; extern TraceEvent _TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_EVENT; extern TraceEvent _TRACE_IMX6_CCM_READ_EVENT; extern TraceEvent _TRACE_IMX6_CCM_RESET_EVENT; extern TraceEvent _TRACE_IMX6_CCM_WRITE_EVENT; extern TraceEvent _TRACE_CCM_ENTRY_EVENT; extern TraceEvent _TRACE_CCM_FREQ_EVENT; extern TraceEvent _TRACE_CCM_CLOCK_FREQ_EVENT; extern TraceEvent _TRACE_CCM_READ_REG_EVENT; extern TraceEvent _TRACE_CCM_WRITE_REG_EVENT; extern TraceEvent _TRACE_IMX7_SRC_READ_EVENT; extern TraceEvent _TRACE_IMX7_SRC_WRITE_EVENT; extern TraceEvent _TRACE_IOTKIT_SYSINFO_READ_EVENT; extern TraceEvent _TRACE_IOTKIT_SYSINFO_WRITE_EVENT; extern TraceEvent _TRACE_IOTKIT_SYSCTL_READ_EVENT; extern TraceEvent _TRACE_IOTKIT_SYSCTL_WRITE_EVENT; extern TraceEvent _TRACE_IOTKIT_SYSCTL_RESET_EVENT; extern TraceEvent _TRACE_ARMSSE_CPU_PWRCTRL_READ_EVENT; extern TraceEvent _TRACE_ARMSSE_CPU_PWRCTRL_WRITE_EVENT; extern TraceEvent _TRACE_ARMSSE_CPUID_READ_EVENT; extern TraceEvent _TRACE_ARMSSE_CPUID_WRITE_EVENT; extern TraceEvent _TRACE_ARMSSE_MHU_READ_EVENT; extern TraceEvent _TRACE_ARMSSE_MHU_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_XDMA_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_I3C_READ_EVENT; extern TraceEvent _TRACE_ASPEED_I3C_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_I3C_DEVICE_READ_EVENT; extern TraceEvent _TRACE_ASPEED_I3C_DEVICE_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_SDMC_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_SDMC_READ_EVENT; extern TraceEvent _TRACE_ASPEED_PECI_READ_EVENT; extern TraceEvent _TRACE_ASPEED_PECI_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_PECI_RAISE_INTERRUPT_EVENT; extern TraceEvent _TRACE_BCM2835_MBOX_PROPERTY_EVENT; extern TraceEvent _TRACE_BCM2835_MBOX_WRITE_EVENT; extern TraceEvent _TRACE_BCM2835_MBOX_READ_EVENT; extern TraceEvent _TRACE_BCM2835_MBOX_IRQ_EVENT; extern TraceEvent _TRACE_VIA1_RTC_UPDATE_DATA_OUT_EVENT; extern TraceEvent _TRACE_VIA1_RTC_UPDATE_DATA_IN_EVENT; extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_STATUS_EVENT; extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_CMD_EVENT; extern TraceEvent _TRACE_VIA1_RTC_CMD_INVALID_EVENT; extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_TIME_EVENT; extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_SET_CMD_EVENT; extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_EVENT; extern TraceEvent _TRACE_VIA1_RTC_INTERNAL_SET_ALT_EVENT; extern TraceEvent _TRACE_VIA1_RTC_CMD_SECONDS_READ_EVENT; extern TraceEvent _TRACE_VIA1_RTC_CMD_SECONDS_WRITE_EVENT; extern TraceEvent _TRACE_VIA1_RTC_CMD_TEST_WRITE_EVENT; extern TraceEvent _TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_EVENT; extern TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_READ_EVENT; extern TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_WRITE_EVENT; extern TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_EVENT; extern TraceEvent _TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_EVENT; extern TraceEvent _TRACE_VIA1_ADB_SEND_EVENT; extern TraceEvent _TRACE_VIA1_ADB_RECEIVE_EVENT; extern TraceEvent _TRACE_VIA1_ADB_POLL_EVENT; extern TraceEvent _TRACE_VIA1_ADB_NETBSD_ENUM_HACK_EVENT; extern TraceEvent _TRACE_VIA1_AUXMODE_EVENT; extern TraceEvent _TRACE_VIA1_TIMER_HACK_STATE_EVENT; extern TraceEvent _TRACE_GRLIB_AHB_PNP_READ_EVENT; extern TraceEvent _TRACE_GRLIB_APB_PNP_READ_EVENT; extern TraceEvent _TRACE_LED_SET_INTENSITY_EVENT; extern TraceEvent _TRACE_LED_CHANGE_INTENSITY_EVENT; extern TraceEvent _TRACE_BCM2835_CPRMAN_READ_EVENT; extern TraceEvent _TRACE_BCM2835_CPRMAN_WRITE_EVENT; extern TraceEvent _TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_EVENT; extern TraceEvent _TRACE_VIRT_CTRL_READ_EVENT; extern TraceEvent _TRACE_VIRT_CTRL_WRITE_EVENT; extern TraceEvent _TRACE_VIRT_CTRL_RESET_EVENT; extern TraceEvent _TRACE_VIRT_CTRL_REALIZE_EVENT; extern TraceEvent _TRACE_VIRT_CTRL_INSTANCE_INIT_EVENT; extern TraceEvent _TRACE_LASI_CHIP_MEM_VALID_EVENT; extern TraceEvent _TRACE_LASI_CHIP_READ_EVENT; extern TraceEvent _TRACE_LASI_CHIP_WRITE_EVENT; extern TraceEvent _TRACE_DJMEMC_READ_EVENT; extern TraceEvent _TRACE_DJMEMC_WRITE_EVENT; extern TraceEvent _TRACE_IOSB_READ_EVENT; extern TraceEvent _TRACE_IOSB_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_SLI_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_SLI_READ_EVENT; extern TraceEvent _TRACE_ASPEED_SLIIO_WRITE_EVENT; extern TraceEvent _TRACE_ASPEED_SLIIO_READ_EVENT; extern uint16_t _TRACE_ALLWINNER_CPUCFG_CPU_RESET_DSTATE; extern uint16_t _TRACE_ALLWINNER_CPUCFG_READ_DSTATE; extern uint16_t _TRACE_ALLWINNER_CPUCFG_WRITE_DSTATE; extern uint16_t _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_DSTATE; extern uint16_t _TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_DSTATE; extern uint16_t _TRACE_ALLWINNER_H3_DRAMCOM_READ_DSTATE; extern uint16_t _TRACE_ALLWINNER_H3_DRAMCOM_WRITE_DSTATE; extern uint16_t _TRACE_ALLWINNER_H3_DRAMCTL_READ_DSTATE; extern uint16_t _TRACE_ALLWINNER_H3_DRAMCTL_WRITE_DSTATE; extern uint16_t _TRACE_ALLWINNER_H3_DRAMPHY_READ_DSTATE; extern uint16_t _TRACE_ALLWINNER_H3_DRAMPHY_WRITE_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMCOM_READ_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMCOM_WRITE_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMCTL_READ_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMCTL_WRITE_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMPHY_READ_DSTATE; extern uint16_t _TRACE_ALLWINNER_R40_DRAMPHY_WRITE_DSTATE; extern uint16_t _TRACE_ALLWINNER_SID_READ_DSTATE; extern uint16_t _TRACE_ALLWINNER_SID_WRITE_DSTATE; extern uint16_t _TRACE_ALLWINNER_SRAMC_READ_DSTATE; extern uint16_t _TRACE_ALLWINNER_SRAMC_WRITE_DSTATE; extern uint16_t _TRACE_AVR_POWER_READ_DSTATE; extern uint16_t _TRACE_AVR_POWER_WRITE_DSTATE; extern uint16_t _TRACE_AXP2XX_RX_DSTATE; extern uint16_t _TRACE_AXP2XX_SELECT_DSTATE; extern uint16_t _TRACE_AXP2XX_TX_DSTATE; extern uint16_t _TRACE_ECC_MEM_WRITEL_MER_DSTATE; extern uint16_t _TRACE_ECC_MEM_WRITEL_MDR_DSTATE; extern uint16_t _TRACE_ECC_MEM_WRITEL_MFSR_DSTATE; extern uint16_t _TRACE_ECC_MEM_WRITEL_VCR_DSTATE; extern uint16_t _TRACE_ECC_MEM_WRITEL_DR_DSTATE; extern uint16_t _TRACE_ECC_MEM_WRITEL_ECR0_DSTATE; extern uint16_t _TRACE_ECC_MEM_WRITEL_ECR1_DSTATE; extern uint16_t _TRACE_ECC_MEM_READL_MER_DSTATE; extern uint16_t _TRACE_ECC_MEM_READL_MDR_DSTATE; extern uint16_t _TRACE_ECC_MEM_READL_MFSR_DSTATE; extern uint16_t _TRACE_ECC_MEM_READL_VCR_DSTATE; extern uint16_t _TRACE_ECC_MEM_READL_MFAR0_DSTATE; extern uint16_t _TRACE_ECC_MEM_READL_MFAR1_DSTATE; extern uint16_t _TRACE_ECC_MEM_READL_DR_DSTATE; extern uint16_t _TRACE_ECC_MEM_READL_ECR0_DSTATE; extern uint16_t _TRACE_ECC_MEM_READL_ECR1_DSTATE; extern uint16_t _TRACE_ECC_DIAG_MEM_WRITEB_DSTATE; extern uint16_t _TRACE_ECC_DIAG_MEM_READB_DSTATE; extern uint16_t _TRACE_EMPTY_SLOT_WRITE_DSTATE; extern uint16_t _TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_DSTATE; extern uint16_t _TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_DSTATE; extern uint16_t _TRACE_SLAVIO_SET_POWER_FAIL_DSTATE; extern uint16_t _TRACE_SLAVIO_CFG_MEM_WRITEB_DSTATE; extern uint16_t _TRACE_SLAVIO_CFG_MEM_READB_DSTATE; extern uint16_t _TRACE_SLAVIO_DIAG_MEM_WRITEB_DSTATE; extern uint16_t _TRACE_SLAVIO_DIAG_MEM_READB_DSTATE; extern uint16_t _TRACE_SLAVIO_MDM_MEM_WRITEB_DSTATE; extern uint16_t _TRACE_SLAVIO_MDM_MEM_READB_DSTATE; extern uint16_t _TRACE_SLAVIO_AUX1_MEM_WRITEB_DSTATE; extern uint16_t _TRACE_SLAVIO_AUX1_MEM_READB_DSTATE; extern uint16_t _TRACE_SLAVIO_AUX2_MEM_WRITEB_DSTATE; extern uint16_t _TRACE_SLAVIO_AUX2_MEM_READB_DSTATE; extern uint16_t _TRACE_APC_MEM_WRITEB_DSTATE; extern uint16_t _TRACE_APC_MEM_READB_DSTATE; extern uint16_t _TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_DSTATE; extern uint16_t _TRACE_SLAVIO_SYSCTRL_MEM_READL_DSTATE; extern uint16_t _TRACE_SLAVIO_LED_MEM_WRITEW_DSTATE; extern uint16_t _TRACE_SLAVIO_LED_MEM_READW_DSTATE; extern uint16_t _TRACE_ASPEED_SCU_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_SCU_READ_DSTATE; extern uint16_t _TRACE_ASPEED_AST2700_SCU_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_AST2700_SCU_READ_DSTATE; extern uint16_t _TRACE_ASPEED_AST2700_SCUIO_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_AST2700_SCUIO_READ_DSTATE; extern uint16_t _TRACE_MPS2_SCC_READ_DSTATE; extern uint16_t _TRACE_MPS2_SCC_WRITE_DSTATE; extern uint16_t _TRACE_MPS2_SCC_RESET_DSTATE; extern uint16_t _TRACE_MPS2_SCC_CFG_WRITE_DSTATE; extern uint16_t _TRACE_MPS2_SCC_CFG_READ_DSTATE; extern uint16_t _TRACE_MPS2_FPGAIO_READ_DSTATE; extern uint16_t _TRACE_MPS2_FPGAIO_WRITE_DSTATE; extern uint16_t _TRACE_MPS2_FPGAIO_RESET_DSTATE; extern uint16_t _TRACE_MSF2_SYSREG_WRITE_DSTATE; extern uint16_t _TRACE_MSF2_SYSREG_READ_DSTATE; extern uint16_t _TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_DSTATE; extern uint16_t _TRACE_IMX7_GPR_READ_DSTATE; extern uint16_t _TRACE_IMX7_GPR_WRITE_DSTATE; extern uint16_t _TRACE_IMX7_SNVS_READ_DSTATE; extern uint16_t _TRACE_IMX7_SNVS_WRITE_DSTATE; extern uint16_t _TRACE_MOS6522_SET_COUNTER_DSTATE; extern uint16_t _TRACE_MOS6522_GET_NEXT_IRQ_TIME_DSTATE; extern uint16_t _TRACE_MOS6522_SET_SR_INT_DSTATE; extern uint16_t _TRACE_MOS6522_WRITE_DSTATE; extern uint16_t _TRACE_MOS6522_READ_DSTATE; extern uint16_t _TRACE_NPCM7XX_CLK_READ_DSTATE; extern uint16_t _TRACE_NPCM7XX_CLK_WRITE_DSTATE; extern uint16_t _TRACE_NPCM7XX_GCR_READ_DSTATE; extern uint16_t _TRACE_NPCM7XX_GCR_WRITE_DSTATE; extern uint16_t _TRACE_NPCM7XX_MFT_READ_DSTATE; extern uint16_t _TRACE_NPCM7XX_MFT_WRITE_DSTATE; extern uint16_t _TRACE_NPCM7XX_MFT_RPM_DSTATE; extern uint16_t _TRACE_NPCM7XX_MFT_CAPTURE_DSTATE; extern uint16_t _TRACE_NPCM7XX_MFT_UPDATE_CLOCK_DSTATE; extern uint16_t _TRACE_NPCM7XX_MFT_SET_DUTY_DSTATE; extern uint16_t _TRACE_NPCM7XX_RNG_READ_DSTATE; extern uint16_t _TRACE_NPCM7XX_RNG_WRITE_DSTATE; extern uint16_t _TRACE_NPCM7XX_PWM_READ_DSTATE; extern uint16_t _TRACE_NPCM7XX_PWM_WRITE_DSTATE; extern uint16_t _TRACE_NPCM7XX_PWM_UPDATE_FREQ_DSTATE; extern uint16_t _TRACE_NPCM7XX_PWM_UPDATE_DUTY_DSTATE; extern uint16_t _TRACE_STM32_RCC_READ_DSTATE; extern uint16_t _TRACE_STM32_RCC_WRITE_DSTATE; extern uint16_t _TRACE_STM32_RCC_PULSE_ENABLE_DSTATE; extern uint16_t _TRACE_STM32_RCC_PULSE_RESET_DSTATE; extern uint16_t _TRACE_STM32F4XX_SYSCFG_SET_IRQ_DSTATE; extern uint16_t _TRACE_STM32F4XX_PULSE_EXTI_DSTATE; extern uint16_t _TRACE_STM32F4XX_SYSCFG_READ_DSTATE; extern uint16_t _TRACE_STM32F4XX_SYSCFG_WRITE_DSTATE; extern uint16_t _TRACE_STM32F4XX_EXTI_SET_IRQ_DSTATE; extern uint16_t _TRACE_STM32F4XX_EXTI_READ_DSTATE; extern uint16_t _TRACE_STM32F4XX_EXTI_WRITE_DSTATE; extern uint16_t _TRACE_STM32L4X5_SYSCFG_SET_IRQ_DSTATE; extern uint16_t _TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_DSTATE; extern uint16_t _TRACE_STM32L4X5_SYSCFG_READ_DSTATE; extern uint16_t _TRACE_STM32L4X5_SYSCFG_WRITE_DSTATE; extern uint16_t _TRACE_STM32L4X5_EXTI_SET_IRQ_DSTATE; extern uint16_t _TRACE_STM32L4X5_EXTI_READ_DSTATE; extern uint16_t _TRACE_STM32L4X5_EXTI_WRITE_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_READ_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_WRITE_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_MUX_ENABLE_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_MUX_DISABLE_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_MUX_SET_SRC_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_MUX_UPDATE_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_DSTATE; extern uint16_t _TRACE_STM32L4X5_RCC_PLL_UPDATE_DSTATE; extern uint16_t _TRACE_TZ_MPC_REG_READ_DSTATE; extern uint16_t _TRACE_TZ_MPC_REG_WRITE_DSTATE; extern uint16_t _TRACE_TZ_MPC_MEM_BLOCKED_READ_DSTATE; extern uint16_t _TRACE_TZ_MPC_MEM_BLOCKED_WRITE_DSTATE; extern uint16_t _TRACE_TZ_MPC_TRANSLATE_DSTATE; extern uint16_t _TRACE_TZ_MPC_IOMMU_NOTIFY_DSTATE; extern uint16_t _TRACE_TZ_MSC_RESET_DSTATE; extern uint16_t _TRACE_TZ_MSC_CFG_NONSEC_DSTATE; extern uint16_t _TRACE_TZ_MSC_CFG_SEC_RESP_DSTATE; extern uint16_t _TRACE_TZ_MSC_IRQ_CLEAR_DSTATE; extern uint16_t _TRACE_TZ_MSC_UPDATE_IRQ_DSTATE; extern uint16_t _TRACE_TZ_MSC_ACCESS_BLOCKED_DSTATE; extern uint16_t _TRACE_TZ_PPC_RESET_DSTATE; extern uint16_t _TRACE_TZ_PPC_CFG_NONSEC_DSTATE; extern uint16_t _TRACE_TZ_PPC_CFG_AP_DSTATE; extern uint16_t _TRACE_TZ_PPC_CFG_SEC_RESP_DSTATE; extern uint16_t _TRACE_TZ_PPC_IRQ_ENABLE_DSTATE; extern uint16_t _TRACE_TZ_PPC_IRQ_CLEAR_DSTATE; extern uint16_t _TRACE_TZ_PPC_UPDATE_IRQ_DSTATE; extern uint16_t _TRACE_TZ_PPC_READ_BLOCKED_DSTATE; extern uint16_t _TRACE_TZ_PPC_WRITE_BLOCKED_DSTATE; extern uint16_t _TRACE_IOTKIT_SECCTL_S_READ_DSTATE; extern uint16_t _TRACE_IOTKIT_SECCTL_S_WRITE_DSTATE; extern uint16_t _TRACE_IOTKIT_SECCTL_NS_READ_DSTATE; extern uint16_t _TRACE_IOTKIT_SECCTL_NS_WRITE_DSTATE; extern uint16_t _TRACE_IMX6_ANALOG_GET_PERIPH_CLK_DSTATE; extern uint16_t _TRACE_IMX6_ANALOG_GET_PLL2_CLK_DSTATE; extern uint16_t _TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_DSTATE; extern uint16_t _TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_DSTATE; extern uint16_t _TRACE_IMX6_ANALOG_READ_DSTATE; extern uint16_t _TRACE_IMX6_ANALOG_WRITE_DSTATE; extern uint16_t _TRACE_IMX6_CCM_GET_AHB_CLK_DSTATE; extern uint16_t _TRACE_IMX6_CCM_GET_IPG_CLK_DSTATE; extern uint16_t _TRACE_IMX6_CCM_GET_PER_CLK_DSTATE; extern uint16_t _TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_DSTATE; extern uint16_t _TRACE_IMX6_CCM_READ_DSTATE; extern uint16_t _TRACE_IMX6_CCM_RESET_DSTATE; extern uint16_t _TRACE_IMX6_CCM_WRITE_DSTATE; extern uint16_t _TRACE_CCM_ENTRY_DSTATE; extern uint16_t _TRACE_CCM_FREQ_DSTATE; extern uint16_t _TRACE_CCM_CLOCK_FREQ_DSTATE; extern uint16_t _TRACE_CCM_READ_REG_DSTATE; extern uint16_t _TRACE_CCM_WRITE_REG_DSTATE; extern uint16_t _TRACE_IMX7_SRC_READ_DSTATE; extern uint16_t _TRACE_IMX7_SRC_WRITE_DSTATE; extern uint16_t _TRACE_IOTKIT_SYSINFO_READ_DSTATE; extern uint16_t _TRACE_IOTKIT_SYSINFO_WRITE_DSTATE; extern uint16_t _TRACE_IOTKIT_SYSCTL_READ_DSTATE; extern uint16_t _TRACE_IOTKIT_SYSCTL_WRITE_DSTATE; extern uint16_t _TRACE_IOTKIT_SYSCTL_RESET_DSTATE; extern uint16_t _TRACE_ARMSSE_CPU_PWRCTRL_READ_DSTATE; extern uint16_t _TRACE_ARMSSE_CPU_PWRCTRL_WRITE_DSTATE; extern uint16_t _TRACE_ARMSSE_CPUID_READ_DSTATE; extern uint16_t _TRACE_ARMSSE_CPUID_WRITE_DSTATE; extern uint16_t _TRACE_ARMSSE_MHU_READ_DSTATE; extern uint16_t _TRACE_ARMSSE_MHU_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_XDMA_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_I3C_READ_DSTATE; extern uint16_t _TRACE_ASPEED_I3C_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_I3C_DEVICE_READ_DSTATE; extern uint16_t _TRACE_ASPEED_I3C_DEVICE_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_SDMC_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_SDMC_READ_DSTATE; extern uint16_t _TRACE_ASPEED_PECI_READ_DSTATE; extern uint16_t _TRACE_ASPEED_PECI_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_PECI_RAISE_INTERRUPT_DSTATE; extern uint16_t _TRACE_BCM2835_MBOX_PROPERTY_DSTATE; extern uint16_t _TRACE_BCM2835_MBOX_WRITE_DSTATE; extern uint16_t _TRACE_BCM2835_MBOX_READ_DSTATE; extern uint16_t _TRACE_BCM2835_MBOX_IRQ_DSTATE; extern uint16_t _TRACE_VIA1_RTC_UPDATE_DATA_OUT_DSTATE; extern uint16_t _TRACE_VIA1_RTC_UPDATE_DATA_IN_DSTATE; extern uint16_t _TRACE_VIA1_RTC_INTERNAL_STATUS_DSTATE; extern uint16_t _TRACE_VIA1_RTC_INTERNAL_CMD_DSTATE; extern uint16_t _TRACE_VIA1_RTC_CMD_INVALID_DSTATE; extern uint16_t _TRACE_VIA1_RTC_INTERNAL_TIME_DSTATE; extern uint16_t _TRACE_VIA1_RTC_INTERNAL_SET_CMD_DSTATE; extern uint16_t _TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_DSTATE; extern uint16_t _TRACE_VIA1_RTC_INTERNAL_SET_ALT_DSTATE; extern uint16_t _TRACE_VIA1_RTC_CMD_SECONDS_READ_DSTATE; extern uint16_t _TRACE_VIA1_RTC_CMD_SECONDS_WRITE_DSTATE; extern uint16_t _TRACE_VIA1_RTC_CMD_TEST_WRITE_DSTATE; extern uint16_t _TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_DSTATE; extern uint16_t _TRACE_VIA1_RTC_CMD_PRAM_READ_DSTATE; extern uint16_t _TRACE_VIA1_RTC_CMD_PRAM_WRITE_DSTATE; extern uint16_t _TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_DSTATE; extern uint16_t _TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_DSTATE; extern uint16_t _TRACE_VIA1_ADB_SEND_DSTATE; extern uint16_t _TRACE_VIA1_ADB_RECEIVE_DSTATE; extern uint16_t _TRACE_VIA1_ADB_POLL_DSTATE; extern uint16_t _TRACE_VIA1_ADB_NETBSD_ENUM_HACK_DSTATE; extern uint16_t _TRACE_VIA1_AUXMODE_DSTATE; extern uint16_t _TRACE_VIA1_TIMER_HACK_STATE_DSTATE; extern uint16_t _TRACE_GRLIB_AHB_PNP_READ_DSTATE; extern uint16_t _TRACE_GRLIB_APB_PNP_READ_DSTATE; extern uint16_t _TRACE_LED_SET_INTENSITY_DSTATE; extern uint16_t _TRACE_LED_CHANGE_INTENSITY_DSTATE; extern uint16_t _TRACE_BCM2835_CPRMAN_READ_DSTATE; extern uint16_t _TRACE_BCM2835_CPRMAN_WRITE_DSTATE; extern uint16_t _TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_DSTATE; extern uint16_t _TRACE_VIRT_CTRL_READ_DSTATE; extern uint16_t _TRACE_VIRT_CTRL_WRITE_DSTATE; extern uint16_t _TRACE_VIRT_CTRL_RESET_DSTATE; extern uint16_t _TRACE_VIRT_CTRL_REALIZE_DSTATE; extern uint16_t _TRACE_VIRT_CTRL_INSTANCE_INIT_DSTATE; extern uint16_t _TRACE_LASI_CHIP_MEM_VALID_DSTATE; extern uint16_t _TRACE_LASI_CHIP_READ_DSTATE; extern uint16_t _TRACE_LASI_CHIP_WRITE_DSTATE; extern uint16_t _TRACE_DJMEMC_READ_DSTATE; extern uint16_t _TRACE_DJMEMC_WRITE_DSTATE; extern uint16_t _TRACE_IOSB_READ_DSTATE; extern uint16_t _TRACE_IOSB_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_SLI_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_SLI_READ_DSTATE; extern uint16_t _TRACE_ASPEED_SLIIO_WRITE_DSTATE; extern uint16_t _TRACE_ASPEED_SLIIO_READ_DSTATE; #define TRACE_ALLWINNER_CPUCFG_CPU_RESET_ENABLED 1 #define TRACE_ALLWINNER_CPUCFG_READ_ENABLED 1 #define TRACE_ALLWINNER_CPUCFG_WRITE_ENABLED 1 #define TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_ENABLED 1 #define TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_ENABLED 1 #define TRACE_ALLWINNER_H3_DRAMCOM_READ_ENABLED 1 #define TRACE_ALLWINNER_H3_DRAMCOM_WRITE_ENABLED 1 #define TRACE_ALLWINNER_H3_DRAMCTL_READ_ENABLED 1 #define TRACE_ALLWINNER_H3_DRAMCTL_WRITE_ENABLED 1 #define TRACE_ALLWINNER_H3_DRAMPHY_READ_ENABLED 1 #define TRACE_ALLWINNER_H3_DRAMPHY_WRITE_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMCOM_READ_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMCOM_WRITE_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMCTL_READ_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMCTL_WRITE_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMPHY_READ_ENABLED 1 #define TRACE_ALLWINNER_R40_DRAMPHY_WRITE_ENABLED 1 #define TRACE_ALLWINNER_SID_READ_ENABLED 1 #define TRACE_ALLWINNER_SID_WRITE_ENABLED 1 #define TRACE_ALLWINNER_SRAMC_READ_ENABLED 1 #define TRACE_ALLWINNER_SRAMC_WRITE_ENABLED 1 #define TRACE_AVR_POWER_READ_ENABLED 1 #define TRACE_AVR_POWER_WRITE_ENABLED 1 #define TRACE_AXP2XX_RX_ENABLED 1 #define TRACE_AXP2XX_SELECT_ENABLED 1 #define TRACE_AXP2XX_TX_ENABLED 1 #define TRACE_ECC_MEM_WRITEL_MER_ENABLED 1 #define TRACE_ECC_MEM_WRITEL_MDR_ENABLED 1 #define TRACE_ECC_MEM_WRITEL_MFSR_ENABLED 1 #define TRACE_ECC_MEM_WRITEL_VCR_ENABLED 1 #define TRACE_ECC_MEM_WRITEL_DR_ENABLED 1 #define TRACE_ECC_MEM_WRITEL_ECR0_ENABLED 1 #define TRACE_ECC_MEM_WRITEL_ECR1_ENABLED 1 #define TRACE_ECC_MEM_READL_MER_ENABLED 1 #define TRACE_ECC_MEM_READL_MDR_ENABLED 1 #define TRACE_ECC_MEM_READL_MFSR_ENABLED 1 #define TRACE_ECC_MEM_READL_VCR_ENABLED 1 #define TRACE_ECC_MEM_READL_MFAR0_ENABLED 1 #define TRACE_ECC_MEM_READL_MFAR1_ENABLED 1 #define TRACE_ECC_MEM_READL_DR_ENABLED 1 #define TRACE_ECC_MEM_READL_ECR0_ENABLED 1 #define TRACE_ECC_MEM_READL_ECR1_ENABLED 1 #define TRACE_ECC_DIAG_MEM_WRITEB_ENABLED 1 #define TRACE_ECC_DIAG_MEM_READB_ENABLED 1 #define TRACE_EMPTY_SLOT_WRITE_ENABLED 1 #define TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_ENABLED 1 #define TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_ENABLED 1 #define TRACE_SLAVIO_SET_POWER_FAIL_ENABLED 1 #define TRACE_SLAVIO_CFG_MEM_WRITEB_ENABLED 1 #define TRACE_SLAVIO_CFG_MEM_READB_ENABLED 1 #define TRACE_SLAVIO_DIAG_MEM_WRITEB_ENABLED 1 #define TRACE_SLAVIO_DIAG_MEM_READB_ENABLED 1 #define TRACE_SLAVIO_MDM_MEM_WRITEB_ENABLED 1 #define TRACE_SLAVIO_MDM_MEM_READB_ENABLED 1 #define TRACE_SLAVIO_AUX1_MEM_WRITEB_ENABLED 1 #define TRACE_SLAVIO_AUX1_MEM_READB_ENABLED 1 #define TRACE_SLAVIO_AUX2_MEM_WRITEB_ENABLED 1 #define TRACE_SLAVIO_AUX2_MEM_READB_ENABLED 1 #define TRACE_APC_MEM_WRITEB_ENABLED 1 #define TRACE_APC_MEM_READB_ENABLED 1 #define TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_ENABLED 1 #define TRACE_SLAVIO_SYSCTRL_MEM_READL_ENABLED 1 #define TRACE_SLAVIO_LED_MEM_WRITEW_ENABLED 1 #define TRACE_SLAVIO_LED_MEM_READW_ENABLED 1 #define TRACE_ASPEED_SCU_WRITE_ENABLED 1 #define TRACE_ASPEED_SCU_READ_ENABLED 1 #define TRACE_ASPEED_AST2700_SCU_WRITE_ENABLED 1 #define TRACE_ASPEED_AST2700_SCU_READ_ENABLED 1 #define TRACE_ASPEED_AST2700_SCUIO_WRITE_ENABLED 1 #define TRACE_ASPEED_AST2700_SCUIO_READ_ENABLED 1 #define TRACE_MPS2_SCC_READ_ENABLED 1 #define TRACE_MPS2_SCC_WRITE_ENABLED 1 #define TRACE_MPS2_SCC_RESET_ENABLED 1 #define TRACE_MPS2_SCC_CFG_WRITE_ENABLED 1 #define TRACE_MPS2_SCC_CFG_READ_ENABLED 1 #define TRACE_MPS2_FPGAIO_READ_ENABLED 1 #define TRACE_MPS2_FPGAIO_WRITE_ENABLED 1 #define TRACE_MPS2_FPGAIO_RESET_ENABLED 1 #define TRACE_MSF2_SYSREG_WRITE_ENABLED 1 #define TRACE_MSF2_SYSREG_READ_ENABLED 1 #define TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_ENABLED 1 #define TRACE_IMX7_GPR_READ_ENABLED 1 #define TRACE_IMX7_GPR_WRITE_ENABLED 1 #define TRACE_IMX7_SNVS_READ_ENABLED 1 #define TRACE_IMX7_SNVS_WRITE_ENABLED 1 #define TRACE_MOS6522_SET_COUNTER_ENABLED 1 #define TRACE_MOS6522_GET_NEXT_IRQ_TIME_ENABLED 1 #define TRACE_MOS6522_SET_SR_INT_ENABLED 1 #define TRACE_MOS6522_WRITE_ENABLED 1 #define TRACE_MOS6522_READ_ENABLED 1 #define TRACE_NPCM7XX_CLK_READ_ENABLED 1 #define TRACE_NPCM7XX_CLK_WRITE_ENABLED 1 #define TRACE_NPCM7XX_GCR_READ_ENABLED 1 #define TRACE_NPCM7XX_GCR_WRITE_ENABLED 1 #define TRACE_NPCM7XX_MFT_READ_ENABLED 1 #define TRACE_NPCM7XX_MFT_WRITE_ENABLED 1 #define TRACE_NPCM7XX_MFT_RPM_ENABLED 1 #define TRACE_NPCM7XX_MFT_CAPTURE_ENABLED 1 #define TRACE_NPCM7XX_MFT_UPDATE_CLOCK_ENABLED 1 #define TRACE_NPCM7XX_MFT_SET_DUTY_ENABLED 1 #define TRACE_NPCM7XX_RNG_READ_ENABLED 1 #define TRACE_NPCM7XX_RNG_WRITE_ENABLED 1 #define TRACE_NPCM7XX_PWM_READ_ENABLED 1 #define TRACE_NPCM7XX_PWM_WRITE_ENABLED 1 #define TRACE_NPCM7XX_PWM_UPDATE_FREQ_ENABLED 1 #define TRACE_NPCM7XX_PWM_UPDATE_DUTY_ENABLED 1 #define TRACE_STM32_RCC_READ_ENABLED 1 #define TRACE_STM32_RCC_WRITE_ENABLED 1 #define TRACE_STM32_RCC_PULSE_ENABLE_ENABLED 1 #define TRACE_STM32_RCC_PULSE_RESET_ENABLED 1 #define TRACE_STM32F4XX_SYSCFG_SET_IRQ_ENABLED 1 #define TRACE_STM32F4XX_PULSE_EXTI_ENABLED 1 #define TRACE_STM32F4XX_SYSCFG_READ_ENABLED 1 #define TRACE_STM32F4XX_SYSCFG_WRITE_ENABLED 1 #define TRACE_STM32F4XX_EXTI_SET_IRQ_ENABLED 1 #define TRACE_STM32F4XX_EXTI_READ_ENABLED 1 #define TRACE_STM32F4XX_EXTI_WRITE_ENABLED 1 #define TRACE_STM32L4X5_SYSCFG_SET_IRQ_ENABLED 1 #define TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_ENABLED 1 #define TRACE_STM32L4X5_SYSCFG_READ_ENABLED 1 #define TRACE_STM32L4X5_SYSCFG_WRITE_ENABLED 1 #define TRACE_STM32L4X5_EXTI_SET_IRQ_ENABLED 1 #define TRACE_STM32L4X5_EXTI_READ_ENABLED 1 #define TRACE_STM32L4X5_EXTI_WRITE_ENABLED 1 #define TRACE_STM32L4X5_RCC_READ_ENABLED 1 #define TRACE_STM32L4X5_RCC_WRITE_ENABLED 1 #define TRACE_STM32L4X5_RCC_MUX_ENABLE_ENABLED 1 #define TRACE_STM32L4X5_RCC_MUX_DISABLE_ENABLED 1 #define TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_ENABLED 1 #define TRACE_STM32L4X5_RCC_MUX_SET_SRC_ENABLED 1 #define TRACE_STM32L4X5_RCC_MUX_UPDATE_ENABLED 1 #define TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_ENABLED 1 #define TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_ENABLED 1 #define TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_ENABLED 1 #define TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_ENABLED 1 #define TRACE_STM32L4X5_RCC_PLL_UPDATE_ENABLED 1 #define TRACE_TZ_MPC_REG_READ_ENABLED 1 #define TRACE_TZ_MPC_REG_WRITE_ENABLED 1 #define TRACE_TZ_MPC_MEM_BLOCKED_READ_ENABLED 1 #define TRACE_TZ_MPC_MEM_BLOCKED_WRITE_ENABLED 1 #define TRACE_TZ_MPC_TRANSLATE_ENABLED 1 #define TRACE_TZ_MPC_IOMMU_NOTIFY_ENABLED 1 #define TRACE_TZ_MSC_RESET_ENABLED 1 #define TRACE_TZ_MSC_CFG_NONSEC_ENABLED 1 #define TRACE_TZ_MSC_CFG_SEC_RESP_ENABLED 1 #define TRACE_TZ_MSC_IRQ_CLEAR_ENABLED 1 #define TRACE_TZ_MSC_UPDATE_IRQ_ENABLED 1 #define TRACE_TZ_MSC_ACCESS_BLOCKED_ENABLED 1 #define TRACE_TZ_PPC_RESET_ENABLED 1 #define TRACE_TZ_PPC_CFG_NONSEC_ENABLED 1 #define TRACE_TZ_PPC_CFG_AP_ENABLED 1 #define TRACE_TZ_PPC_CFG_SEC_RESP_ENABLED 1 #define TRACE_TZ_PPC_IRQ_ENABLE_ENABLED 1 #define TRACE_TZ_PPC_IRQ_CLEAR_ENABLED 1 #define TRACE_TZ_PPC_UPDATE_IRQ_ENABLED 1 #define TRACE_TZ_PPC_READ_BLOCKED_ENABLED 1 #define TRACE_TZ_PPC_WRITE_BLOCKED_ENABLED 1 #define TRACE_IOTKIT_SECCTL_S_READ_ENABLED 1 #define TRACE_IOTKIT_SECCTL_S_WRITE_ENABLED 1 #define TRACE_IOTKIT_SECCTL_NS_READ_ENABLED 1 #define TRACE_IOTKIT_SECCTL_NS_WRITE_ENABLED 1 #define TRACE_IMX6_ANALOG_GET_PERIPH_CLK_ENABLED 1 #define TRACE_IMX6_ANALOG_GET_PLL2_CLK_ENABLED 1 #define TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_ENABLED 1 #define TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_ENABLED 1 #define TRACE_IMX6_ANALOG_READ_ENABLED 1 #define TRACE_IMX6_ANALOG_WRITE_ENABLED 1 #define TRACE_IMX6_CCM_GET_AHB_CLK_ENABLED 1 #define TRACE_IMX6_CCM_GET_IPG_CLK_ENABLED 1 #define TRACE_IMX6_CCM_GET_PER_CLK_ENABLED 1 #define TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_ENABLED 1 #define TRACE_IMX6_CCM_READ_ENABLED 1 #define TRACE_IMX6_CCM_RESET_ENABLED 1 #define TRACE_IMX6_CCM_WRITE_ENABLED 1 #define TRACE_CCM_ENTRY_ENABLED 1 #define TRACE_CCM_FREQ_ENABLED 1 #define TRACE_CCM_CLOCK_FREQ_ENABLED 1 #define TRACE_CCM_READ_REG_ENABLED 1 #define TRACE_CCM_WRITE_REG_ENABLED 1 #define TRACE_IMX7_SRC_READ_ENABLED 1 #define TRACE_IMX7_SRC_WRITE_ENABLED 1 #define TRACE_IOTKIT_SYSINFO_READ_ENABLED 1 #define TRACE_IOTKIT_SYSINFO_WRITE_ENABLED 1 #define TRACE_IOTKIT_SYSCTL_READ_ENABLED 1 #define TRACE_IOTKIT_SYSCTL_WRITE_ENABLED 1 #define TRACE_IOTKIT_SYSCTL_RESET_ENABLED 1 #define TRACE_ARMSSE_CPU_PWRCTRL_READ_ENABLED 1 #define TRACE_ARMSSE_CPU_PWRCTRL_WRITE_ENABLED 1 #define TRACE_ARMSSE_CPUID_READ_ENABLED 1 #define TRACE_ARMSSE_CPUID_WRITE_ENABLED 1 #define TRACE_ARMSSE_MHU_READ_ENABLED 1 #define TRACE_ARMSSE_MHU_WRITE_ENABLED 1 #define TRACE_ASPEED_XDMA_WRITE_ENABLED 1 #define TRACE_ASPEED_I3C_READ_ENABLED 1 #define TRACE_ASPEED_I3C_WRITE_ENABLED 1 #define TRACE_ASPEED_I3C_DEVICE_READ_ENABLED 1 #define TRACE_ASPEED_I3C_DEVICE_WRITE_ENABLED 1 #define TRACE_ASPEED_SDMC_WRITE_ENABLED 1 #define TRACE_ASPEED_SDMC_READ_ENABLED 1 #define TRACE_ASPEED_PECI_READ_ENABLED 1 #define TRACE_ASPEED_PECI_WRITE_ENABLED 1 #define TRACE_ASPEED_PECI_RAISE_INTERRUPT_ENABLED 1 #define TRACE_BCM2835_MBOX_PROPERTY_ENABLED 1 #define TRACE_BCM2835_MBOX_WRITE_ENABLED 1 #define TRACE_BCM2835_MBOX_READ_ENABLED 1 #define TRACE_BCM2835_MBOX_IRQ_ENABLED 1 #define TRACE_VIA1_RTC_UPDATE_DATA_OUT_ENABLED 1 #define TRACE_VIA1_RTC_UPDATE_DATA_IN_ENABLED 1 #define TRACE_VIA1_RTC_INTERNAL_STATUS_ENABLED 1 #define TRACE_VIA1_RTC_INTERNAL_CMD_ENABLED 1 #define TRACE_VIA1_RTC_CMD_INVALID_ENABLED 1 #define TRACE_VIA1_RTC_INTERNAL_TIME_ENABLED 1 #define TRACE_VIA1_RTC_INTERNAL_SET_CMD_ENABLED 1 #define TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_ENABLED 1 #define TRACE_VIA1_RTC_INTERNAL_SET_ALT_ENABLED 1 #define TRACE_VIA1_RTC_CMD_SECONDS_READ_ENABLED 1 #define TRACE_VIA1_RTC_CMD_SECONDS_WRITE_ENABLED 1 #define TRACE_VIA1_RTC_CMD_TEST_WRITE_ENABLED 1 #define TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_ENABLED 1 #define TRACE_VIA1_RTC_CMD_PRAM_READ_ENABLED 1 #define TRACE_VIA1_RTC_CMD_PRAM_WRITE_ENABLED 1 #define TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_ENABLED 1 #define TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_ENABLED 1 #define TRACE_VIA1_ADB_SEND_ENABLED 1 #define TRACE_VIA1_ADB_RECEIVE_ENABLED 1 #define TRACE_VIA1_ADB_POLL_ENABLED 1 #define TRACE_VIA1_ADB_NETBSD_ENUM_HACK_ENABLED 1 #define TRACE_VIA1_AUXMODE_ENABLED 1 #define TRACE_VIA1_TIMER_HACK_STATE_ENABLED 1 #define TRACE_GRLIB_AHB_PNP_READ_ENABLED 1 #define TRACE_GRLIB_APB_PNP_READ_ENABLED 1 #define TRACE_LED_SET_INTENSITY_ENABLED 1 #define TRACE_LED_CHANGE_INTENSITY_ENABLED 1 #define TRACE_BCM2835_CPRMAN_READ_ENABLED 1 #define TRACE_BCM2835_CPRMAN_WRITE_ENABLED 1 #define TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_ENABLED 1 #define TRACE_VIRT_CTRL_READ_ENABLED 1 #define TRACE_VIRT_CTRL_WRITE_ENABLED 1 #define TRACE_VIRT_CTRL_RESET_ENABLED 1 #define TRACE_VIRT_CTRL_REALIZE_ENABLED 1 #define TRACE_VIRT_CTRL_INSTANCE_INIT_ENABLED 1 #define TRACE_LASI_CHIP_MEM_VALID_ENABLED 1 #define TRACE_LASI_CHIP_READ_ENABLED 1 #define TRACE_LASI_CHIP_WRITE_ENABLED 1 #define TRACE_DJMEMC_READ_ENABLED 1 #define TRACE_DJMEMC_WRITE_ENABLED 1 #define TRACE_IOSB_READ_ENABLED 1 #define TRACE_IOSB_WRITE_ENABLED 1 #define TRACE_ASPEED_SLI_WRITE_ENABLED 1 #define TRACE_ASPEED_SLI_READ_ENABLED 1 #define TRACE_ASPEED_SLIIO_WRITE_ENABLED 1 #define TRACE_ASPEED_SLIIO_READ_ENABLED 1 #include "qemu/log-for-trace.h" #include "qemu/error-report.h" #define TRACE_ALLWINNER_CPUCFG_CPU_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_CPUCFG_CPU_RESET) || \ false) static inline void _nocheck__trace_allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) { if (trace_event_get_state(TRACE_ALLWINNER_CPUCFG_CPU_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 4 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_cpucfg_cpu_reset " "id %u, reset_addr 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cpu_id, reset_addr); #line 802 "trace/trace-hw_misc.h" } else { #line 4 "../hw/misc/trace-events" qemu_log("allwinner_cpucfg_cpu_reset " "id %u, reset_addr 0x%" PRIx32 "\n", cpu_id, reset_addr); #line 806 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) { if (true) { _nocheck__trace_allwinner_cpucfg_cpu_reset(cpu_id, reset_addr); } } #define TRACE_ALLWINNER_CPUCFG_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_CPUCFG_READ) || \ false) static inline void _nocheck__trace_allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_CPUCFG_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 5 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_cpucfg_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 833 "trace/trace-hw_misc.h" } else { #line 5 "../hw/misc/trace-events" qemu_log("allwinner_cpucfg_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 837 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_cpucfg_read(offset, data, size); } } #define TRACE_ALLWINNER_CPUCFG_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_CPUCFG_WRITE) || \ false) static inline void _nocheck__trace_allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_CPUCFG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 6 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_cpucfg_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 864 "trace/trace-hw_misc.h" } else { #line 6 "../hw/misc/trace-events" qemu_log("allwinner_cpucfg_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 868 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_cpucfg_write(offset, data, size); } } #define TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE) || \ false) static inline void _nocheck__trace_allwinner_h3_dramc_rowmirror_disable(void) { if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_DISABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 9 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_h3_dramc_rowmirror_disable " "Disable row mirror" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 895 "trace/trace-hw_misc.h" } else { #line 9 "../hw/misc/trace-events" qemu_log("allwinner_h3_dramc_rowmirror_disable " "Disable row mirror" "\n"); #line 899 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_h3_dramc_rowmirror_disable(void) { if (true) { _nocheck__trace_allwinner_h3_dramc_rowmirror_disable(); } } #define TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE) || \ false) static inline void _nocheck__trace_allwinner_h3_dramc_rowmirror_enable(uint64_t addr) { if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMC_ROWMIRROR_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 10 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_h3_dramc_rowmirror_enable " "Enable row mirror: addr 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr); #line 926 "trace/trace-hw_misc.h" } else { #line 10 "../hw/misc/trace-events" qemu_log("allwinner_h3_dramc_rowmirror_enable " "Enable row mirror: addr 0x%" PRIx64 "\n", addr); #line 930 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_h3_dramc_rowmirror_enable(uint64_t addr) { if (true) { _nocheck__trace_allwinner_h3_dramc_rowmirror_enable(addr); } } #define TRACE_ALLWINNER_H3_DRAMCOM_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMCOM_READ) || \ false) static inline void _nocheck__trace_allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMCOM_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 11 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_h3_dramcom_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 957 "trace/trace-hw_misc.h" } else { #line 11 "../hw/misc/trace-events" qemu_log("allwinner_h3_dramcom_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 961 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_h3_dramcom_read(offset, data, size); } } #define TRACE_ALLWINNER_H3_DRAMCOM_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMCOM_WRITE) || \ false) static inline void _nocheck__trace_allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMCOM_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 12 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_h3_dramcom_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 988 "trace/trace-hw_misc.h" } else { #line 12 "../hw/misc/trace-events" qemu_log("allwinner_h3_dramcom_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 992 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_h3_dramcom_write(offset, data, size); } } #define TRACE_ALLWINNER_H3_DRAMCTL_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMCTL_READ) || \ false) static inline void _nocheck__trace_allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMCTL_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 13 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_h3_dramctl_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1019 "trace/trace-hw_misc.h" } else { #line 13 "../hw/misc/trace-events" qemu_log("allwinner_h3_dramctl_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1023 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_h3_dramctl_read(offset, data, size); } } #define TRACE_ALLWINNER_H3_DRAMCTL_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMCTL_WRITE) || \ false) static inline void _nocheck__trace_allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMCTL_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 14 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_h3_dramctl_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1050 "trace/trace-hw_misc.h" } else { #line 14 "../hw/misc/trace-events" qemu_log("allwinner_h3_dramctl_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1054 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_h3_dramctl_write(offset, data, size); } } #define TRACE_ALLWINNER_H3_DRAMPHY_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMPHY_READ) || \ false) static inline void _nocheck__trace_allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMPHY_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 15 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_h3_dramphy_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1081 "trace/trace-hw_misc.h" } else { #line 15 "../hw/misc/trace-events" qemu_log("allwinner_h3_dramphy_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1085 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_h3_dramphy_read(offset, data, size); } } #define TRACE_ALLWINNER_H3_DRAMPHY_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_H3_DRAMPHY_WRITE) || \ false) static inline void _nocheck__trace_allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_H3_DRAMPHY_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 16 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_h3_dramphy_write " "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1112 "trace/trace-hw_misc.h" } else { #line 16 "../hw/misc/trace-events" qemu_log("allwinner_h3_dramphy_write " "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1116 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_h3_dramphy_write(offset, data, size); } } #define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE) || \ false) static inline void _nocheck__trace_allwinner_r40_dramc_detect_cells_disable(void) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_DISABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 19 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramc_detect_cells_disable " "Disable detect cells" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 1143 "trace/trace-hw_misc.h" } else { #line 19 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramc_detect_cells_disable " "Disable detect cells" "\n"); #line 1147 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramc_detect_cells_disable(void) { if (true) { _nocheck__trace_allwinner_r40_dramc_detect_cells_disable(); } } #define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE) || \ false) static inline void _nocheck__trace_allwinner_r40_dramc_detect_cells_enable(void) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELLS_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 20 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramc_detect_cells_enable " "Enable detect cells" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 1174 "trace/trace-hw_misc.h" } else { #line 20 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramc_detect_cells_enable " "Enable detect cells" "\n"); #line 1178 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramc_detect_cells_enable(void) { if (true) { _nocheck__trace_allwinner_r40_dramc_detect_cells_enable(); } } #define TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS) || \ false) static inline void _nocheck__trace_allwinner_r40_dramc_map_rows(uint8_t row_bits, uint8_t bank_bits, uint8_t col_bits) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_MAP_ROWS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 21 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramc_map_rows " "DRAM layout: row_bits %d, bank_bits %d, col_bits %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , row_bits, bank_bits, col_bits); #line 1205 "trace/trace-hw_misc.h" } else { #line 21 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramc_map_rows " "DRAM layout: row_bits %d, bank_bits %d, col_bits %d" "\n", row_bits, bank_bits, col_bits); #line 1209 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramc_map_rows(uint8_t row_bits, uint8_t bank_bits, uint8_t col_bits) { if (true) { _nocheck__trace_allwinner_r40_dramc_map_rows(row_bits, bank_bits, col_bits); } } #define TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL) || \ false) static inline void _nocheck__trace_allwinner_r40_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_OFFSET_TO_CELL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 22 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramc_offset_to_cell " "offset 0x%" PRIx64 " row %d bank %d col %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, row, bank, col); #line 1236 "trace/trace-hw_misc.h" } else { #line 22 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramc_offset_to_cell " "offset 0x%" PRIx64 " row %d bank %d col %d" "\n", offset, row, bank, col); #line 1240 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col) { if (true) { _nocheck__trace_allwinner_r40_dramc_offset_to_cell(offset, row, bank, col); } } #define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE) || \ false) static inline void _nocheck__trace_allwinner_r40_dramc_detect_cell_write(uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 23 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramc_detect_cell_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data); #line 1267 "trace/trace-hw_misc.h" } else { #line 23 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramc_detect_cell_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 "" "\n", offset, data); #line 1271 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramc_detect_cell_write(uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_allwinner_r40_dramc_detect_cell_write(offset, data); } } #define TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ) || \ false) static inline void _nocheck__trace_allwinner_r40_dramc_detect_cell_read(uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMC_DETECT_CELL_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 24 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramc_detect_cell_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data); #line 1298 "trace/trace-hw_misc.h" } else { #line 24 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramc_detect_cell_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 "" "\n", offset, data); #line 1302 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramc_detect_cell_read(uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_allwinner_r40_dramc_detect_cell_read(offset, data); } } #define TRACE_ALLWINNER_R40_DRAMCOM_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMCOM_READ) || \ false) static inline void _nocheck__trace_allwinner_r40_dramcom_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMCOM_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 25 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramcom_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1329 "trace/trace-hw_misc.h" } else { #line 25 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramcom_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1333 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramcom_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_r40_dramcom_read(offset, data, size); } } #define TRACE_ALLWINNER_R40_DRAMCOM_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMCOM_WRITE) || \ false) static inline void _nocheck__trace_allwinner_r40_dramcom_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMCOM_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 26 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramcom_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1360 "trace/trace-hw_misc.h" } else { #line 26 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramcom_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1364 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramcom_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_r40_dramcom_write(offset, data, size); } } #define TRACE_ALLWINNER_R40_DRAMCTL_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMCTL_READ) || \ false) static inline void _nocheck__trace_allwinner_r40_dramctl_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMCTL_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 27 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramctl_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1391 "trace/trace-hw_misc.h" } else { #line 27 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramctl_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1395 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramctl_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_r40_dramctl_read(offset, data, size); } } #define TRACE_ALLWINNER_R40_DRAMCTL_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMCTL_WRITE) || \ false) static inline void _nocheck__trace_allwinner_r40_dramctl_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMCTL_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 28 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramctl_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1422 "trace/trace-hw_misc.h" } else { #line 28 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramctl_write " "Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1426 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramctl_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_r40_dramctl_write(offset, data, size); } } #define TRACE_ALLWINNER_R40_DRAMPHY_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMPHY_READ) || \ false) static inline void _nocheck__trace_allwinner_r40_dramphy_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMPHY_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 29 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramphy_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1453 "trace/trace-hw_misc.h" } else { #line 29 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramphy_read " "Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1457 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramphy_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_r40_dramphy_read(offset, data, size); } } #define TRACE_ALLWINNER_R40_DRAMPHY_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_R40_DRAMPHY_WRITE) || \ false) static inline void _nocheck__trace_allwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_R40_DRAMPHY_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 30 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_r40_dramphy_write " "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1484 "trace/trace-hw_misc.h" } else { #line 30 "../hw/misc/trace-events" qemu_log("allwinner_r40_dramphy_write " "write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1488 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_r40_dramphy_write(offset, data, size); } } #define TRACE_ALLWINNER_SID_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SID_READ) || \ false) static inline void _nocheck__trace_allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_SID_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 33 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_sid_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1515 "trace/trace-hw_misc.h" } else { #line 33 "../hw/misc/trace-events" qemu_log("allwinner_sid_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1519 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_sid_read(offset, data, size); } } #define TRACE_ALLWINNER_SID_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SID_WRITE) || \ false) static inline void _nocheck__trace_allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ALLWINNER_SID_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 34 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_sid_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 1546 "trace/trace-hw_misc.h" } else { #line 34 "../hw/misc/trace-events" qemu_log("allwinner_sid_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 "\n", offset, data, size); #line 1550 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_allwinner_sid_write(offset, data, size); } } #define TRACE_ALLWINNER_SRAMC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SRAMC_READ) || \ false) static inline void _nocheck__trace_allwinner_sramc_read(uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_ALLWINNER_SRAMC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 37 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_sramc_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data); #line 1577 "trace/trace-hw_misc.h" } else { #line 37 "../hw/misc/trace-events" qemu_log("allwinner_sramc_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data); #line 1581 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_sramc_read(uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_allwinner_sramc_read(offset, data); } } #define TRACE_ALLWINNER_SRAMC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ALLWINNER_SRAMC_WRITE) || \ false) static inline void _nocheck__trace_allwinner_sramc_write(uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_ALLWINNER_SRAMC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 38 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:allwinner_sramc_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data); #line 1608 "trace/trace-hw_misc.h" } else { #line 38 "../hw/misc/trace-events" qemu_log("allwinner_sramc_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data); #line 1612 "trace/trace-hw_misc.h" } } } static inline void trace_allwinner_sramc_write(uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_allwinner_sramc_write(offset, data); } } #define TRACE_AVR_POWER_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_AVR_POWER_READ) || \ false) static inline void _nocheck__trace_avr_power_read(uint8_t value) { if (trace_event_get_state(TRACE_AVR_POWER_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 41 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:avr_power_read " "power_reduc read value:%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , value); #line 1639 "trace/trace-hw_misc.h" } else { #line 41 "../hw/misc/trace-events" qemu_log("avr_power_read " "power_reduc read value:%u" "\n", value); #line 1643 "trace/trace-hw_misc.h" } } } static inline void trace_avr_power_read(uint8_t value) { if (true) { _nocheck__trace_avr_power_read(value); } } #define TRACE_AVR_POWER_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_AVR_POWER_WRITE) || \ false) static inline void _nocheck__trace_avr_power_write(uint8_t value) { if (trace_event_get_state(TRACE_AVR_POWER_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 42 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:avr_power_write " "power_reduc write value:%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , value); #line 1670 "trace/trace-hw_misc.h" } else { #line 42 "../hw/misc/trace-events" qemu_log("avr_power_write " "power_reduc write value:%u" "\n", value); #line 1674 "trace/trace-hw_misc.h" } } } static inline void trace_avr_power_write(uint8_t value) { if (true) { _nocheck__trace_avr_power_write(value); } } #define TRACE_AXP2XX_RX_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_AXP2XX_RX) || \ false) static inline void _nocheck__trace_axp2xx_rx(uint8_t reg, uint8_t data) { if (trace_event_get_state(TRACE_AXP2XX_RX) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 45 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:axp2xx_rx " "Read reg 0x%" PRIx8 " : 0x%" PRIx8 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, data); #line 1701 "trace/trace-hw_misc.h" } else { #line 45 "../hw/misc/trace-events" qemu_log("axp2xx_rx " "Read reg 0x%" PRIx8 " : 0x%" PRIx8 "\n", reg, data); #line 1705 "trace/trace-hw_misc.h" } } } static inline void trace_axp2xx_rx(uint8_t reg, uint8_t data) { if (true) { _nocheck__trace_axp2xx_rx(reg, data); } } #define TRACE_AXP2XX_SELECT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_AXP2XX_SELECT) || \ false) static inline void _nocheck__trace_axp2xx_select(uint8_t reg) { if (trace_event_get_state(TRACE_AXP2XX_SELECT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 46 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:axp2xx_select " "Accessing reg 0x%" PRIx8 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg); #line 1732 "trace/trace-hw_misc.h" } else { #line 46 "../hw/misc/trace-events" qemu_log("axp2xx_select " "Accessing reg 0x%" PRIx8 "\n", reg); #line 1736 "trace/trace-hw_misc.h" } } } static inline void trace_axp2xx_select(uint8_t reg) { if (true) { _nocheck__trace_axp2xx_select(reg); } } #define TRACE_AXP2XX_TX_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_AXP2XX_TX) || \ false) static inline void _nocheck__trace_axp2xx_tx(uint8_t reg, uint8_t data) { if (trace_event_get_state(TRACE_AXP2XX_TX) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 47 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:axp2xx_tx " "Write reg 0x%" PRIx8 " : 0x%" PRIx8 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, data); #line 1763 "trace/trace-hw_misc.h" } else { #line 47 "../hw/misc/trace-events" qemu_log("axp2xx_tx " "Write reg 0x%" PRIx8 " : 0x%" PRIx8 "\n", reg, data); #line 1767 "trace/trace-hw_misc.h" } } } static inline void trace_axp2xx_tx(uint8_t reg, uint8_t data) { if (true) { _nocheck__trace_axp2xx_tx(reg, data); } } #define TRACE_ECC_MEM_WRITEL_MER_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_MER) || \ false) static inline void _nocheck__trace_ecc_mem_writel_mer(uint32_t val) { if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_MER) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 50 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_writel_mer " "Write memory enable 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 1794 "trace/trace-hw_misc.h" } else { #line 50 "../hw/misc/trace-events" qemu_log("ecc_mem_writel_mer " "Write memory enable 0x%08x" "\n", val); #line 1798 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_writel_mer(uint32_t val) { if (true) { _nocheck__trace_ecc_mem_writel_mer(val); } } #define TRACE_ECC_MEM_WRITEL_MDR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_MDR) || \ false) static inline void _nocheck__trace_ecc_mem_writel_mdr(uint32_t val) { if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_MDR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 51 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_writel_mdr " "Write memory delay 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 1825 "trace/trace-hw_misc.h" } else { #line 51 "../hw/misc/trace-events" qemu_log("ecc_mem_writel_mdr " "Write memory delay 0x%08x" "\n", val); #line 1829 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_writel_mdr(uint32_t val) { if (true) { _nocheck__trace_ecc_mem_writel_mdr(val); } } #define TRACE_ECC_MEM_WRITEL_MFSR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_MFSR) || \ false) static inline void _nocheck__trace_ecc_mem_writel_mfsr(uint32_t val) { if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_MFSR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 52 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_writel_mfsr " "Write memory fault status 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 1856 "trace/trace-hw_misc.h" } else { #line 52 "../hw/misc/trace-events" qemu_log("ecc_mem_writel_mfsr " "Write memory fault status 0x%08x" "\n", val); #line 1860 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_writel_mfsr(uint32_t val) { if (true) { _nocheck__trace_ecc_mem_writel_mfsr(val); } } #define TRACE_ECC_MEM_WRITEL_VCR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_VCR) || \ false) static inline void _nocheck__trace_ecc_mem_writel_vcr(uint32_t val) { if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_VCR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 53 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_writel_vcr " "Write slot configuration 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 1887 "trace/trace-hw_misc.h" } else { #line 53 "../hw/misc/trace-events" qemu_log("ecc_mem_writel_vcr " "Write slot configuration 0x%08x" "\n", val); #line 1891 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_writel_vcr(uint32_t val) { if (true) { _nocheck__trace_ecc_mem_writel_vcr(val); } } #define TRACE_ECC_MEM_WRITEL_DR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_DR) || \ false) static inline void _nocheck__trace_ecc_mem_writel_dr(uint32_t val) { if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_DR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 54 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_writel_dr " "Write diagnostic 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 1918 "trace/trace-hw_misc.h" } else { #line 54 "../hw/misc/trace-events" qemu_log("ecc_mem_writel_dr " "Write diagnostic 0x%08x" "\n", val); #line 1922 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_writel_dr(uint32_t val) { if (true) { _nocheck__trace_ecc_mem_writel_dr(val); } } #define TRACE_ECC_MEM_WRITEL_ECR0_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_ECR0) || \ false) static inline void _nocheck__trace_ecc_mem_writel_ecr0(uint32_t val) { if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_ECR0) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 55 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_writel_ecr0 " "Write event count 1 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 1949 "trace/trace-hw_misc.h" } else { #line 55 "../hw/misc/trace-events" qemu_log("ecc_mem_writel_ecr0 " "Write event count 1 0x%08x" "\n", val); #line 1953 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_writel_ecr0(uint32_t val) { if (true) { _nocheck__trace_ecc_mem_writel_ecr0(val); } } #define TRACE_ECC_MEM_WRITEL_ECR1_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_WRITEL_ECR1) || \ false) static inline void _nocheck__trace_ecc_mem_writel_ecr1(uint32_t val) { if (trace_event_get_state(TRACE_ECC_MEM_WRITEL_ECR1) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 56 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_writel_ecr1 " "Write event count 2 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 1980 "trace/trace-hw_misc.h" } else { #line 56 "../hw/misc/trace-events" qemu_log("ecc_mem_writel_ecr1 " "Write event count 2 0x%08x" "\n", val); #line 1984 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_writel_ecr1(uint32_t val) { if (true) { _nocheck__trace_ecc_mem_writel_ecr1(val); } } #define TRACE_ECC_MEM_READL_MER_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_MER) || \ false) static inline void _nocheck__trace_ecc_mem_readl_mer(uint32_t ret) { if (trace_event_get_state(TRACE_ECC_MEM_READL_MER) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 57 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_readl_mer " "Read memory enable 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2011 "trace/trace-hw_misc.h" } else { #line 57 "../hw/misc/trace-events" qemu_log("ecc_mem_readl_mer " "Read memory enable 0x%08x" "\n", ret); #line 2015 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_readl_mer(uint32_t ret) { if (true) { _nocheck__trace_ecc_mem_readl_mer(ret); } } #define TRACE_ECC_MEM_READL_MDR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_MDR) || \ false) static inline void _nocheck__trace_ecc_mem_readl_mdr(uint32_t ret) { if (trace_event_get_state(TRACE_ECC_MEM_READL_MDR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 58 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_readl_mdr " "Read memory delay 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2042 "trace/trace-hw_misc.h" } else { #line 58 "../hw/misc/trace-events" qemu_log("ecc_mem_readl_mdr " "Read memory delay 0x%08x" "\n", ret); #line 2046 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_readl_mdr(uint32_t ret) { if (true) { _nocheck__trace_ecc_mem_readl_mdr(ret); } } #define TRACE_ECC_MEM_READL_MFSR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_MFSR) || \ false) static inline void _nocheck__trace_ecc_mem_readl_mfsr(uint32_t ret) { if (trace_event_get_state(TRACE_ECC_MEM_READL_MFSR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 59 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_readl_mfsr " "Read memory fault status 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2073 "trace/trace-hw_misc.h" } else { #line 59 "../hw/misc/trace-events" qemu_log("ecc_mem_readl_mfsr " "Read memory fault status 0x%08x" "\n", ret); #line 2077 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_readl_mfsr(uint32_t ret) { if (true) { _nocheck__trace_ecc_mem_readl_mfsr(ret); } } #define TRACE_ECC_MEM_READL_VCR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_VCR) || \ false) static inline void _nocheck__trace_ecc_mem_readl_vcr(uint32_t ret) { if (trace_event_get_state(TRACE_ECC_MEM_READL_VCR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 60 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_readl_vcr " "Read slot configuration 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2104 "trace/trace-hw_misc.h" } else { #line 60 "../hw/misc/trace-events" qemu_log("ecc_mem_readl_vcr " "Read slot configuration 0x%08x" "\n", ret); #line 2108 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_readl_vcr(uint32_t ret) { if (true) { _nocheck__trace_ecc_mem_readl_vcr(ret); } } #define TRACE_ECC_MEM_READL_MFAR0_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_MFAR0) || \ false) static inline void _nocheck__trace_ecc_mem_readl_mfar0(uint32_t ret) { if (trace_event_get_state(TRACE_ECC_MEM_READL_MFAR0) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 61 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_readl_mfar0 " "Read memory fault address 0 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2135 "trace/trace-hw_misc.h" } else { #line 61 "../hw/misc/trace-events" qemu_log("ecc_mem_readl_mfar0 " "Read memory fault address 0 0x%08x" "\n", ret); #line 2139 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_readl_mfar0(uint32_t ret) { if (true) { _nocheck__trace_ecc_mem_readl_mfar0(ret); } } #define TRACE_ECC_MEM_READL_MFAR1_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_MFAR1) || \ false) static inline void _nocheck__trace_ecc_mem_readl_mfar1(uint32_t ret) { if (trace_event_get_state(TRACE_ECC_MEM_READL_MFAR1) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 62 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_readl_mfar1 " "Read memory fault address 1 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2166 "trace/trace-hw_misc.h" } else { #line 62 "../hw/misc/trace-events" qemu_log("ecc_mem_readl_mfar1 " "Read memory fault address 1 0x%08x" "\n", ret); #line 2170 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_readl_mfar1(uint32_t ret) { if (true) { _nocheck__trace_ecc_mem_readl_mfar1(ret); } } #define TRACE_ECC_MEM_READL_DR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_DR) || \ false) static inline void _nocheck__trace_ecc_mem_readl_dr(uint32_t ret) { if (trace_event_get_state(TRACE_ECC_MEM_READL_DR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 63 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_readl_dr " "Read diagnostic 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2197 "trace/trace-hw_misc.h" } else { #line 63 "../hw/misc/trace-events" qemu_log("ecc_mem_readl_dr " "Read diagnostic 0x%08x" "\n", ret); #line 2201 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_readl_dr(uint32_t ret) { if (true) { _nocheck__trace_ecc_mem_readl_dr(ret); } } #define TRACE_ECC_MEM_READL_ECR0_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_ECR0) || \ false) static inline void _nocheck__trace_ecc_mem_readl_ecr0(uint32_t ret) { if (trace_event_get_state(TRACE_ECC_MEM_READL_ECR0) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 64 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_readl_ecr0 " "Read event count 1 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2228 "trace/trace-hw_misc.h" } else { #line 64 "../hw/misc/trace-events" qemu_log("ecc_mem_readl_ecr0 " "Read event count 1 0x%08x" "\n", ret); #line 2232 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_readl_ecr0(uint32_t ret) { if (true) { _nocheck__trace_ecc_mem_readl_ecr0(ret); } } #define TRACE_ECC_MEM_READL_ECR1_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_MEM_READL_ECR1) || \ false) static inline void _nocheck__trace_ecc_mem_readl_ecr1(uint32_t ret) { if (trace_event_get_state(TRACE_ECC_MEM_READL_ECR1) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 65 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_mem_readl_ecr1 " "Read event count 2 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2259 "trace/trace-hw_misc.h" } else { #line 65 "../hw/misc/trace-events" qemu_log("ecc_mem_readl_ecr1 " "Read event count 2 0x%08x" "\n", ret); #line 2263 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_mem_readl_ecr1(uint32_t ret) { if (true) { _nocheck__trace_ecc_mem_readl_ecr1(ret); } } #define TRACE_ECC_DIAG_MEM_WRITEB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_DIAG_MEM_WRITEB) || \ false) static inline void _nocheck__trace_ecc_diag_mem_writeb(uint64_t addr, uint32_t val) { if (trace_event_get_state(TRACE_ECC_DIAG_MEM_WRITEB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 66 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_diag_mem_writeb " "Write diagnostic %"PRId64" = 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 2290 "trace/trace-hw_misc.h" } else { #line 66 "../hw/misc/trace-events" qemu_log("ecc_diag_mem_writeb " "Write diagnostic %"PRId64" = 0x%02x" "\n", addr, val); #line 2294 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_diag_mem_writeb(uint64_t addr, uint32_t val) { if (true) { _nocheck__trace_ecc_diag_mem_writeb(addr, val); } } #define TRACE_ECC_DIAG_MEM_READB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ECC_DIAG_MEM_READB) || \ false) static inline void _nocheck__trace_ecc_diag_mem_readb(uint64_t addr, uint32_t ret) { if (trace_event_get_state(TRACE_ECC_DIAG_MEM_READB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 67 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ecc_diag_mem_readb " "Read diagnostic %"PRId64"= 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, ret); #line 2321 "trace/trace-hw_misc.h" } else { #line 67 "../hw/misc/trace-events" qemu_log("ecc_diag_mem_readb " "Read diagnostic %"PRId64"= 0x%02x" "\n", addr, ret); #line 2325 "trace/trace-hw_misc.h" } } } static inline void trace_ecc_diag_mem_readb(uint64_t addr, uint32_t ret) { if (true) { _nocheck__trace_ecc_diag_mem_readb(addr, ret); } } #define TRACE_EMPTY_SLOT_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_EMPTY_SLOT_WRITE) || \ false) static inline void _nocheck__trace_empty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char * name) { if (trace_event_get_state(TRACE_EMPTY_SLOT_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 70 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:empty_slot_write " "wr addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, width, value, size, name); #line 2352 "trace/trace-hw_misc.h" } else { #line 70 "../hw/misc/trace-events" qemu_log("empty_slot_write " "wr addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]" "\n", addr, width, value, size, name); #line 2356 "trace/trace-hw_misc.h" } } } static inline void trace_empty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char * name) { if (true) { _nocheck__trace_empty_slot_write(addr, width, value, size, name); } } #define TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE) || \ false) static inline void _nocheck__trace_slavio_misc_update_irq_raise(void) { if (trace_event_get_state(TRACE_SLAVIO_MISC_UPDATE_IRQ_RAISE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 73 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_misc_update_irq_raise " "Raise IRQ" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 2383 "trace/trace-hw_misc.h" } else { #line 73 "../hw/misc/trace-events" qemu_log("slavio_misc_update_irq_raise " "Raise IRQ" "\n"); #line 2387 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_misc_update_irq_raise(void) { if (true) { _nocheck__trace_slavio_misc_update_irq_raise(); } } #define TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER) || \ false) static inline void _nocheck__trace_slavio_misc_update_irq_lower(void) { if (trace_event_get_state(TRACE_SLAVIO_MISC_UPDATE_IRQ_LOWER) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 74 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_misc_update_irq_lower " "Lower IRQ" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 2414 "trace/trace-hw_misc.h" } else { #line 74 "../hw/misc/trace-events" qemu_log("slavio_misc_update_irq_lower " "Lower IRQ" "\n"); #line 2418 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_misc_update_irq_lower(void) { if (true) { _nocheck__trace_slavio_misc_update_irq_lower(); } } #define TRACE_SLAVIO_SET_POWER_FAIL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_SET_POWER_FAIL) || \ false) static inline void _nocheck__trace_slavio_set_power_fail(int power_failing, uint8_t config) { if (trace_event_get_state(TRACE_SLAVIO_SET_POWER_FAIL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 75 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_set_power_fail " "Power fail: %d, config: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , power_failing, config); #line 2445 "trace/trace-hw_misc.h" } else { #line 75 "../hw/misc/trace-events" qemu_log("slavio_set_power_fail " "Power fail: %d, config: %d" "\n", power_failing, config); #line 2449 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_set_power_fail(int power_failing, uint8_t config) { if (true) { _nocheck__trace_slavio_set_power_fail(power_failing, config); } } #define TRACE_SLAVIO_CFG_MEM_WRITEB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_CFG_MEM_WRITEB) || \ false) static inline void _nocheck__trace_slavio_cfg_mem_writeb(uint32_t val) { if (trace_event_get_state(TRACE_SLAVIO_CFG_MEM_WRITEB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 76 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_cfg_mem_writeb " "Write config 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 2476 "trace/trace-hw_misc.h" } else { #line 76 "../hw/misc/trace-events" qemu_log("slavio_cfg_mem_writeb " "Write config 0x%02x" "\n", val); #line 2480 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_cfg_mem_writeb(uint32_t val) { if (true) { _nocheck__trace_slavio_cfg_mem_writeb(val); } } #define TRACE_SLAVIO_CFG_MEM_READB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_CFG_MEM_READB) || \ false) static inline void _nocheck__trace_slavio_cfg_mem_readb(uint32_t ret) { if (trace_event_get_state(TRACE_SLAVIO_CFG_MEM_READB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 77 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_cfg_mem_readb " "Read config 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2507 "trace/trace-hw_misc.h" } else { #line 77 "../hw/misc/trace-events" qemu_log("slavio_cfg_mem_readb " "Read config 0x%02x" "\n", ret); #line 2511 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_cfg_mem_readb(uint32_t ret) { if (true) { _nocheck__trace_slavio_cfg_mem_readb(ret); } } #define TRACE_SLAVIO_DIAG_MEM_WRITEB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_DIAG_MEM_WRITEB) || \ false) static inline void _nocheck__trace_slavio_diag_mem_writeb(uint32_t val) { if (trace_event_get_state(TRACE_SLAVIO_DIAG_MEM_WRITEB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 78 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_diag_mem_writeb " "Write diag 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 2538 "trace/trace-hw_misc.h" } else { #line 78 "../hw/misc/trace-events" qemu_log("slavio_diag_mem_writeb " "Write diag 0x%02x" "\n", val); #line 2542 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_diag_mem_writeb(uint32_t val) { if (true) { _nocheck__trace_slavio_diag_mem_writeb(val); } } #define TRACE_SLAVIO_DIAG_MEM_READB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_DIAG_MEM_READB) || \ false) static inline void _nocheck__trace_slavio_diag_mem_readb(uint32_t ret) { if (trace_event_get_state(TRACE_SLAVIO_DIAG_MEM_READB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 79 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_diag_mem_readb " "Read diag 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2569 "trace/trace-hw_misc.h" } else { #line 79 "../hw/misc/trace-events" qemu_log("slavio_diag_mem_readb " "Read diag 0x%02x" "\n", ret); #line 2573 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_diag_mem_readb(uint32_t ret) { if (true) { _nocheck__trace_slavio_diag_mem_readb(ret); } } #define TRACE_SLAVIO_MDM_MEM_WRITEB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_MDM_MEM_WRITEB) || \ false) static inline void _nocheck__trace_slavio_mdm_mem_writeb(uint32_t val) { if (trace_event_get_state(TRACE_SLAVIO_MDM_MEM_WRITEB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 80 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_mdm_mem_writeb " "Write modem control 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 2600 "trace/trace-hw_misc.h" } else { #line 80 "../hw/misc/trace-events" qemu_log("slavio_mdm_mem_writeb " "Write modem control 0x%02x" "\n", val); #line 2604 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_mdm_mem_writeb(uint32_t val) { if (true) { _nocheck__trace_slavio_mdm_mem_writeb(val); } } #define TRACE_SLAVIO_MDM_MEM_READB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_MDM_MEM_READB) || \ false) static inline void _nocheck__trace_slavio_mdm_mem_readb(uint32_t ret) { if (trace_event_get_state(TRACE_SLAVIO_MDM_MEM_READB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 81 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_mdm_mem_readb " "Read modem control 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2631 "trace/trace-hw_misc.h" } else { #line 81 "../hw/misc/trace-events" qemu_log("slavio_mdm_mem_readb " "Read modem control 0x%02x" "\n", ret); #line 2635 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_mdm_mem_readb(uint32_t ret) { if (true) { _nocheck__trace_slavio_mdm_mem_readb(ret); } } #define TRACE_SLAVIO_AUX1_MEM_WRITEB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_AUX1_MEM_WRITEB) || \ false) static inline void _nocheck__trace_slavio_aux1_mem_writeb(uint32_t val) { if (trace_event_get_state(TRACE_SLAVIO_AUX1_MEM_WRITEB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 82 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_aux1_mem_writeb " "Write aux1 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 2662 "trace/trace-hw_misc.h" } else { #line 82 "../hw/misc/trace-events" qemu_log("slavio_aux1_mem_writeb " "Write aux1 0x%02x" "\n", val); #line 2666 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_aux1_mem_writeb(uint32_t val) { if (true) { _nocheck__trace_slavio_aux1_mem_writeb(val); } } #define TRACE_SLAVIO_AUX1_MEM_READB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_AUX1_MEM_READB) || \ false) static inline void _nocheck__trace_slavio_aux1_mem_readb(uint32_t ret) { if (trace_event_get_state(TRACE_SLAVIO_AUX1_MEM_READB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 83 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_aux1_mem_readb " "Read aux1 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2693 "trace/trace-hw_misc.h" } else { #line 83 "../hw/misc/trace-events" qemu_log("slavio_aux1_mem_readb " "Read aux1 0x%02x" "\n", ret); #line 2697 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_aux1_mem_readb(uint32_t ret) { if (true) { _nocheck__trace_slavio_aux1_mem_readb(ret); } } #define TRACE_SLAVIO_AUX2_MEM_WRITEB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_AUX2_MEM_WRITEB) || \ false) static inline void _nocheck__trace_slavio_aux2_mem_writeb(uint32_t val) { if (trace_event_get_state(TRACE_SLAVIO_AUX2_MEM_WRITEB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 84 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_aux2_mem_writeb " "Write aux2 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 2724 "trace/trace-hw_misc.h" } else { #line 84 "../hw/misc/trace-events" qemu_log("slavio_aux2_mem_writeb " "Write aux2 0x%02x" "\n", val); #line 2728 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_aux2_mem_writeb(uint32_t val) { if (true) { _nocheck__trace_slavio_aux2_mem_writeb(val); } } #define TRACE_SLAVIO_AUX2_MEM_READB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_AUX2_MEM_READB) || \ false) static inline void _nocheck__trace_slavio_aux2_mem_readb(uint32_t ret) { if (trace_event_get_state(TRACE_SLAVIO_AUX2_MEM_READB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 85 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_aux2_mem_readb " "Read aux2 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2755 "trace/trace-hw_misc.h" } else { #line 85 "../hw/misc/trace-events" qemu_log("slavio_aux2_mem_readb " "Read aux2 0x%02x" "\n", ret); #line 2759 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_aux2_mem_readb(uint32_t ret) { if (true) { _nocheck__trace_slavio_aux2_mem_readb(ret); } } #define TRACE_APC_MEM_WRITEB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_APC_MEM_WRITEB) || \ false) static inline void _nocheck__trace_apc_mem_writeb(uint32_t val) { if (trace_event_get_state(TRACE_APC_MEM_WRITEB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 86 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:apc_mem_writeb " "Write power management 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 2786 "trace/trace-hw_misc.h" } else { #line 86 "../hw/misc/trace-events" qemu_log("apc_mem_writeb " "Write power management 0x%02x" "\n", val); #line 2790 "trace/trace-hw_misc.h" } } } static inline void trace_apc_mem_writeb(uint32_t val) { if (true) { _nocheck__trace_apc_mem_writeb(val); } } #define TRACE_APC_MEM_READB_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_APC_MEM_READB) || \ false) static inline void _nocheck__trace_apc_mem_readb(uint32_t ret) { if (trace_event_get_state(TRACE_APC_MEM_READB) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 87 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:apc_mem_readb " "Read power management 0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2817 "trace/trace-hw_misc.h" } else { #line 87 "../hw/misc/trace-events" qemu_log("apc_mem_readb " "Read power management 0x%02x" "\n", ret); #line 2821 "trace/trace-hw_misc.h" } } } static inline void trace_apc_mem_readb(uint32_t ret) { if (true) { _nocheck__trace_apc_mem_readb(ret); } } #define TRACE_SLAVIO_SYSCTRL_MEM_WRITEL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_SYSCTRL_MEM_WRITEL) || \ false) static inline void _nocheck__trace_slavio_sysctrl_mem_writel(uint32_t val) { if (trace_event_get_state(TRACE_SLAVIO_SYSCTRL_MEM_WRITEL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 88 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_sysctrl_mem_writel " "Write system control 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 2848 "trace/trace-hw_misc.h" } else { #line 88 "../hw/misc/trace-events" qemu_log("slavio_sysctrl_mem_writel " "Write system control 0x%08x" "\n", val); #line 2852 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_sysctrl_mem_writel(uint32_t val) { if (true) { _nocheck__trace_slavio_sysctrl_mem_writel(val); } } #define TRACE_SLAVIO_SYSCTRL_MEM_READL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_SYSCTRL_MEM_READL) || \ false) static inline void _nocheck__trace_slavio_sysctrl_mem_readl(uint32_t ret) { if (trace_event_get_state(TRACE_SLAVIO_SYSCTRL_MEM_READL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 89 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_sysctrl_mem_readl " "Read system control 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2879 "trace/trace-hw_misc.h" } else { #line 89 "../hw/misc/trace-events" qemu_log("slavio_sysctrl_mem_readl " "Read system control 0x%08x" "\n", ret); #line 2883 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_sysctrl_mem_readl(uint32_t ret) { if (true) { _nocheck__trace_slavio_sysctrl_mem_readl(ret); } } #define TRACE_SLAVIO_LED_MEM_WRITEW_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_LED_MEM_WRITEW) || \ false) static inline void _nocheck__trace_slavio_led_mem_writew(uint32_t val) { if (trace_event_get_state(TRACE_SLAVIO_LED_MEM_WRITEW) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 90 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_led_mem_writew " "Write diagnostic LED 0x%04x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , val); #line 2910 "trace/trace-hw_misc.h" } else { #line 90 "../hw/misc/trace-events" qemu_log("slavio_led_mem_writew " "Write diagnostic LED 0x%04x" "\n", val); #line 2914 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_led_mem_writew(uint32_t val) { if (true) { _nocheck__trace_slavio_led_mem_writew(val); } } #define TRACE_SLAVIO_LED_MEM_READW_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_SLAVIO_LED_MEM_READW) || \ false) static inline void _nocheck__trace_slavio_led_mem_readw(uint32_t ret) { if (trace_event_get_state(TRACE_SLAVIO_LED_MEM_READW) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 91 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:slavio_led_mem_readw " "Read diagnostic LED 0x%04x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ret); #line 2941 "trace/trace-hw_misc.h" } else { #line 91 "../hw/misc/trace-events" qemu_log("slavio_led_mem_readw " "Read diagnostic LED 0x%04x" "\n", ret); #line 2945 "trace/trace-hw_misc.h" } } } static inline void trace_slavio_led_mem_readw(uint32_t ret) { if (true) { _nocheck__trace_slavio_led_mem_readw(ret); } } #define TRACE_ASPEED_SCU_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SCU_WRITE) || \ false) static inline void _nocheck__trace_aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_SCU_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 94 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_scu_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 2972 "trace/trace-hw_misc.h" } else { #line 94 "../hw/misc/trace-events" qemu_log("aspeed_scu_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 2976 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) { if (true) { _nocheck__trace_aspeed_scu_write(offset, size, data); } } #define TRACE_ASPEED_SCU_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SCU_READ) || \ false) static inline void _nocheck__trace_aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_SCU_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 95 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_scu_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 3003 "trace/trace-hw_misc.h" } else { #line 95 "../hw/misc/trace-events" qemu_log("aspeed_scu_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 3007 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) { if (true) { _nocheck__trace_aspeed_scu_read(offset, size, data); } } #define TRACE_ASPEED_AST2700_SCU_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_AST2700_SCU_WRITE) || \ false) static inline void _nocheck__trace_aspeed_ast2700_scu_write(uint64_t offset, unsigned size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_AST2700_SCU_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 96 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_ast2700_scu_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 3034 "trace/trace-hw_misc.h" } else { #line 96 "../hw/misc/trace-events" qemu_log("aspeed_ast2700_scu_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 3038 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_ast2700_scu_write(uint64_t offset, unsigned size, uint32_t data) { if (true) { _nocheck__trace_aspeed_ast2700_scu_write(offset, size, data); } } #define TRACE_ASPEED_AST2700_SCU_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_AST2700_SCU_READ) || \ false) static inline void _nocheck__trace_aspeed_ast2700_scu_read(uint64_t offset, unsigned size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_AST2700_SCU_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 97 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_ast2700_scu_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 3065 "trace/trace-hw_misc.h" } else { #line 97 "../hw/misc/trace-events" qemu_log("aspeed_ast2700_scu_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 3069 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_ast2700_scu_read(uint64_t offset, unsigned size, uint32_t data) { if (true) { _nocheck__trace_aspeed_ast2700_scu_read(offset, size, data); } } #define TRACE_ASPEED_AST2700_SCUIO_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_AST2700_SCUIO_WRITE) || \ false) static inline void _nocheck__trace_aspeed_ast2700_scuio_write(uint64_t offset, unsigned size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_AST2700_SCUIO_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 98 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_ast2700_scuio_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 3096 "trace/trace-hw_misc.h" } else { #line 98 "../hw/misc/trace-events" qemu_log("aspeed_ast2700_scuio_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 3100 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_ast2700_scuio_write(uint64_t offset, unsigned size, uint32_t data) { if (true) { _nocheck__trace_aspeed_ast2700_scuio_write(offset, size, data); } } #define TRACE_ASPEED_AST2700_SCUIO_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_AST2700_SCUIO_READ) || \ false) static inline void _nocheck__trace_aspeed_ast2700_scuio_read(uint64_t offset, unsigned size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_AST2700_SCUIO_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 99 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_ast2700_scuio_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 3127 "trace/trace-hw_misc.h" } else { #line 99 "../hw/misc/trace-events" qemu_log("aspeed_ast2700_scuio_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 3131 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_ast2700_scuio_read(uint64_t offset, unsigned size, uint32_t data) { if (true) { _nocheck__trace_aspeed_ast2700_scuio_read(offset, size, data); } } #define TRACE_MPS2_SCC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MPS2_SCC_READ) || \ false) static inline void _nocheck__trace_mps2_scc_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_MPS2_SCC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 102 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mps2_scc_read " "MPS2 SCC read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 3158 "trace/trace-hw_misc.h" } else { #line 102 "../hw/misc/trace-events" qemu_log("mps2_scc_read " "MPS2 SCC read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 3162 "trace/trace-hw_misc.h" } } } static inline void trace_mps2_scc_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_mps2_scc_read(offset, data, size); } } #define TRACE_MPS2_SCC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MPS2_SCC_WRITE) || \ false) static inline void _nocheck__trace_mps2_scc_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_MPS2_SCC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 103 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mps2_scc_write " "MPS2 SCC write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 3189 "trace/trace-hw_misc.h" } else { #line 103 "../hw/misc/trace-events" qemu_log("mps2_scc_write " "MPS2 SCC write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 3193 "trace/trace-hw_misc.h" } } } static inline void trace_mps2_scc_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_mps2_scc_write(offset, data, size); } } #define TRACE_MPS2_SCC_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MPS2_SCC_RESET) || \ false) static inline void _nocheck__trace_mps2_scc_reset(void) { if (trace_event_get_state(TRACE_MPS2_SCC_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 104 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mps2_scc_reset " "MPS2 SCC: reset" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 3220 "trace/trace-hw_misc.h" } else { #line 104 "../hw/misc/trace-events" qemu_log("mps2_scc_reset " "MPS2 SCC: reset" "\n"); #line 3224 "trace/trace-hw_misc.h" } } } static inline void trace_mps2_scc_reset(void) { if (true) { _nocheck__trace_mps2_scc_reset(); } } #define TRACE_MPS2_SCC_CFG_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MPS2_SCC_CFG_WRITE) || \ false) static inline void _nocheck__trace_mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) { if (trace_event_get_state(TRACE_MPS2_SCC_CFG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 105 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mps2_scc_cfg_write " "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , function, device, value); #line 3251 "trace/trace-hw_misc.h" } else { #line 105 "../hw/misc/trace-events" qemu_log("mps2_scc_cfg_write " "MPS2 SCC config write: function %d device %d data 0x%" PRIx32 "\n", function, device, value); #line 3255 "trace/trace-hw_misc.h" } } } static inline void trace_mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) { if (true) { _nocheck__trace_mps2_scc_cfg_write(function, device, value); } } #define TRACE_MPS2_SCC_CFG_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MPS2_SCC_CFG_READ) || \ false) static inline void _nocheck__trace_mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) { if (trace_event_get_state(TRACE_MPS2_SCC_CFG_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 106 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mps2_scc_cfg_read " "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , function, device, value); #line 3282 "trace/trace-hw_misc.h" } else { #line 106 "../hw/misc/trace-events" qemu_log("mps2_scc_cfg_read " "MPS2 SCC config read: function %d device %d data 0x%" PRIx32 "\n", function, device, value); #line 3286 "trace/trace-hw_misc.h" } } } static inline void trace_mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) { if (true) { _nocheck__trace_mps2_scc_cfg_read(function, device, value); } } #define TRACE_MPS2_FPGAIO_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MPS2_FPGAIO_READ) || \ false) static inline void _nocheck__trace_mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_MPS2_FPGAIO_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 109 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mps2_fpgaio_read " "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 3313 "trace/trace-hw_misc.h" } else { #line 109 "../hw/misc/trace-events" qemu_log("mps2_fpgaio_read " "MPS2 FPGAIO read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 3317 "trace/trace-hw_misc.h" } } } static inline void trace_mps2_fpgaio_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_mps2_fpgaio_read(offset, data, size); } } #define TRACE_MPS2_FPGAIO_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MPS2_FPGAIO_WRITE) || \ false) static inline void _nocheck__trace_mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_MPS2_FPGAIO_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 110 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mps2_fpgaio_write " "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 3344 "trace/trace-hw_misc.h" } else { #line 110 "../hw/misc/trace-events" qemu_log("mps2_fpgaio_write " "MPS2 FPGAIO write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 3348 "trace/trace-hw_misc.h" } } } static inline void trace_mps2_fpgaio_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_mps2_fpgaio_write(offset, data, size); } } #define TRACE_MPS2_FPGAIO_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MPS2_FPGAIO_RESET) || \ false) static inline void _nocheck__trace_mps2_fpgaio_reset(void) { if (trace_event_get_state(TRACE_MPS2_FPGAIO_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 111 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mps2_fpgaio_reset " "MPS2 FPGAIO: reset" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 3375 "trace/trace-hw_misc.h" } else { #line 111 "../hw/misc/trace-events" qemu_log("mps2_fpgaio_reset " "MPS2 FPGAIO: reset" "\n"); #line 3379 "trace/trace-hw_misc.h" } } } static inline void trace_mps2_fpgaio_reset(void) { if (true) { _nocheck__trace_mps2_fpgaio_reset(); } } #define TRACE_MSF2_SYSREG_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MSF2_SYSREG_WRITE) || \ false) static inline void _nocheck__trace_msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) { if (trace_event_get_state(TRACE_MSF2_SYSREG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 114 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:msf2_sysreg_write " "msf2-sysreg write: addr 0x%08" PRIx64 " data 0x%" PRIx32 " prev 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, val, prev); #line 3406 "trace/trace-hw_misc.h" } else { #line 114 "../hw/misc/trace-events" qemu_log("msf2_sysreg_write " "msf2-sysreg write: addr 0x%08" PRIx64 " data 0x%" PRIx32 " prev 0x%" PRIx32 "\n", offset, val, prev); #line 3410 "trace/trace-hw_misc.h" } } } static inline void trace_msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) { if (true) { _nocheck__trace_msf2_sysreg_write(offset, val, prev); } } #define TRACE_MSF2_SYSREG_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MSF2_SYSREG_READ) || \ false) static inline void _nocheck__trace_msf2_sysreg_read(uint64_t offset, uint32_t val) { if (trace_event_get_state(TRACE_MSF2_SYSREG_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 115 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:msf2_sysreg_read " "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, val); #line 3437 "trace/trace-hw_misc.h" } else { #line 115 "../hw/misc/trace-events" qemu_log("msf2_sysreg_read " "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08" PRIx32 "\n", offset, val); #line 3441 "trace/trace-hw_misc.h" } } } static inline void trace_msf2_sysreg_read(uint64_t offset, uint32_t val) { if (true) { _nocheck__trace_msf2_sysreg_read(offset, val); } } #define TRACE_MSF2_SYSREG_WRITE_PLL_STATUS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MSF2_SYSREG_WRITE_PLL_STATUS) || \ false) static inline void _nocheck__trace_msf2_sysreg_write_pll_status(void) { if (trace_event_get_state(TRACE_MSF2_SYSREG_WRITE_PLL_STATUS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 116 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:msf2_sysreg_write_pll_status " "Invalid write to read only PLL status register" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 3468 "trace/trace-hw_misc.h" } else { #line 116 "../hw/misc/trace-events" qemu_log("msf2_sysreg_write_pll_status " "Invalid write to read only PLL status register" "\n"); #line 3472 "trace/trace-hw_misc.h" } } } static inline void trace_msf2_sysreg_write_pll_status(void) { if (true) { _nocheck__trace_msf2_sysreg_write_pll_status(); } } #define TRACE_IMX7_GPR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX7_GPR_READ) || \ false) static inline void _nocheck__trace_imx7_gpr_read(uint64_t offset) { if (trace_event_get_state(TRACE_IMX7_GPR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 119 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx7_gpr_read " "addr 0x%08" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset); #line 3499 "trace/trace-hw_misc.h" } else { #line 119 "../hw/misc/trace-events" qemu_log("imx7_gpr_read " "addr 0x%08" PRIx64 "\n", offset); #line 3503 "trace/trace-hw_misc.h" } } } static inline void trace_imx7_gpr_read(uint64_t offset) { if (true) { _nocheck__trace_imx7_gpr_read(offset); } } #define TRACE_IMX7_GPR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX7_GPR_WRITE) || \ false) static inline void _nocheck__trace_imx7_gpr_write(uint64_t offset, uint64_t value) { if (trace_event_get_state(TRACE_IMX7_GPR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 120 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx7_gpr_write " "addr 0x%08" PRIx64 "value 0x%08" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value); #line 3530 "trace/trace-hw_misc.h" } else { #line 120 "../hw/misc/trace-events" qemu_log("imx7_gpr_write " "addr 0x%08" PRIx64 "value 0x%08" PRIx64 "\n", offset, value); #line 3534 "trace/trace-hw_misc.h" } } } static inline void trace_imx7_gpr_write(uint64_t offset, uint64_t value) { if (true) { _nocheck__trace_imx7_gpr_write(offset, value); } } #define TRACE_IMX7_SNVS_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX7_SNVS_READ) || \ false) static inline void _nocheck__trace_imx7_snvs_read(uint64_t offset, uint64_t value, unsigned size) { if (trace_event_get_state(TRACE_IMX7_SNVS_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 123 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx7_snvs_read " "i.MX SNVS read: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value, size); #line 3561 "trace/trace-hw_misc.h" } else { #line 123 "../hw/misc/trace-events" qemu_log("imx7_snvs_read " "i.MX SNVS read: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" "\n", offset, value, size); #line 3565 "trace/trace-hw_misc.h" } } } static inline void trace_imx7_snvs_read(uint64_t offset, uint64_t value, unsigned size) { if (true) { _nocheck__trace_imx7_snvs_read(offset, value, size); } } #define TRACE_IMX7_SNVS_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX7_SNVS_WRITE) || \ false) static inline void _nocheck__trace_imx7_snvs_write(uint64_t offset, uint64_t value, unsigned size) { if (trace_event_get_state(TRACE_IMX7_SNVS_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 124 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx7_snvs_write " "i.MX SNVS write: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value, size); #line 3592 "trace/trace-hw_misc.h" } else { #line 124 "../hw/misc/trace-events" qemu_log("imx7_snvs_write " "i.MX SNVS write: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" "\n", offset, value, size); #line 3596 "trace/trace-hw_misc.h" } } } static inline void trace_imx7_snvs_write(uint64_t offset, uint64_t value, unsigned size) { if (true) { _nocheck__trace_imx7_snvs_write(offset, value, size); } } #define TRACE_MOS6522_SET_COUNTER_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MOS6522_SET_COUNTER) || \ false) static inline void _nocheck__trace_mos6522_set_counter(int index, unsigned int val) { if (trace_event_get_state(TRACE_MOS6522_SET_COUNTER) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 127 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mos6522_set_counter " "T%d.counter=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , index, val); #line 3623 "trace/trace-hw_misc.h" } else { #line 127 "../hw/misc/trace-events" qemu_log("mos6522_set_counter " "T%d.counter=%d" "\n", index, val); #line 3627 "trace/trace-hw_misc.h" } } } static inline void trace_mos6522_set_counter(int index, unsigned int val) { if (true) { _nocheck__trace_mos6522_set_counter(index, val); } } #define TRACE_MOS6522_GET_NEXT_IRQ_TIME_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MOS6522_GET_NEXT_IRQ_TIME) || \ false) static inline void _nocheck__trace_mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) { if (trace_event_get_state(TRACE_MOS6522_GET_NEXT_IRQ_TIME) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 128 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mos6522_get_next_irq_time " "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , latch, d, delta); #line 3654 "trace/trace-hw_misc.h" } else { #line 128 "../hw/misc/trace-events" qemu_log("mos6522_get_next_irq_time " "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64 "\n", latch, d, delta); #line 3658 "trace/trace-hw_misc.h" } } } static inline void trace_mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) { if (true) { _nocheck__trace_mos6522_get_next_irq_time(latch, d, delta); } } #define TRACE_MOS6522_SET_SR_INT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MOS6522_SET_SR_INT) || \ false) static inline void _nocheck__trace_mos6522_set_sr_int(void) { if (trace_event_get_state(TRACE_MOS6522_SET_SR_INT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 129 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mos6522_set_sr_int " "set sr_int" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 3685 "trace/trace-hw_misc.h" } else { #line 129 "../hw/misc/trace-events" qemu_log("mos6522_set_sr_int " "set sr_int" "\n"); #line 3689 "trace/trace-hw_misc.h" } } } static inline void trace_mos6522_set_sr_int(void) { if (true) { _nocheck__trace_mos6522_set_sr_int(); } } #define TRACE_MOS6522_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MOS6522_WRITE) || \ false) static inline void _nocheck__trace_mos6522_write(uint64_t addr, const char * name, uint64_t val) { if (trace_event_get_state(TRACE_MOS6522_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 130 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mos6522_write " "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, name, val); #line 3716 "trace/trace-hw_misc.h" } else { #line 130 "../hw/misc/trace-events" qemu_log("mos6522_write " "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64 "\n", addr, name, val); #line 3720 "trace/trace-hw_misc.h" } } } static inline void trace_mos6522_write(uint64_t addr, const char * name, uint64_t val) { if (true) { _nocheck__trace_mos6522_write(addr, name, val); } } #define TRACE_MOS6522_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_MOS6522_READ) || \ false) static inline void _nocheck__trace_mos6522_read(uint64_t addr, const char * name, unsigned val) { if (trace_event_get_state(TRACE_MOS6522_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 131 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:mos6522_read " "reg=0x%"PRIx64 " [%s] val=0x%x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, name, val); #line 3747 "trace/trace-hw_misc.h" } else { #line 131 "../hw/misc/trace-events" qemu_log("mos6522_read " "reg=0x%"PRIx64 " [%s] val=0x%x" "\n", addr, name, val); #line 3751 "trace/trace-hw_misc.h" } } } static inline void trace_mos6522_read(uint64_t addr, const char * name, unsigned val) { if (true) { _nocheck__trace_mos6522_read(addr, name, val); } } #define TRACE_NPCM7XX_CLK_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_CLK_READ) || \ false) static inline void _nocheck__trace_npcm7xx_clk_read(uint64_t offset, uint32_t value) { if (trace_event_get_state(TRACE_NPCM7XX_CLK_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 134 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_clk_read " " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value); #line 3778 "trace/trace-hw_misc.h" } else { #line 134 "../hw/misc/trace-events" qemu_log("npcm7xx_clk_read " " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", offset, value); #line 3782 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_clk_read(uint64_t offset, uint32_t value) { if (true) { _nocheck__trace_npcm7xx_clk_read(offset, value); } } #define TRACE_NPCM7XX_CLK_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_CLK_WRITE) || \ false) static inline void _nocheck__trace_npcm7xx_clk_write(uint64_t offset, uint32_t value) { if (trace_event_get_state(TRACE_NPCM7XX_CLK_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 135 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_clk_write " "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value); #line 3809 "trace/trace-hw_misc.h" } else { #line 135 "../hw/misc/trace-events" qemu_log("npcm7xx_clk_write " "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", offset, value); #line 3813 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_clk_write(uint64_t offset, uint32_t value) { if (true) { _nocheck__trace_npcm7xx_clk_write(offset, value); } } #define TRACE_NPCM7XX_GCR_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_GCR_READ) || \ false) static inline void _nocheck__trace_npcm7xx_gcr_read(uint64_t offset, uint32_t value) { if (trace_event_get_state(TRACE_NPCM7XX_GCR_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 138 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_gcr_read " " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value); #line 3840 "trace/trace-hw_misc.h" } else { #line 138 "../hw/misc/trace-events" qemu_log("npcm7xx_gcr_read " " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", offset, value); #line 3844 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_gcr_read(uint64_t offset, uint32_t value) { if (true) { _nocheck__trace_npcm7xx_gcr_read(offset, value); } } #define TRACE_NPCM7XX_GCR_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_GCR_WRITE) || \ false) static inline void _nocheck__trace_npcm7xx_gcr_write(uint64_t offset, uint32_t value) { if (trace_event_get_state(TRACE_NPCM7XX_GCR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 139 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_gcr_write " "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value); #line 3871 "trace/trace-hw_misc.h" } else { #line 139 "../hw/misc/trace-events" qemu_log("npcm7xx_gcr_write " "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", offset, value); #line 3875 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_gcr_write(uint64_t offset, uint32_t value) { if (true) { _nocheck__trace_npcm7xx_gcr_write(offset, value); } } #define TRACE_NPCM7XX_MFT_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_READ) || \ false) static inline void _nocheck__trace_npcm7xx_mft_read(const char * name, uint64_t offset, uint16_t value) { if (trace_event_get_state(TRACE_NPCM7XX_MFT_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 142 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_mft_read " "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , name, offset, value); #line 3902 "trace/trace-hw_misc.h" } else { #line 142 "../hw/misc/trace-events" qemu_log("npcm7xx_mft_read " "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 "\n", name, offset, value); #line 3906 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_mft_read(const char * name, uint64_t offset, uint16_t value) { if (true) { _nocheck__trace_npcm7xx_mft_read(name, offset, value); } } #define TRACE_NPCM7XX_MFT_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_WRITE) || \ false) static inline void _nocheck__trace_npcm7xx_mft_write(const char * name, uint64_t offset, uint16_t value) { if (trace_event_get_state(TRACE_NPCM7XX_MFT_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 143 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_mft_write " "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , name, offset, value); #line 3933 "trace/trace-hw_misc.h" } else { #line 143 "../hw/misc/trace-events" qemu_log("npcm7xx_mft_write " "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 "\n", name, offset, value); #line 3937 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_mft_write(const char * name, uint64_t offset, uint16_t value) { if (true) { _nocheck__trace_npcm7xx_mft_write(name, offset, value); } } #define TRACE_NPCM7XX_MFT_RPM_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_RPM) || \ false) static inline void _nocheck__trace_npcm7xx_mft_rpm(const char * clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty) { if (trace_event_get_state(TRACE_NPCM7XX_MFT_RPM) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 144 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_mft_rpm " " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , clock, clock_hz, state, cnt, rpm, duty); #line 3964 "trace/trace-hw_misc.h" } else { #line 144 "../hw/misc/trace-events" qemu_log("npcm7xx_mft_rpm " " fan clk: %s clock_hz: %" PRIu32 ", state: %d, cnt: %" PRIi32 ", rpm: %" PRIu32 ", duty: %" PRIu32 "\n", clock, clock_hz, state, cnt, rpm, duty); #line 3968 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_mft_rpm(const char * clock, uint32_t clock_hz, int state, int32_t cnt, uint32_t rpm, uint32_t duty) { if (true) { _nocheck__trace_npcm7xx_mft_rpm(clock, clock_hz, state, cnt, rpm, duty); } } #define TRACE_NPCM7XX_MFT_CAPTURE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_CAPTURE) || \ false) static inline void _nocheck__trace_npcm7xx_mft_capture(const char * name, int irq_level) { if (trace_event_get_state(TRACE_NPCM7XX_MFT_CAPTURE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 145 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_mft_capture " "%s: level: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , name, irq_level); #line 3995 "trace/trace-hw_misc.h" } else { #line 145 "../hw/misc/trace-events" qemu_log("npcm7xx_mft_capture " "%s: level: %d" "\n", name, irq_level); #line 3999 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_mft_capture(const char * name, int irq_level) { if (true) { _nocheck__trace_npcm7xx_mft_capture(name, irq_level); } } #define TRACE_NPCM7XX_MFT_UPDATE_CLOCK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_UPDATE_CLOCK) || \ false) static inline void _nocheck__trace_npcm7xx_mft_update_clock(const char * name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period) { if (trace_event_get_state(TRACE_NPCM7XX_MFT_UPDATE_CLOCK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 146 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_mft_update_clock " "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , name, sel, clock_period, prescaled_clock_period); #line 4026 "trace/trace-hw_misc.h" } else { #line 146 "../hw/misc/trace-events" qemu_log("npcm7xx_mft_update_clock " "%s: sel: 0x%02" PRIx16 ", period: %" PRIu64 ", prescaled: %" PRIu64 "\n", name, sel, clock_period, prescaled_clock_period); #line 4030 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_mft_update_clock(const char * name, uint16_t sel, uint64_t clock_period, uint64_t prescaled_clock_period) { if (true) { _nocheck__trace_npcm7xx_mft_update_clock(name, sel, clock_period, prescaled_clock_period); } } #define TRACE_NPCM7XX_MFT_SET_DUTY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_MFT_SET_DUTY) || \ false) static inline void _nocheck__trace_npcm7xx_mft_set_duty(const char * name, int n, int value) { if (trace_event_get_state(TRACE_NPCM7XX_MFT_SET_DUTY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 147 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_mft_set_duty " "%s[%d]: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , name, n, value); #line 4057 "trace/trace-hw_misc.h" } else { #line 147 "../hw/misc/trace-events" qemu_log("npcm7xx_mft_set_duty " "%s[%d]: %d" "\n", name, n, value); #line 4061 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_mft_set_duty(const char * name, int n, int value) { if (true) { _nocheck__trace_npcm7xx_mft_set_duty(name, n, value); } } #define TRACE_NPCM7XX_RNG_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_RNG_READ) || \ false) static inline void _nocheck__trace_npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) { if (trace_event_get_state(TRACE_NPCM7XX_RNG_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 150 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_rng_read " "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value, size); #line 4088 "trace/trace-hw_misc.h" } else { #line 150 "../hw/misc/trace-events" qemu_log("npcm7xx_rng_read " "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n", offset, value, size); #line 4092 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) { if (true) { _nocheck__trace_npcm7xx_rng_read(offset, value, size); } } #define TRACE_NPCM7XX_RNG_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_RNG_WRITE) || \ false) static inline void _nocheck__trace_npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) { if (trace_event_get_state(TRACE_NPCM7XX_RNG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 151 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_rng_write " "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value, size); #line 4119 "trace/trace-hw_misc.h" } else { #line 151 "../hw/misc/trace-events" qemu_log("npcm7xx_rng_write " "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" "\n", offset, value, size); #line 4123 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) { if (true) { _nocheck__trace_npcm7xx_rng_write(offset, value, size); } } #define TRACE_NPCM7XX_PWM_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_PWM_READ) || \ false) static inline void _nocheck__trace_npcm7xx_pwm_read(const char * id, uint64_t offset, uint32_t value) { if (trace_event_get_state(TRACE_NPCM7XX_PWM_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 154 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_pwm_read " "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , id, offset, value); #line 4150 "trace/trace-hw_misc.h" } else { #line 154 "../hw/misc/trace-events" qemu_log("npcm7xx_pwm_read " "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", id, offset, value); #line 4154 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_pwm_read(const char * id, uint64_t offset, uint32_t value) { if (true) { _nocheck__trace_npcm7xx_pwm_read(id, offset, value); } } #define TRACE_NPCM7XX_PWM_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_PWM_WRITE) || \ false) static inline void _nocheck__trace_npcm7xx_pwm_write(const char * id, uint64_t offset, uint32_t value) { if (trace_event_get_state(TRACE_NPCM7XX_PWM_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 155 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_pwm_write " "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , id, offset, value); #line 4181 "trace/trace-hw_misc.h" } else { #line 155 "../hw/misc/trace-events" qemu_log("npcm7xx_pwm_write " "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 "\n", id, offset, value); #line 4185 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_pwm_write(const char * id, uint64_t offset, uint32_t value) { if (true) { _nocheck__trace_npcm7xx_pwm_write(id, offset, value); } } #define TRACE_NPCM7XX_PWM_UPDATE_FREQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_PWM_UPDATE_FREQ) || \ false) static inline void _nocheck__trace_npcm7xx_pwm_update_freq(const char * id, uint8_t index, uint32_t old_value, uint32_t new_value) { if (trace_event_get_state(TRACE_NPCM7XX_PWM_UPDATE_FREQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 156 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_pwm_update_freq " "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , id, index, old_value, new_value); #line 4212 "trace/trace-hw_misc.h" } else { #line 156 "../hw/misc/trace-events" qemu_log("npcm7xx_pwm_update_freq " "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" "\n", id, index, old_value, new_value); #line 4216 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_pwm_update_freq(const char * id, uint8_t index, uint32_t old_value, uint32_t new_value) { if (true) { _nocheck__trace_npcm7xx_pwm_update_freq(id, index, old_value, new_value); } } #define TRACE_NPCM7XX_PWM_UPDATE_DUTY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_NPCM7XX_PWM_UPDATE_DUTY) || \ false) static inline void _nocheck__trace_npcm7xx_pwm_update_duty(const char * id, uint8_t index, uint32_t old_value, uint32_t new_value) { if (trace_event_get_state(TRACE_NPCM7XX_PWM_UPDATE_DUTY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 157 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:npcm7xx_pwm_update_duty " "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , id, index, old_value, new_value); #line 4243 "trace/trace-hw_misc.h" } else { #line 157 "../hw/misc/trace-events" qemu_log("npcm7xx_pwm_update_duty " "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" "\n", id, index, old_value, new_value); #line 4247 "trace/trace-hw_misc.h" } } } static inline void trace_npcm7xx_pwm_update_duty(const char * id, uint8_t index, uint32_t old_value, uint32_t new_value) { if (true) { _nocheck__trace_npcm7xx_pwm_update_duty(id, index, old_value, new_value); } } #define TRACE_STM32_RCC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32_RCC_READ) || \ false) static inline void _nocheck__trace_stm32_rcc_read(uint64_t addr, uint64_t data) { if (trace_event_get_state(TRACE_STM32_RCC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 160 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32_rcc_read " "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, data); #line 4274 "trace/trace-hw_misc.h" } else { #line 160 "../hw/misc/trace-events" qemu_log("stm32_rcc_read " "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data); #line 4278 "trace/trace-hw_misc.h" } } } static inline void trace_stm32_rcc_read(uint64_t addr, uint64_t data) { if (true) { _nocheck__trace_stm32_rcc_read(addr, data); } } #define TRACE_STM32_RCC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32_RCC_WRITE) || \ false) static inline void _nocheck__trace_stm32_rcc_write(uint64_t addr, uint64_t data) { if (trace_event_get_state(TRACE_STM32_RCC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 161 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32_rcc_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, data); #line 4305 "trace/trace-hw_misc.h" } else { #line 161 "../hw/misc/trace-events" qemu_log("stm32_rcc_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data); #line 4309 "trace/trace-hw_misc.h" } } } static inline void trace_stm32_rcc_write(uint64_t addr, uint64_t data) { if (true) { _nocheck__trace_stm32_rcc_write(addr, data); } } #define TRACE_STM32_RCC_PULSE_ENABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32_RCC_PULSE_ENABLE) || \ false) static inline void _nocheck__trace_stm32_rcc_pulse_enable(int line, int level) { if (trace_event_get_state(TRACE_STM32_RCC_PULSE_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 162 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32_rcc_pulse_enable " "Enable: %d to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , line, level); #line 4336 "trace/trace-hw_misc.h" } else { #line 162 "../hw/misc/trace-events" qemu_log("stm32_rcc_pulse_enable " "Enable: %d to %d" "\n", line, level); #line 4340 "trace/trace-hw_misc.h" } } } static inline void trace_stm32_rcc_pulse_enable(int line, int level) { if (true) { _nocheck__trace_stm32_rcc_pulse_enable(line, level); } } #define TRACE_STM32_RCC_PULSE_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32_RCC_PULSE_RESET) || \ false) static inline void _nocheck__trace_stm32_rcc_pulse_reset(int line, int level) { if (trace_event_get_state(TRACE_STM32_RCC_PULSE_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 163 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32_rcc_pulse_reset " "Reset: %d to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , line, level); #line 4367 "trace/trace-hw_misc.h" } else { #line 163 "../hw/misc/trace-events" qemu_log("stm32_rcc_pulse_reset " "Reset: %d to %d" "\n", line, level); #line 4371 "trace/trace-hw_misc.h" } } } static inline void trace_stm32_rcc_pulse_reset(int line, int level) { if (true) { _nocheck__trace_stm32_rcc_pulse_reset(line, level); } } #define TRACE_STM32F4XX_SYSCFG_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_SYSCFG_SET_IRQ) || \ false) static inline void _nocheck__trace_stm32f4xx_syscfg_set_irq(int gpio, int line, int level) { if (trace_event_get_state(TRACE_STM32F4XX_SYSCFG_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 166 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32f4xx_syscfg_set_irq " "Interrupt: GPIO: %d, Line: %d; Level: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , gpio, line, level); #line 4398 "trace/trace-hw_misc.h" } else { #line 166 "../hw/misc/trace-events" qemu_log("stm32f4xx_syscfg_set_irq " "Interrupt: GPIO: %d, Line: %d; Level: %d" "\n", gpio, line, level); #line 4402 "trace/trace-hw_misc.h" } } } static inline void trace_stm32f4xx_syscfg_set_irq(int gpio, int line, int level) { if (true) { _nocheck__trace_stm32f4xx_syscfg_set_irq(gpio, line, level); } } #define TRACE_STM32F4XX_PULSE_EXTI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_PULSE_EXTI) || \ false) static inline void _nocheck__trace_stm32f4xx_pulse_exti(int irq) { if (trace_event_get_state(TRACE_STM32F4XX_PULSE_EXTI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 167 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32f4xx_pulse_exti " "Pulse EXTI: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq); #line 4429 "trace/trace-hw_misc.h" } else { #line 167 "../hw/misc/trace-events" qemu_log("stm32f4xx_pulse_exti " "Pulse EXTI: %d" "\n", irq); #line 4433 "trace/trace-hw_misc.h" } } } static inline void trace_stm32f4xx_pulse_exti(int irq) { if (true) { _nocheck__trace_stm32f4xx_pulse_exti(irq); } } #define TRACE_STM32F4XX_SYSCFG_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_SYSCFG_READ) || \ false) static inline void _nocheck__trace_stm32f4xx_syscfg_read(uint64_t addr) { if (trace_event_get_state(TRACE_STM32F4XX_SYSCFG_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 168 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32f4xx_syscfg_read " "reg read: addr: 0x%" PRIx64 " " "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr); #line 4460 "trace/trace-hw_misc.h" } else { #line 168 "../hw/misc/trace-events" qemu_log("stm32f4xx_syscfg_read " "reg read: addr: 0x%" PRIx64 " " "\n", addr); #line 4464 "trace/trace-hw_misc.h" } } } static inline void trace_stm32f4xx_syscfg_read(uint64_t addr) { if (true) { _nocheck__trace_stm32f4xx_syscfg_read(addr); } } #define TRACE_STM32F4XX_SYSCFG_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_SYSCFG_WRITE) || \ false) static inline void _nocheck__trace_stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) { if (trace_event_get_state(TRACE_STM32F4XX_SYSCFG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 169 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32f4xx_syscfg_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, data); #line 4491 "trace/trace-hw_misc.h" } else { #line 169 "../hw/misc/trace-events" qemu_log("stm32f4xx_syscfg_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data); #line 4495 "trace/trace-hw_misc.h" } } } static inline void trace_stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) { if (true) { _nocheck__trace_stm32f4xx_syscfg_write(addr, data); } } #define TRACE_STM32F4XX_EXTI_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_EXTI_SET_IRQ) || \ false) static inline void _nocheck__trace_stm32f4xx_exti_set_irq(int irq, int level) { if (trace_event_get_state(TRACE_STM32F4XX_EXTI_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 172 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32f4xx_exti_set_irq " "Set EXTI: %d to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 4522 "trace/trace-hw_misc.h" } else { #line 172 "../hw/misc/trace-events" qemu_log("stm32f4xx_exti_set_irq " "Set EXTI: %d to %d" "\n", irq, level); #line 4526 "trace/trace-hw_misc.h" } } } static inline void trace_stm32f4xx_exti_set_irq(int irq, int level) { if (true) { _nocheck__trace_stm32f4xx_exti_set_irq(irq, level); } } #define TRACE_STM32F4XX_EXTI_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_EXTI_READ) || \ false) static inline void _nocheck__trace_stm32f4xx_exti_read(uint64_t addr) { if (trace_event_get_state(TRACE_STM32F4XX_EXTI_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 173 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32f4xx_exti_read " "reg read: addr: 0x%" PRIx64 " " "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr); #line 4553 "trace/trace-hw_misc.h" } else { #line 173 "../hw/misc/trace-events" qemu_log("stm32f4xx_exti_read " "reg read: addr: 0x%" PRIx64 " " "\n", addr); #line 4557 "trace/trace-hw_misc.h" } } } static inline void trace_stm32f4xx_exti_read(uint64_t addr) { if (true) { _nocheck__trace_stm32f4xx_exti_read(addr); } } #define TRACE_STM32F4XX_EXTI_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32F4XX_EXTI_WRITE) || \ false) static inline void _nocheck__trace_stm32f4xx_exti_write(uint64_t addr, uint64_t data) { if (trace_event_get_state(TRACE_STM32F4XX_EXTI_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 174 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32f4xx_exti_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, data); #line 4584 "trace/trace-hw_misc.h" } else { #line 174 "../hw/misc/trace-events" qemu_log("stm32f4xx_exti_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data); #line 4588 "trace/trace-hw_misc.h" } } } static inline void trace_stm32f4xx_exti_write(uint64_t addr, uint64_t data) { if (true) { _nocheck__trace_stm32f4xx_exti_write(addr, data); } } #define TRACE_STM32L4X5_SYSCFG_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_SYSCFG_SET_IRQ) || \ false) static inline void _nocheck__trace_stm32l4x5_syscfg_set_irq(int gpio, int line, int level) { if (trace_event_get_state(TRACE_STM32L4X5_SYSCFG_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 177 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_syscfg_set_irq " "irq from GPIO: %d, line: %d, level: %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , gpio, line, level); #line 4615 "trace/trace-hw_misc.h" } else { #line 177 "../hw/misc/trace-events" qemu_log("stm32l4x5_syscfg_set_irq " "irq from GPIO: %d, line: %d, level: %d" "\n", gpio, line, level); #line 4619 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_syscfg_set_irq(int gpio, int line, int level) { if (true) { _nocheck__trace_stm32l4x5_syscfg_set_irq(gpio, line, level); } } #define TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI) || \ false) static inline void _nocheck__trace_stm32l4x5_syscfg_forward_exti(int irq) { if (trace_event_get_state(TRACE_STM32L4X5_SYSCFG_FORWARD_EXTI) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 178 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_syscfg_forward_exti " "irq %d forwarded to EXTI" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq); #line 4646 "trace/trace-hw_misc.h" } else { #line 178 "../hw/misc/trace-events" qemu_log("stm32l4x5_syscfg_forward_exti " "irq %d forwarded to EXTI" "\n", irq); #line 4650 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_syscfg_forward_exti(int irq) { if (true) { _nocheck__trace_stm32l4x5_syscfg_forward_exti(irq); } } #define TRACE_STM32L4X5_SYSCFG_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_SYSCFG_READ) || \ false) static inline void _nocheck__trace_stm32l4x5_syscfg_read(uint64_t addr) { if (trace_event_get_state(TRACE_STM32L4X5_SYSCFG_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 179 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_syscfg_read " "reg read: addr: 0x%" PRIx64 " " "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr); #line 4677 "trace/trace-hw_misc.h" } else { #line 179 "../hw/misc/trace-events" qemu_log("stm32l4x5_syscfg_read " "reg read: addr: 0x%" PRIx64 " " "\n", addr); #line 4681 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_syscfg_read(uint64_t addr) { if (true) { _nocheck__trace_stm32l4x5_syscfg_read(addr); } } #define TRACE_STM32L4X5_SYSCFG_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_SYSCFG_WRITE) || \ false) static inline void _nocheck__trace_stm32l4x5_syscfg_write(uint64_t addr, uint64_t data) { if (trace_event_get_state(TRACE_STM32L4X5_SYSCFG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 180 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_syscfg_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, data); #line 4708 "trace/trace-hw_misc.h" } else { #line 180 "../hw/misc/trace-events" qemu_log("stm32l4x5_syscfg_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data); #line 4712 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_syscfg_write(uint64_t addr, uint64_t data) { if (true) { _nocheck__trace_stm32l4x5_syscfg_write(addr, data); } } #define TRACE_STM32L4X5_EXTI_SET_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_EXTI_SET_IRQ) || \ false) static inline void _nocheck__trace_stm32l4x5_exti_set_irq(int irq, int level) { if (trace_event_get_state(TRACE_STM32L4X5_EXTI_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 183 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_exti_set_irq " "Set EXTI: %d to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , irq, level); #line 4739 "trace/trace-hw_misc.h" } else { #line 183 "../hw/misc/trace-events" qemu_log("stm32l4x5_exti_set_irq " "Set EXTI: %d to %d" "\n", irq, level); #line 4743 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_exti_set_irq(int irq, int level) { if (true) { _nocheck__trace_stm32l4x5_exti_set_irq(irq, level); } } #define TRACE_STM32L4X5_EXTI_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_EXTI_READ) || \ false) static inline void _nocheck__trace_stm32l4x5_exti_read(uint64_t addr, uint64_t data) { if (trace_event_get_state(TRACE_STM32L4X5_EXTI_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 184 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_exti_read " "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, data); #line 4770 "trace/trace-hw_misc.h" } else { #line 184 "../hw/misc/trace-events" qemu_log("stm32l4x5_exti_read " "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data); #line 4774 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_exti_read(uint64_t addr, uint64_t data) { if (true) { _nocheck__trace_stm32l4x5_exti_read(addr, data); } } #define TRACE_STM32L4X5_EXTI_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_EXTI_WRITE) || \ false) static inline void _nocheck__trace_stm32l4x5_exti_write(uint64_t addr, uint64_t data) { if (trace_event_get_state(TRACE_STM32L4X5_EXTI_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 185 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_exti_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, data); #line 4801 "trace/trace-hw_misc.h" } else { #line 185 "../hw/misc/trace-events" qemu_log("stm32l4x5_exti_write " "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 "" "\n", addr, data); #line 4805 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_exti_write(uint64_t addr, uint64_t data) { if (true) { _nocheck__trace_stm32l4x5_exti_write(addr, data); } } #define TRACE_STM32L4X5_RCC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_READ) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_read(uint64_t addr, uint32_t data) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 188 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_read " "RCC: Read <0x%" PRIx64 "> -> 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, data); #line 4832 "trace/trace-hw_misc.h" } else { #line 188 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_read " "RCC: Read <0x%" PRIx64 "> -> 0x%" PRIx32 "\n", addr, data); #line 4836 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_read(uint64_t addr, uint32_t data) { if (true) { _nocheck__trace_stm32l4x5_rcc_read(addr, data); } } #define TRACE_STM32L4X5_RCC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_WRITE) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_write(uint64_t addr, uint32_t data) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 189 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_write " "RCC: Write <0x%" PRIx64 "> <- 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, data); #line 4863 "trace/trace-hw_misc.h" } else { #line 189 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_write " "RCC: Write <0x%" PRIx64 "> <- 0x%" PRIx32 "\n", addr, data); #line 4867 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_write(uint64_t addr, uint32_t data) { if (true) { _nocheck__trace_stm32l4x5_rcc_write(addr, data); } } #define TRACE_STM32L4X5_RCC_MUX_ENABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_MUX_ENABLE) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_mux_enable(uint32_t mux_id) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_MUX_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 190 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_mux_enable " "RCC: Mux %d enabled" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , mux_id); #line 4894 "trace/trace-hw_misc.h" } else { #line 190 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_mux_enable " "RCC: Mux %d enabled" "\n", mux_id); #line 4898 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_mux_enable(uint32_t mux_id) { if (true) { _nocheck__trace_stm32l4x5_rcc_mux_enable(mux_id); } } #define TRACE_STM32L4X5_RCC_MUX_DISABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_MUX_DISABLE) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_mux_disable(uint32_t mux_id) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_MUX_DISABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 191 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_mux_disable " "RCC: Mux %d disabled" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , mux_id); #line 4925 "trace/trace-hw_misc.h" } else { #line 191 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_mux_disable " "RCC: Mux %d disabled" "\n", mux_id); #line 4929 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_mux_disable(uint32_t mux_id) { if (true) { _nocheck__trace_stm32l4x5_rcc_mux_disable(mux_id); } } #define TRACE_STM32L4X5_RCC_MUX_SET_FACTOR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_MUX_SET_FACTOR) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_mux_set_factor(uint32_t mux_id, uint32_t old_multiplier, uint32_t new_multiplier, uint32_t old_divider, uint32_t new_divider) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_MUX_SET_FACTOR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 192 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_mux_set_factor " "RCC: Mux %d factor changed: multiplier (%u -> %u), divider (%u -> %u)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , mux_id, old_multiplier, new_multiplier, old_divider, new_divider); #line 4956 "trace/trace-hw_misc.h" } else { #line 192 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_mux_set_factor " "RCC: Mux %d factor changed: multiplier (%u -> %u), divider (%u -> %u)" "\n", mux_id, old_multiplier, new_multiplier, old_divider, new_divider); #line 4960 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_mux_set_factor(uint32_t mux_id, uint32_t old_multiplier, uint32_t new_multiplier, uint32_t old_divider, uint32_t new_divider) { if (true) { _nocheck__trace_stm32l4x5_rcc_mux_set_factor(mux_id, old_multiplier, new_multiplier, old_divider, new_divider); } } #define TRACE_STM32L4X5_RCC_MUX_SET_SRC_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_MUX_SET_SRC) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_mux_set_src(uint32_t mux_id, uint32_t old_src, uint32_t new_src) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_MUX_SET_SRC) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 193 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_mux_set_src " "RCC: Mux %d source changed: from %u to %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , mux_id, old_src, new_src); #line 4987 "trace/trace-hw_misc.h" } else { #line 193 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_mux_set_src " "RCC: Mux %d source changed: from %u to %u" "\n", mux_id, old_src, new_src); #line 4991 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_mux_set_src(uint32_t mux_id, uint32_t old_src, uint32_t new_src) { if (true) { _nocheck__trace_stm32l4x5_rcc_mux_set_src(mux_id, old_src, new_src); } } #define TRACE_STM32L4X5_RCC_MUX_UPDATE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_MUX_UPDATE) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_mux_update(uint32_t mux_id, uint32_t src, uint64_t src_freq, uint32_t multiplier, uint32_t divider) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_MUX_UPDATE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 194 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_mux_update " "RCC: Mux %d src %d update: src_freq %" PRIu64 " multiplier %" PRIu32 " divider %" PRIu32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , mux_id, src, src_freq, multiplier, divider); #line 5018 "trace/trace-hw_misc.h" } else { #line 194 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_mux_update " "RCC: Mux %d src %d update: src_freq %" PRIu64 " multiplier %" PRIu32 " divider %" PRIu32 "\n", mux_id, src, src_freq, multiplier, divider); #line 5022 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_mux_update(uint32_t mux_id, uint32_t src, uint64_t src_freq, uint32_t multiplier, uint32_t divider) { if (true) { _nocheck__trace_stm32l4x5_rcc_mux_update(mux_id, src, src_freq, multiplier, divider); } } #define TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_pll_set_vco_multiplier(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_PLL_SET_VCO_MULTIPLIER) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 195 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_pll_set_vco_multiplier " "RCC: PLL %u: vco_multiplier changed (%u -> %u)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , pll_id, old_multiplier, new_multiplier); #line 5049 "trace/trace-hw_misc.h" } else { #line 195 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_pll_set_vco_multiplier " "RCC: PLL %u: vco_multiplier changed (%u -> %u)" "\n", pll_id, old_multiplier, new_multiplier); #line 5053 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_pll_set_vco_multiplier(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) { if (true) { _nocheck__trace_stm32l4x5_rcc_pll_set_vco_multiplier(pll_id, old_multiplier, new_multiplier); } } #define TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_PLL_CHANNEL_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 196 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_pll_channel_enable " "RCC: PLL %u, channel %u enabled" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , pll_id, channel_id); #line 5080 "trace/trace-hw_misc.h" } else { #line 196 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_pll_channel_enable " "RCC: PLL %u, channel %u enabled" "\n", pll_id, channel_id); #line 5084 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) { if (true) { _nocheck__trace_stm32l4x5_rcc_pll_channel_enable(pll_id, channel_id); } } #define TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_PLL_CHANNEL_DISABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 197 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_pll_channel_disable " "RCC: PLL %u, channel %u disabled" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , pll_id, channel_id); #line 5111 "trace/trace-hw_misc.h" } else { #line 197 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_pll_channel_disable " "RCC: PLL %u, channel %u disabled" "\n", pll_id, channel_id); #line 5115 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) { if (true) { _nocheck__trace_stm32l4x5_rcc_pll_channel_disable(pll_id, channel_id); } } #define TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_pll_set_channel_divider(uint32_t pll_id, uint32_t channel_id, uint32_t old_divider, uint32_t new_divider) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_PLL_SET_CHANNEL_DIVIDER) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 198 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_pll_set_channel_divider " "RCC: PLL %u, channel %u: divider changed (%u -> %u)" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , pll_id, channel_id, old_divider, new_divider); #line 5142 "trace/trace-hw_misc.h" } else { #line 198 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_pll_set_channel_divider " "RCC: PLL %u, channel %u: divider changed (%u -> %u)" "\n", pll_id, channel_id, old_divider, new_divider); #line 5146 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_pll_set_channel_divider(uint32_t pll_id, uint32_t channel_id, uint32_t old_divider, uint32_t new_divider) { if (true) { _nocheck__trace_stm32l4x5_rcc_pll_set_channel_divider(pll_id, channel_id, old_divider, new_divider); } } #define TRACE_STM32L4X5_RCC_PLL_UPDATE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_STM32L4X5_RCC_PLL_UPDATE) || \ false) static inline void _nocheck__trace_stm32l4x5_rcc_pll_update(uint32_t pll_id, uint32_t channel_id, uint64_t vco_freq, uint64_t old_freq, uint64_t new_freq) { if (trace_event_get_state(TRACE_STM32L4X5_RCC_PLL_UPDATE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 199 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:stm32l4x5_rcc_pll_update " "RCC: PLL %d channel %d update: vco_freq %" PRIu64 " old_freq %" PRIu64 " new_freq %" PRIu64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , pll_id, channel_id, vco_freq, old_freq, new_freq); #line 5173 "trace/trace-hw_misc.h" } else { #line 199 "../hw/misc/trace-events" qemu_log("stm32l4x5_rcc_pll_update " "RCC: PLL %d channel %d update: vco_freq %" PRIu64 " old_freq %" PRIu64 " new_freq %" PRIu64 "\n", pll_id, channel_id, vco_freq, old_freq, new_freq); #line 5177 "trace/trace-hw_misc.h" } } } static inline void trace_stm32l4x5_rcc_pll_update(uint32_t pll_id, uint32_t channel_id, uint64_t vco_freq, uint64_t old_freq, uint64_t new_freq) { if (true) { _nocheck__trace_stm32l4x5_rcc_pll_update(pll_id, channel_id, vco_freq, old_freq, new_freq); } } #define TRACE_TZ_MPC_REG_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_REG_READ) || \ false) static inline void _nocheck__trace_tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_TZ_MPC_REG_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 202 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_mpc_reg_read " "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 5204 "trace/trace-hw_misc.h" } else { #line 202 "../hw/misc/trace-events" qemu_log("tz_mpc_reg_read " "TZ MPC regs read: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 5208 "trace/trace-hw_misc.h" } } } static inline void trace_tz_mpc_reg_read(uint32_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_tz_mpc_reg_read(offset, data, size); } } #define TRACE_TZ_MPC_REG_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_REG_WRITE) || \ false) static inline void _nocheck__trace_tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_TZ_MPC_REG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 203 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_mpc_reg_write " "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 5235 "trace/trace-hw_misc.h" } else { #line 203 "../hw/misc/trace-events" qemu_log("tz_mpc_reg_write " "TZ MPC regs write: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 5239 "trace/trace-hw_misc.h" } } } static inline void trace_tz_mpc_reg_write(uint32_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_tz_mpc_reg_write(offset, data, size); } } #define TRACE_TZ_MPC_MEM_BLOCKED_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_MEM_BLOCKED_READ) || \ false) static inline void _nocheck__trace_tz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure) { if (trace_event_get_state(TRACE_TZ_MPC_MEM_BLOCKED_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 204 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_mpc_mem_blocked_read " "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, size, secure); #line 5266 "trace/trace-hw_misc.h" } else { #line 204 "../hw/misc/trace-events" qemu_log("tz_mpc_mem_blocked_read " "TZ MPC blocked read: offset 0x%" PRIx64 " size %u secure %d" "\n", addr, size, secure); #line 5270 "trace/trace-hw_misc.h" } } } static inline void trace_tz_mpc_mem_blocked_read(uint64_t addr, unsigned size, bool secure) { if (true) { _nocheck__trace_tz_mpc_mem_blocked_read(addr, size, secure); } } #define TRACE_TZ_MPC_MEM_BLOCKED_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_MEM_BLOCKED_WRITE) || \ false) static inline void _nocheck__trace_tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure) { if (trace_event_get_state(TRACE_TZ_MPC_MEM_BLOCKED_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 205 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_mpc_mem_blocked_write " "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, data, size, secure); #line 5297 "trace/trace-hw_misc.h" } else { #line 205 "../hw/misc/trace-events" qemu_log("tz_mpc_mem_blocked_write " "TZ MPC blocked write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" "\n", addr, data, size, secure); #line 5301 "trace/trace-hw_misc.h" } } } static inline void trace_tz_mpc_mem_blocked_write(uint64_t addr, uint64_t data, unsigned size, bool secure) { if (true) { _nocheck__trace_tz_mpc_mem_blocked_write(addr, data, size, secure); } } #define TRACE_TZ_MPC_TRANSLATE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_TRANSLATE) || \ false) static inline void _nocheck__trace_tz_mpc_translate(uint64_t addr, int flags, const char * idx, const char * res) { if (trace_event_get_state(TRACE_TZ_MPC_TRANSLATE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 206 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_mpc_translate " "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, flags, idx, res); #line 5328 "trace/trace-hw_misc.h" } else { #line 206 "../hw/misc/trace-events" qemu_log("tz_mpc_translate " "TZ MPC translate: addr 0x%" PRIx64 " flags 0x%x iommu_idx %s: %s" "\n", addr, flags, idx, res); #line 5332 "trace/trace-hw_misc.h" } } } static inline void trace_tz_mpc_translate(uint64_t addr, int flags, const char * idx, const char * res) { if (true) { _nocheck__trace_tz_mpc_translate(addr, flags, idx, res); } } #define TRACE_TZ_MPC_IOMMU_NOTIFY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MPC_IOMMU_NOTIFY) || \ false) static inline void _nocheck__trace_tz_mpc_iommu_notify(uint64_t addr) { if (trace_event_get_state(TRACE_TZ_MPC_IOMMU_NOTIFY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 207 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_mpc_iommu_notify " "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr); #line 5359 "trace/trace-hw_misc.h" } else { #line 207 "../hw/misc/trace-events" qemu_log("tz_mpc_iommu_notify " "TZ MPC iommu: notifying UNMAP/MAP for 0x%" PRIx64 "\n", addr); #line 5363 "trace/trace-hw_misc.h" } } } static inline void trace_tz_mpc_iommu_notify(uint64_t addr) { if (true) { _nocheck__trace_tz_mpc_iommu_notify(addr); } } #define TRACE_TZ_MSC_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_RESET) || \ false) static inline void _nocheck__trace_tz_msc_reset(void) { if (trace_event_get_state(TRACE_TZ_MSC_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 210 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_msc_reset " "TZ MSC: reset" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 5390 "trace/trace-hw_misc.h" } else { #line 210 "../hw/misc/trace-events" qemu_log("tz_msc_reset " "TZ MSC: reset" "\n"); #line 5394 "trace/trace-hw_misc.h" } } } static inline void trace_tz_msc_reset(void) { if (true) { _nocheck__trace_tz_msc_reset(); } } #define TRACE_TZ_MSC_CFG_NONSEC_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_CFG_NONSEC) || \ false) static inline void _nocheck__trace_tz_msc_cfg_nonsec(int level) { if (trace_event_get_state(TRACE_TZ_MSC_CFG_NONSEC) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 211 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_msc_cfg_nonsec " "TZ MSC: cfg_nonsec = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , level); #line 5421 "trace/trace-hw_misc.h" } else { #line 211 "../hw/misc/trace-events" qemu_log("tz_msc_cfg_nonsec " "TZ MSC: cfg_nonsec = %d" "\n", level); #line 5425 "trace/trace-hw_misc.h" } } } static inline void trace_tz_msc_cfg_nonsec(int level) { if (true) { _nocheck__trace_tz_msc_cfg_nonsec(level); } } #define TRACE_TZ_MSC_CFG_SEC_RESP_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_CFG_SEC_RESP) || \ false) static inline void _nocheck__trace_tz_msc_cfg_sec_resp(int level) { if (trace_event_get_state(TRACE_TZ_MSC_CFG_SEC_RESP) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 212 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_msc_cfg_sec_resp " "TZ MSC: cfg_sec_resp = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , level); #line 5452 "trace/trace-hw_misc.h" } else { #line 212 "../hw/misc/trace-events" qemu_log("tz_msc_cfg_sec_resp " "TZ MSC: cfg_sec_resp = %d" "\n", level); #line 5456 "trace/trace-hw_misc.h" } } } static inline void trace_tz_msc_cfg_sec_resp(int level) { if (true) { _nocheck__trace_tz_msc_cfg_sec_resp(level); } } #define TRACE_TZ_MSC_IRQ_CLEAR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_IRQ_CLEAR) || \ false) static inline void _nocheck__trace_tz_msc_irq_clear(int level) { if (trace_event_get_state(TRACE_TZ_MSC_IRQ_CLEAR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 213 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_msc_irq_clear " "TZ MSC: int_clear = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , level); #line 5483 "trace/trace-hw_misc.h" } else { #line 213 "../hw/misc/trace-events" qemu_log("tz_msc_irq_clear " "TZ MSC: int_clear = %d" "\n", level); #line 5487 "trace/trace-hw_misc.h" } } } static inline void trace_tz_msc_irq_clear(int level) { if (true) { _nocheck__trace_tz_msc_irq_clear(level); } } #define TRACE_TZ_MSC_UPDATE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_UPDATE_IRQ) || \ false) static inline void _nocheck__trace_tz_msc_update_irq(int level) { if (trace_event_get_state(TRACE_TZ_MSC_UPDATE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 214 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_msc_update_irq " "TZ MSC: setting irq line to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , level); #line 5514 "trace/trace-hw_misc.h" } else { #line 214 "../hw/misc/trace-events" qemu_log("tz_msc_update_irq " "TZ MSC: setting irq line to %d" "\n", level); #line 5518 "trace/trace-hw_misc.h" } } } static inline void trace_tz_msc_update_irq(int level) { if (true) { _nocheck__trace_tz_msc_update_irq(level); } } #define TRACE_TZ_MSC_ACCESS_BLOCKED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_MSC_ACCESS_BLOCKED) || \ false) static inline void _nocheck__trace_tz_msc_access_blocked(uint64_t offset) { if (trace_event_get_state(TRACE_TZ_MSC_ACCESS_BLOCKED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 215 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_msc_access_blocked " "TZ MSC: offset 0x%" PRIx64 " access blocked" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset); #line 5545 "trace/trace-hw_misc.h" } else { #line 215 "../hw/misc/trace-events" qemu_log("tz_msc_access_blocked " "TZ MSC: offset 0x%" PRIx64 " access blocked" "\n", offset); #line 5549 "trace/trace-hw_misc.h" } } } static inline void trace_tz_msc_access_blocked(uint64_t offset) { if (true) { _nocheck__trace_tz_msc_access_blocked(offset); } } #define TRACE_TZ_PPC_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_RESET) || \ false) static inline void _nocheck__trace_tz_ppc_reset(void) { if (trace_event_get_state(TRACE_TZ_PPC_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 218 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_ppc_reset " "TZ PPC: reset" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 5576 "trace/trace-hw_misc.h" } else { #line 218 "../hw/misc/trace-events" qemu_log("tz_ppc_reset " "TZ PPC: reset" "\n"); #line 5580 "trace/trace-hw_misc.h" } } } static inline void trace_tz_ppc_reset(void) { if (true) { _nocheck__trace_tz_ppc_reset(); } } #define TRACE_TZ_PPC_CFG_NONSEC_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_CFG_NONSEC) || \ false) static inline void _nocheck__trace_tz_ppc_cfg_nonsec(int n, int level) { if (trace_event_get_state(TRACE_TZ_PPC_CFG_NONSEC) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 219 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_ppc_cfg_nonsec " "TZ PPC: cfg_nonsec[%d] = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , n, level); #line 5607 "trace/trace-hw_misc.h" } else { #line 219 "../hw/misc/trace-events" qemu_log("tz_ppc_cfg_nonsec " "TZ PPC: cfg_nonsec[%d] = %d" "\n", n, level); #line 5611 "trace/trace-hw_misc.h" } } } static inline void trace_tz_ppc_cfg_nonsec(int n, int level) { if (true) { _nocheck__trace_tz_ppc_cfg_nonsec(n, level); } } #define TRACE_TZ_PPC_CFG_AP_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_CFG_AP) || \ false) static inline void _nocheck__trace_tz_ppc_cfg_ap(int n, int level) { if (trace_event_get_state(TRACE_TZ_PPC_CFG_AP) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 220 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_ppc_cfg_ap " "TZ PPC: cfg_ap[%d] = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , n, level); #line 5638 "trace/trace-hw_misc.h" } else { #line 220 "../hw/misc/trace-events" qemu_log("tz_ppc_cfg_ap " "TZ PPC: cfg_ap[%d] = %d" "\n", n, level); #line 5642 "trace/trace-hw_misc.h" } } } static inline void trace_tz_ppc_cfg_ap(int n, int level) { if (true) { _nocheck__trace_tz_ppc_cfg_ap(n, level); } } #define TRACE_TZ_PPC_CFG_SEC_RESP_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_CFG_SEC_RESP) || \ false) static inline void _nocheck__trace_tz_ppc_cfg_sec_resp(int level) { if (trace_event_get_state(TRACE_TZ_PPC_CFG_SEC_RESP) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 221 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_ppc_cfg_sec_resp " "TZ PPC: cfg_sec_resp = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , level); #line 5669 "trace/trace-hw_misc.h" } else { #line 221 "../hw/misc/trace-events" qemu_log("tz_ppc_cfg_sec_resp " "TZ PPC: cfg_sec_resp = %d" "\n", level); #line 5673 "trace/trace-hw_misc.h" } } } static inline void trace_tz_ppc_cfg_sec_resp(int level) { if (true) { _nocheck__trace_tz_ppc_cfg_sec_resp(level); } } #define TRACE_TZ_PPC_IRQ_ENABLE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_IRQ_ENABLE) || \ false) static inline void _nocheck__trace_tz_ppc_irq_enable(int level) { if (trace_event_get_state(TRACE_TZ_PPC_IRQ_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 222 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_ppc_irq_enable " "TZ PPC: int_enable = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , level); #line 5700 "trace/trace-hw_misc.h" } else { #line 222 "../hw/misc/trace-events" qemu_log("tz_ppc_irq_enable " "TZ PPC: int_enable = %d" "\n", level); #line 5704 "trace/trace-hw_misc.h" } } } static inline void trace_tz_ppc_irq_enable(int level) { if (true) { _nocheck__trace_tz_ppc_irq_enable(level); } } #define TRACE_TZ_PPC_IRQ_CLEAR_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_IRQ_CLEAR) || \ false) static inline void _nocheck__trace_tz_ppc_irq_clear(int level) { if (trace_event_get_state(TRACE_TZ_PPC_IRQ_CLEAR) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 223 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_ppc_irq_clear " "TZ PPC: int_clear = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , level); #line 5731 "trace/trace-hw_misc.h" } else { #line 223 "../hw/misc/trace-events" qemu_log("tz_ppc_irq_clear " "TZ PPC: int_clear = %d" "\n", level); #line 5735 "trace/trace-hw_misc.h" } } } static inline void trace_tz_ppc_irq_clear(int level) { if (true) { _nocheck__trace_tz_ppc_irq_clear(level); } } #define TRACE_TZ_PPC_UPDATE_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_UPDATE_IRQ) || \ false) static inline void _nocheck__trace_tz_ppc_update_irq(int level) { if (trace_event_get_state(TRACE_TZ_PPC_UPDATE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 224 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_ppc_update_irq " "TZ PPC: setting irq line to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , level); #line 5762 "trace/trace-hw_misc.h" } else { #line 224 "../hw/misc/trace-events" qemu_log("tz_ppc_update_irq " "TZ PPC: setting irq line to %d" "\n", level); #line 5766 "trace/trace-hw_misc.h" } } } static inline void trace_tz_ppc_update_irq(int level) { if (true) { _nocheck__trace_tz_ppc_update_irq(level); } } #define TRACE_TZ_PPC_READ_BLOCKED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_READ_BLOCKED) || \ false) static inline void _nocheck__trace_tz_ppc_read_blocked(int n, uint64_t offset, bool secure, bool user) { if (trace_event_get_state(TRACE_TZ_PPC_READ_BLOCKED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 225 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_ppc_read_blocked " "TZ PPC: port %d offset 0x%" PRIx64 " read (secure %d user %d) blocked" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , n, offset, secure, user); #line 5793 "trace/trace-hw_misc.h" } else { #line 225 "../hw/misc/trace-events" qemu_log("tz_ppc_read_blocked " "TZ PPC: port %d offset 0x%" PRIx64 " read (secure %d user %d) blocked" "\n", n, offset, secure, user); #line 5797 "trace/trace-hw_misc.h" } } } static inline void trace_tz_ppc_read_blocked(int n, uint64_t offset, bool secure, bool user) { if (true) { _nocheck__trace_tz_ppc_read_blocked(n, offset, secure, user); } } #define TRACE_TZ_PPC_WRITE_BLOCKED_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_TZ_PPC_WRITE_BLOCKED) || \ false) static inline void _nocheck__trace_tz_ppc_write_blocked(int n, uint64_t offset, bool secure, bool user) { if (trace_event_get_state(TRACE_TZ_PPC_WRITE_BLOCKED) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 226 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:tz_ppc_write_blocked " "TZ PPC: port %d offset 0x%" PRIx64 " write (secure %d user %d) blocked" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , n, offset, secure, user); #line 5824 "trace/trace-hw_misc.h" } else { #line 226 "../hw/misc/trace-events" qemu_log("tz_ppc_write_blocked " "TZ PPC: port %d offset 0x%" PRIx64 " write (secure %d user %d) blocked" "\n", n, offset, secure, user); #line 5828 "trace/trace-hw_misc.h" } } } static inline void trace_tz_ppc_write_blocked(int n, uint64_t offset, bool secure, bool user) { if (true) { _nocheck__trace_tz_ppc_write_blocked(n, offset, secure, user); } } #define TRACE_IOTKIT_SECCTL_S_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SECCTL_S_READ) || \ false) static inline void _nocheck__trace_iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_IOTKIT_SECCTL_S_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 229 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:iotkit_secctl_s_read " "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 5855 "trace/trace-hw_misc.h" } else { #line 229 "../hw/misc/trace-events" qemu_log("iotkit_secctl_s_read " "IoTKit SecCtl S regs read: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 5859 "trace/trace-hw_misc.h" } } } static inline void trace_iotkit_secctl_s_read(uint32_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_iotkit_secctl_s_read(offset, data, size); } } #define TRACE_IOTKIT_SECCTL_S_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SECCTL_S_WRITE) || \ false) static inline void _nocheck__trace_iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_IOTKIT_SECCTL_S_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 230 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:iotkit_secctl_s_write " "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 5886 "trace/trace-hw_misc.h" } else { #line 230 "../hw/misc/trace-events" qemu_log("iotkit_secctl_s_write " "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 5890 "trace/trace-hw_misc.h" } } } static inline void trace_iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_iotkit_secctl_s_write(offset, data, size); } } #define TRACE_IOTKIT_SECCTL_NS_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SECCTL_NS_READ) || \ false) static inline void _nocheck__trace_iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_IOTKIT_SECCTL_NS_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 231 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:iotkit_secctl_ns_read " "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 5917 "trace/trace-hw_misc.h" } else { #line 231 "../hw/misc/trace-events" qemu_log("iotkit_secctl_ns_read " "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 5921 "trace/trace-hw_misc.h" } } } static inline void trace_iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_iotkit_secctl_ns_read(offset, data, size); } } #define TRACE_IOTKIT_SECCTL_NS_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SECCTL_NS_WRITE) || \ false) static inline void _nocheck__trace_iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_IOTKIT_SECCTL_NS_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 232 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:iotkit_secctl_ns_write " "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 5948 "trace/trace-hw_misc.h" } else { #line 232 "../hw/misc/trace-events" qemu_log("iotkit_secctl_ns_write " "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 5952 "trace/trace-hw_misc.h" } } } static inline void trace_iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_iotkit_secctl_ns_write(offset, data, size); } } #define TRACE_IMX6_ANALOG_GET_PERIPH_CLK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_GET_PERIPH_CLK) || \ false) static inline void _nocheck__trace_imx6_analog_get_periph_clk(uint32_t freq) { if (trace_event_get_state(TRACE_IMX6_ANALOG_GET_PERIPH_CLK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 235 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_analog_get_periph_clk " "freq = %u Hz" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , freq); #line 5979 "trace/trace-hw_misc.h" } else { #line 235 "../hw/misc/trace-events" qemu_log("imx6_analog_get_periph_clk " "freq = %u Hz" "\n", freq); #line 5983 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_analog_get_periph_clk(uint32_t freq) { if (true) { _nocheck__trace_imx6_analog_get_periph_clk(freq); } } #define TRACE_IMX6_ANALOG_GET_PLL2_CLK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_GET_PLL2_CLK) || \ false) static inline void _nocheck__trace_imx6_analog_get_pll2_clk(uint32_t freq) { if (trace_event_get_state(TRACE_IMX6_ANALOG_GET_PLL2_CLK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 236 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_analog_get_pll2_clk " "freq = %u Hz" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , freq); #line 6010 "trace/trace-hw_misc.h" } else { #line 236 "../hw/misc/trace-events" qemu_log("imx6_analog_get_pll2_clk " "freq = %u Hz" "\n", freq); #line 6014 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_analog_get_pll2_clk(uint32_t freq) { if (true) { _nocheck__trace_imx6_analog_get_pll2_clk(freq); } } #define TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK) || \ false) static inline void _nocheck__trace_imx6_analog_get_pll2_pfd0_clk(uint32_t freq) { if (trace_event_get_state(TRACE_IMX6_ANALOG_GET_PLL2_PFD0_CLK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 237 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_analog_get_pll2_pfd0_clk " "freq = %u Hz" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , freq); #line 6041 "trace/trace-hw_misc.h" } else { #line 237 "../hw/misc/trace-events" qemu_log("imx6_analog_get_pll2_pfd0_clk " "freq = %u Hz" "\n", freq); #line 6045 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_analog_get_pll2_pfd0_clk(uint32_t freq) { if (true) { _nocheck__trace_imx6_analog_get_pll2_pfd0_clk(freq); } } #define TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK) || \ false) static inline void _nocheck__trace_imx6_analog_get_pll2_pfd2_clk(uint32_t freq) { if (trace_event_get_state(TRACE_IMX6_ANALOG_GET_PLL2_PFD2_CLK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 238 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_analog_get_pll2_pfd2_clk " "freq = %u Hz" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , freq); #line 6072 "trace/trace-hw_misc.h" } else { #line 238 "../hw/misc/trace-events" qemu_log("imx6_analog_get_pll2_pfd2_clk " "freq = %u Hz" "\n", freq); #line 6076 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_analog_get_pll2_pfd2_clk(uint32_t freq) { if (true) { _nocheck__trace_imx6_analog_get_pll2_pfd2_clk(freq); } } #define TRACE_IMX6_ANALOG_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_READ) || \ false) static inline void _nocheck__trace_imx6_analog_read(const char * reg, uint32_t value) { if (trace_event_get_state(TRACE_IMX6_ANALOG_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 239 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_analog_read " "reg[%s] => 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, value); #line 6103 "trace/trace-hw_misc.h" } else { #line 239 "../hw/misc/trace-events" qemu_log("imx6_analog_read " "reg[%s] => 0x%" PRIx32 "\n", reg, value); #line 6107 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_analog_read(const char * reg, uint32_t value) { if (true) { _nocheck__trace_imx6_analog_read(reg, value); } } #define TRACE_IMX6_ANALOG_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_ANALOG_WRITE) || \ false) static inline void _nocheck__trace_imx6_analog_write(const char * reg, uint32_t value) { if (trace_event_get_state(TRACE_IMX6_ANALOG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 240 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_analog_write " "reg[%s] <= 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, value); #line 6134 "trace/trace-hw_misc.h" } else { #line 240 "../hw/misc/trace-events" qemu_log("imx6_analog_write " "reg[%s] <= 0x%" PRIx32 "\n", reg, value); #line 6138 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_analog_write(const char * reg, uint32_t value) { if (true) { _nocheck__trace_imx6_analog_write(reg, value); } } #define TRACE_IMX6_CCM_GET_AHB_CLK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_GET_AHB_CLK) || \ false) static inline void _nocheck__trace_imx6_ccm_get_ahb_clk(uint32_t freq) { if (trace_event_get_state(TRACE_IMX6_CCM_GET_AHB_CLK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 241 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_ccm_get_ahb_clk " "freq = %u Hz" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , freq); #line 6165 "trace/trace-hw_misc.h" } else { #line 241 "../hw/misc/trace-events" qemu_log("imx6_ccm_get_ahb_clk " "freq = %u Hz" "\n", freq); #line 6169 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_ccm_get_ahb_clk(uint32_t freq) { if (true) { _nocheck__trace_imx6_ccm_get_ahb_clk(freq); } } #define TRACE_IMX6_CCM_GET_IPG_CLK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_GET_IPG_CLK) || \ false) static inline void _nocheck__trace_imx6_ccm_get_ipg_clk(uint32_t freq) { if (trace_event_get_state(TRACE_IMX6_CCM_GET_IPG_CLK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 242 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_ccm_get_ipg_clk " "freq = %u Hz" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , freq); #line 6196 "trace/trace-hw_misc.h" } else { #line 242 "../hw/misc/trace-events" qemu_log("imx6_ccm_get_ipg_clk " "freq = %u Hz" "\n", freq); #line 6200 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_ccm_get_ipg_clk(uint32_t freq) { if (true) { _nocheck__trace_imx6_ccm_get_ipg_clk(freq); } } #define TRACE_IMX6_CCM_GET_PER_CLK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_GET_PER_CLK) || \ false) static inline void _nocheck__trace_imx6_ccm_get_per_clk(uint32_t freq) { if (trace_event_get_state(TRACE_IMX6_CCM_GET_PER_CLK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 243 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_ccm_get_per_clk " "freq = %u Hz" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , freq); #line 6227 "trace/trace-hw_misc.h" } else { #line 243 "../hw/misc/trace-events" qemu_log("imx6_ccm_get_per_clk " "freq = %u Hz" "\n", freq); #line 6231 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_ccm_get_per_clk(uint32_t freq) { if (true) { _nocheck__trace_imx6_ccm_get_per_clk(freq); } } #define TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY) || \ false) static inline void _nocheck__trace_imx6_ccm_get_clock_frequency(unsigned clock, uint32_t freq) { if (trace_event_get_state(TRACE_IMX6_CCM_GET_CLOCK_FREQUENCY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 244 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_ccm_get_clock_frequency " "(Clock = %d) = %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , clock, freq); #line 6258 "trace/trace-hw_misc.h" } else { #line 244 "../hw/misc/trace-events" qemu_log("imx6_ccm_get_clock_frequency " "(Clock = %d) = %u" "\n", clock, freq); #line 6262 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_ccm_get_clock_frequency(unsigned clock, uint32_t freq) { if (true) { _nocheck__trace_imx6_ccm_get_clock_frequency(clock, freq); } } #define TRACE_IMX6_CCM_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_READ) || \ false) static inline void _nocheck__trace_imx6_ccm_read(const char * reg, uint32_t value) { if (trace_event_get_state(TRACE_IMX6_CCM_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 245 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_ccm_read " "reg[%s] => 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, value); #line 6289 "trace/trace-hw_misc.h" } else { #line 245 "../hw/misc/trace-events" qemu_log("imx6_ccm_read " "reg[%s] => 0x%" PRIx32 "\n", reg, value); #line 6293 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_ccm_read(const char * reg, uint32_t value) { if (true) { _nocheck__trace_imx6_ccm_read(reg, value); } } #define TRACE_IMX6_CCM_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_RESET) || \ false) static inline void _nocheck__trace_imx6_ccm_reset(void) { if (trace_event_get_state(TRACE_IMX6_CCM_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 246 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_ccm_reset " "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 6320 "trace/trace-hw_misc.h" } else { #line 246 "../hw/misc/trace-events" qemu_log("imx6_ccm_reset " "" "\n"); #line 6324 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_ccm_reset(void) { if (true) { _nocheck__trace_imx6_ccm_reset(); } } #define TRACE_IMX6_CCM_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX6_CCM_WRITE) || \ false) static inline void _nocheck__trace_imx6_ccm_write(const char * reg, uint32_t value) { if (trace_event_get_state(TRACE_IMX6_CCM_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 247 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx6_ccm_write " "reg[%s] <= 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, value); #line 6351 "trace/trace-hw_misc.h" } else { #line 247 "../hw/misc/trace-events" qemu_log("imx6_ccm_write " "reg[%s] <= 0x%" PRIx32 "\n", reg, value); #line 6355 "trace/trace-hw_misc.h" } } } static inline void trace_imx6_ccm_write(const char * reg, uint32_t value) { if (true) { _nocheck__trace_imx6_ccm_write(reg, value); } } #define TRACE_CCM_ENTRY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_CCM_ENTRY) || \ false) static inline void _nocheck__trace_ccm_entry(void) { if (trace_event_get_state(TRACE_CCM_ENTRY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 250 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ccm_entry " "" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 6382 "trace/trace-hw_misc.h" } else { #line 250 "../hw/misc/trace-events" qemu_log("ccm_entry " "" "\n"); #line 6386 "trace/trace-hw_misc.h" } } } static inline void trace_ccm_entry(void) { if (true) { _nocheck__trace_ccm_entry(); } } #define TRACE_CCM_FREQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_CCM_FREQ) || \ false) static inline void _nocheck__trace_ccm_freq(uint32_t freq) { if (trace_event_get_state(TRACE_CCM_FREQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 251 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ccm_freq " "freq = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , freq); #line 6413 "trace/trace-hw_misc.h" } else { #line 251 "../hw/misc/trace-events" qemu_log("ccm_freq " "freq = %d" "\n", freq); #line 6417 "trace/trace-hw_misc.h" } } } static inline void trace_ccm_freq(uint32_t freq) { if (true) { _nocheck__trace_ccm_freq(freq); } } #define TRACE_CCM_CLOCK_FREQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_CCM_CLOCK_FREQ) || \ false) static inline void _nocheck__trace_ccm_clock_freq(uint32_t clock, uint32_t freq) { if (trace_event_get_state(TRACE_CCM_CLOCK_FREQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 252 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ccm_clock_freq " "(Clock = %d) = %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , clock, freq); #line 6444 "trace/trace-hw_misc.h" } else { #line 252 "../hw/misc/trace-events" qemu_log("ccm_clock_freq " "(Clock = %d) = %d" "\n", clock, freq); #line 6448 "trace/trace-hw_misc.h" } } } static inline void trace_ccm_clock_freq(uint32_t clock, uint32_t freq) { if (true) { _nocheck__trace_ccm_clock_freq(clock, freq); } } #define TRACE_CCM_READ_REG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_CCM_READ_REG) || \ false) static inline void _nocheck__trace_ccm_read_reg(const char * reg_name, uint32_t value) { if (trace_event_get_state(TRACE_CCM_READ_REG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 253 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ccm_read_reg " "reg[%s] <= 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg_name, value); #line 6475 "trace/trace-hw_misc.h" } else { #line 253 "../hw/misc/trace-events" qemu_log("ccm_read_reg " "reg[%s] <= 0x%" PRIx32 "\n", reg_name, value); #line 6479 "trace/trace-hw_misc.h" } } } static inline void trace_ccm_read_reg(const char * reg_name, uint32_t value) { if (true) { _nocheck__trace_ccm_read_reg(reg_name, value); } } #define TRACE_CCM_WRITE_REG_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_CCM_WRITE_REG) || \ false) static inline void _nocheck__trace_ccm_write_reg(const char * reg_name, uint32_t value) { if (trace_event_get_state(TRACE_CCM_WRITE_REG) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 254 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:ccm_write_reg " "reg[%s] => 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg_name, value); #line 6506 "trace/trace-hw_misc.h" } else { #line 254 "../hw/misc/trace-events" qemu_log("ccm_write_reg " "reg[%s] => 0x%" PRIx32 "\n", reg_name, value); #line 6510 "trace/trace-hw_misc.h" } } } static inline void trace_ccm_write_reg(const char * reg_name, uint32_t value) { if (true) { _nocheck__trace_ccm_write_reg(reg_name, value); } } #define TRACE_IMX7_SRC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX7_SRC_READ) || \ false) static inline void _nocheck__trace_imx7_src_read(const char * reg_name, uint32_t value) { if (trace_event_get_state(TRACE_IMX7_SRC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 257 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx7_src_read " "reg[%s] => 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg_name, value); #line 6537 "trace/trace-hw_misc.h" } else { #line 257 "../hw/misc/trace-events" qemu_log("imx7_src_read " "reg[%s] => 0x%" PRIx32 "\n", reg_name, value); #line 6541 "trace/trace-hw_misc.h" } } } static inline void trace_imx7_src_read(const char * reg_name, uint32_t value) { if (true) { _nocheck__trace_imx7_src_read(reg_name, value); } } #define TRACE_IMX7_SRC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IMX7_SRC_WRITE) || \ false) static inline void _nocheck__trace_imx7_src_write(const char * reg_name, uint32_t value) { if (trace_event_get_state(TRACE_IMX7_SRC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 258 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:imx7_src_write " "reg[%s] <= 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg_name, value); #line 6568 "trace/trace-hw_misc.h" } else { #line 258 "../hw/misc/trace-events" qemu_log("imx7_src_write " "reg[%s] <= 0x%" PRIx32 "\n", reg_name, value); #line 6572 "trace/trace-hw_misc.h" } } } static inline void trace_imx7_src_write(const char * reg_name, uint32_t value) { if (true) { _nocheck__trace_imx7_src_write(reg_name, value); } } #define TRACE_IOTKIT_SYSINFO_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SYSINFO_READ) || \ false) static inline void _nocheck__trace_iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_IOTKIT_SYSINFO_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 261 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:iotkit_sysinfo_read " "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 6599 "trace/trace-hw_misc.h" } else { #line 261 "../hw/misc/trace-events" qemu_log("iotkit_sysinfo_read " "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 6603 "trace/trace-hw_misc.h" } } } static inline void trace_iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_iotkit_sysinfo_read(offset, data, size); } } #define TRACE_IOTKIT_SYSINFO_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SYSINFO_WRITE) || \ false) static inline void _nocheck__trace_iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_IOTKIT_SYSINFO_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 262 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:iotkit_sysinfo_write " "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 6630 "trace/trace-hw_misc.h" } else { #line 262 "../hw/misc/trace-events" qemu_log("iotkit_sysinfo_write " "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 6634 "trace/trace-hw_misc.h" } } } static inline void trace_iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_iotkit_sysinfo_write(offset, data, size); } } #define TRACE_IOTKIT_SYSCTL_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SYSCTL_READ) || \ false) static inline void _nocheck__trace_iotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_IOTKIT_SYSCTL_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 265 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:iotkit_sysctl_read " "IoTKit SysCtl read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 6661 "trace/trace-hw_misc.h" } else { #line 265 "../hw/misc/trace-events" qemu_log("iotkit_sysctl_read " "IoTKit SysCtl read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 6665 "trace/trace-hw_misc.h" } } } static inline void trace_iotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_iotkit_sysctl_read(offset, data, size); } } #define TRACE_IOTKIT_SYSCTL_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SYSCTL_WRITE) || \ false) static inline void _nocheck__trace_iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_IOTKIT_SYSCTL_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 266 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:iotkit_sysctl_write " "IoTKit SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 6692 "trace/trace-hw_misc.h" } else { #line 266 "../hw/misc/trace-events" qemu_log("iotkit_sysctl_write " "IoTKit SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 6696 "trace/trace-hw_misc.h" } } } static inline void trace_iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_iotkit_sysctl_write(offset, data, size); } } #define TRACE_IOTKIT_SYSCTL_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOTKIT_SYSCTL_RESET) || \ false) static inline void _nocheck__trace_iotkit_sysctl_reset(void) { if (trace_event_get_state(TRACE_IOTKIT_SYSCTL_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 267 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:iotkit_sysctl_reset " "IoTKit SysCtl: reset" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 6723 "trace/trace-hw_misc.h" } else { #line 267 "../hw/misc/trace-events" qemu_log("iotkit_sysctl_reset " "IoTKit SysCtl: reset" "\n"); #line 6727 "trace/trace-hw_misc.h" } } } static inline void trace_iotkit_sysctl_reset(void) { if (true) { _nocheck__trace_iotkit_sysctl_reset(); } } #define TRACE_ARMSSE_CPU_PWRCTRL_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_CPU_PWRCTRL_READ) || \ false) static inline void _nocheck__trace_armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ARMSSE_CPU_PWRCTRL_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 270 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:armsse_cpu_pwrctrl_read " "SSE-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 6754 "trace/trace-hw_misc.h" } else { #line 270 "../hw/misc/trace-events" qemu_log("armsse_cpu_pwrctrl_read " "SSE-300 CPU_PWRCTRL read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 6758 "trace/trace-hw_misc.h" } } } static inline void trace_armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_armsse_cpu_pwrctrl_read(offset, data, size); } } #define TRACE_ARMSSE_CPU_PWRCTRL_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_CPU_PWRCTRL_WRITE) || \ false) static inline void _nocheck__trace_armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ARMSSE_CPU_PWRCTRL_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 271 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:armsse_cpu_pwrctrl_write " "SSE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 6785 "trace/trace-hw_misc.h" } else { #line 271 "../hw/misc/trace-events" qemu_log("armsse_cpu_pwrctrl_write " "SSE-300 CPU_PWRCTRL write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 6789 "trace/trace-hw_misc.h" } } } static inline void trace_armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_armsse_cpu_pwrctrl_write(offset, data, size); } } #define TRACE_ARMSSE_CPUID_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_CPUID_READ) || \ false) static inline void _nocheck__trace_armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ARMSSE_CPUID_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 274 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:armsse_cpuid_read " "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 6816 "trace/trace-hw_misc.h" } else { #line 274 "../hw/misc/trace-events" qemu_log("armsse_cpuid_read " "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 6820 "trace/trace-hw_misc.h" } } } static inline void trace_armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_armsse_cpuid_read(offset, data, size); } } #define TRACE_ARMSSE_CPUID_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_CPUID_WRITE) || \ false) static inline void _nocheck__trace_armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ARMSSE_CPUID_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 275 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:armsse_cpuid_write " "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 6847 "trace/trace-hw_misc.h" } else { #line 275 "../hw/misc/trace-events" qemu_log("armsse_cpuid_write " "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 6851 "trace/trace-hw_misc.h" } } } static inline void trace_armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_armsse_cpuid_write(offset, data, size); } } #define TRACE_ARMSSE_MHU_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_MHU_READ) || \ false) static inline void _nocheck__trace_armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ARMSSE_MHU_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 278 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:armsse_mhu_read " "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 6878 "trace/trace-hw_misc.h" } else { #line 278 "../hw/misc/trace-events" qemu_log("armsse_mhu_read " "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 6882 "trace/trace-hw_misc.h" } } } static inline void trace_armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_armsse_mhu_read(offset, data, size); } } #define TRACE_ARMSSE_MHU_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ARMSSE_MHU_WRITE) || \ false) static inline void _nocheck__trace_armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) { if (trace_event_get_state(TRACE_ARMSSE_MHU_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 279 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:armsse_mhu_write " "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data, size); #line 6909 "trace/trace-hw_misc.h" } else { #line 279 "../hw/misc/trace-events" qemu_log("armsse_mhu_write " "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" "\n", offset, data, size); #line 6913 "trace/trace-hw_misc.h" } } } static inline void trace_armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) { if (true) { _nocheck__trace_armsse_mhu_write(offset, data, size); } } #define TRACE_ASPEED_XDMA_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_XDMA_WRITE) || \ false) static inline void _nocheck__trace_aspeed_xdma_write(uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_ASPEED_XDMA_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 282 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_xdma_write " "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data); #line 6940 "trace/trace-hw_misc.h" } else { #line 282 "../hw/misc/trace-events" qemu_log("aspeed_xdma_write " "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data); #line 6944 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_xdma_write(uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_aspeed_xdma_write(offset, data); } } #define TRACE_ASPEED_I3C_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I3C_READ) || \ false) static inline void _nocheck__trace_aspeed_i3c_read(uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_ASPEED_I3C_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 285 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_i3c_read " "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data); #line 6971 "trace/trace-hw_misc.h" } else { #line 285 "../hw/misc/trace-events" qemu_log("aspeed_i3c_read " "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data); #line 6975 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_i3c_read(uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_aspeed_i3c_read(offset, data); } } #define TRACE_ASPEED_I3C_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I3C_WRITE) || \ false) static inline void _nocheck__trace_aspeed_i3c_write(uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_ASPEED_I3C_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 286 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_i3c_write " "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data); #line 7002 "trace/trace-hw_misc.h" } else { #line 286 "../hw/misc/trace-events" qemu_log("aspeed_i3c_write " "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data); #line 7006 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_i3c_write(uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_aspeed_i3c_write(offset, data); } } #define TRACE_ASPEED_I3C_DEVICE_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I3C_DEVICE_READ) || \ false) static inline void _nocheck__trace_aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_ASPEED_I3C_DEVICE_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 287 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_i3c_device_read " "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , deviceid, offset, data); #line 7033 "trace/trace-hw_misc.h" } else { #line 287 "../hw/misc/trace-events" qemu_log("aspeed_i3c_device_read " "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", deviceid, offset, data); #line 7037 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_aspeed_i3c_device_read(deviceid, offset, data); } } #define TRACE_ASPEED_I3C_DEVICE_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_I3C_DEVICE_WRITE) || \ false) static inline void _nocheck__trace_aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_ASPEED_I3C_DEVICE_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 288 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_i3c_device_write " "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , deviceid, offset, data); #line 7064 "trace/trace-hw_misc.h" } else { #line 288 "../hw/misc/trace-events" qemu_log("aspeed_i3c_device_write " "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", deviceid, offset, data); #line 7068 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_aspeed_i3c_device_write(deviceid, offset, data); } } #define TRACE_ASPEED_SDMC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SDMC_WRITE) || \ false) static inline void _nocheck__trace_aspeed_sdmc_write(uint64_t reg, uint64_t data) { if (trace_event_get_state(TRACE_ASPEED_SDMC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 291 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_sdmc_write " "reg @0x%" PRIx64 " data: 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, data); #line 7095 "trace/trace-hw_misc.h" } else { #line 291 "../hw/misc/trace-events" qemu_log("aspeed_sdmc_write " "reg @0x%" PRIx64 " data: 0x%" PRIx64 "\n", reg, data); #line 7099 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_sdmc_write(uint64_t reg, uint64_t data) { if (true) { _nocheck__trace_aspeed_sdmc_write(reg, data); } } #define TRACE_ASPEED_SDMC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SDMC_READ) || \ false) static inline void _nocheck__trace_aspeed_sdmc_read(uint64_t reg, uint64_t data) { if (trace_event_get_state(TRACE_ASPEED_SDMC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 292 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_sdmc_read " "reg @0x%" PRIx64 " data: 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, data); #line 7126 "trace/trace-hw_misc.h" } else { #line 292 "../hw/misc/trace-events" qemu_log("aspeed_sdmc_read " "reg @0x%" PRIx64 " data: 0x%" PRIx64 "\n", reg, data); #line 7130 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_sdmc_read(uint64_t reg, uint64_t data) { if (true) { _nocheck__trace_aspeed_sdmc_read(reg, data); } } #define TRACE_ASPEED_PECI_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_PECI_READ) || \ false) static inline void _nocheck__trace_aspeed_peci_read(uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_ASPEED_PECI_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 295 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_peci_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data); #line 7157 "trace/trace-hw_misc.h" } else { #line 295 "../hw/misc/trace-events" qemu_log("aspeed_peci_read " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data); #line 7161 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_peci_read(uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_aspeed_peci_read(offset, data); } } #define TRACE_ASPEED_PECI_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_PECI_WRITE) || \ false) static inline void _nocheck__trace_aspeed_peci_write(uint64_t offset, uint64_t data) { if (trace_event_get_state(TRACE_ASPEED_PECI_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 296 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_peci_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, data); #line 7188 "trace/trace-hw_misc.h" } else { #line 296 "../hw/misc/trace-events" qemu_log("aspeed_peci_write " "offset 0x%" PRIx64 " data 0x%" PRIx64 "\n", offset, data); #line 7192 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_peci_write(uint64_t offset, uint64_t data) { if (true) { _nocheck__trace_aspeed_peci_write(offset, data); } } #define TRACE_ASPEED_PECI_RAISE_INTERRUPT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_PECI_RAISE_INTERRUPT) || \ false) static inline void _nocheck__trace_aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) { if (trace_event_get_state(TRACE_ASPEED_PECI_RAISE_INTERRUPT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 297 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_peci_raise_interrupt " "ctrl 0x%" PRIx32 " status 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , ctrl, status); #line 7219 "trace/trace-hw_misc.h" } else { #line 297 "../hw/misc/trace-events" qemu_log("aspeed_peci_raise_interrupt " "ctrl 0x%" PRIx32 " status 0x%" PRIx32 "\n", ctrl, status); #line 7223 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) { if (true) { _nocheck__trace_aspeed_peci_raise_interrupt(ctrl, status); } } #define TRACE_BCM2835_MBOX_PROPERTY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_BCM2835_MBOX_PROPERTY) || \ false) static inline void _nocheck__trace_bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) { if (trace_event_get_state(TRACE_BCM2835_MBOX_PROPERTY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 300 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:bcm2835_mbox_property " "mbox property tag:0x%08x in_sz:%u out_sz:%zu" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , tag, bufsize, resplen); #line 7250 "trace/trace-hw_misc.h" } else { #line 300 "../hw/misc/trace-events" qemu_log("bcm2835_mbox_property " "mbox property tag:0x%08x in_sz:%u out_sz:%zu" "\n", tag, bufsize, resplen); #line 7254 "trace/trace-hw_misc.h" } } } static inline void trace_bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) { if (true) { _nocheck__trace_bcm2835_mbox_property(tag, bufsize, resplen); } } #define TRACE_BCM2835_MBOX_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_BCM2835_MBOX_WRITE) || \ false) static inline void _nocheck__trace_bcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value) { if (trace_event_get_state(TRACE_BCM2835_MBOX_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 303 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:bcm2835_mbox_write " "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, value); #line 7281 "trace/trace-hw_misc.h" } else { #line 303 "../hw/misc/trace-events" qemu_log("bcm2835_mbox_write " "mbox write sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 "\n", size, addr, value); #line 7285 "trace/trace-hw_misc.h" } } } static inline void trace_bcm2835_mbox_write(unsigned int size, uint64_t addr, uint64_t value) { if (true) { _nocheck__trace_bcm2835_mbox_write(size, addr, value); } } #define TRACE_BCM2835_MBOX_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_BCM2835_MBOX_READ) || \ false) static inline void _nocheck__trace_bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) { if (trace_event_get_state(TRACE_BCM2835_MBOX_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 304 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:bcm2835_mbox_read " "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , size, addr, value); #line 7312 "trace/trace-hw_misc.h" } else { #line 304 "../hw/misc/trace-events" qemu_log("bcm2835_mbox_read " "mbox read sz:%u addr:0x%"PRIx64" data:0x%"PRIx64 "\n", size, addr, value); #line 7316 "trace/trace-hw_misc.h" } } } static inline void trace_bcm2835_mbox_read(unsigned int size, uint64_t addr, uint64_t value) { if (true) { _nocheck__trace_bcm2835_mbox_read(size, addr, value); } } #define TRACE_BCM2835_MBOX_IRQ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_BCM2835_MBOX_IRQ) || \ false) static inline void _nocheck__trace_bcm2835_mbox_irq(unsigned level) { if (trace_event_get_state(TRACE_BCM2835_MBOX_IRQ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 305 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:bcm2835_mbox_irq " "mbox irq:ARM level:%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , level); #line 7343 "trace/trace-hw_misc.h" } else { #line 305 "../hw/misc/trace-events" qemu_log("bcm2835_mbox_irq " "mbox irq:ARM level:%u" "\n", level); #line 7347 "trace/trace-hw_misc.h" } } } static inline void trace_bcm2835_mbox_irq(unsigned level) { if (true) { _nocheck__trace_bcm2835_mbox_irq(level); } } #define TRACE_VIA1_RTC_UPDATE_DATA_OUT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_UPDATE_DATA_OUT) || \ false) static inline void _nocheck__trace_via1_rtc_update_data_out(int count, int value) { if (trace_event_get_state(TRACE_VIA1_RTC_UPDATE_DATA_OUT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 308 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_update_data_out " "count=%d value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , count, value); #line 7374 "trace/trace-hw_misc.h" } else { #line 308 "../hw/misc/trace-events" qemu_log("via1_rtc_update_data_out " "count=%d value=0x%02x" "\n", count, value); #line 7378 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_update_data_out(int count, int value) { if (true) { _nocheck__trace_via1_rtc_update_data_out(count, value); } } #define TRACE_VIA1_RTC_UPDATE_DATA_IN_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_UPDATE_DATA_IN) || \ false) static inline void _nocheck__trace_via1_rtc_update_data_in(int count, int value) { if (trace_event_get_state(TRACE_VIA1_RTC_UPDATE_DATA_IN) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 309 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_update_data_in " "count=%d value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , count, value); #line 7405 "trace/trace-hw_misc.h" } else { #line 309 "../hw/misc/trace-events" qemu_log("via1_rtc_update_data_in " "count=%d value=0x%02x" "\n", count, value); #line 7409 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_update_data_in(int count, int value) { if (true) { _nocheck__trace_via1_rtc_update_data_in(count, value); } } #define TRACE_VIA1_RTC_INTERNAL_STATUS_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_STATUS) || \ false) static inline void _nocheck__trace_via1_rtc_internal_status(int cmd, int alt, int value) { if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_STATUS) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 310 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_internal_status " "cmd=0x%02x alt=0x%02x value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cmd, alt, value); #line 7436 "trace/trace-hw_misc.h" } else { #line 310 "../hw/misc/trace-events" qemu_log("via1_rtc_internal_status " "cmd=0x%02x alt=0x%02x value=0x%02x" "\n", cmd, alt, value); #line 7440 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_internal_status(int cmd, int alt, int value) { if (true) { _nocheck__trace_via1_rtc_internal_status(cmd, alt, value); } } #define TRACE_VIA1_RTC_INTERNAL_CMD_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_CMD) || \ false) static inline void _nocheck__trace_via1_rtc_internal_cmd(int cmd) { if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_CMD) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 311 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_internal_cmd " "cmd=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cmd); #line 7467 "trace/trace-hw_misc.h" } else { #line 311 "../hw/misc/trace-events" qemu_log("via1_rtc_internal_cmd " "cmd=0x%02x" "\n", cmd); #line 7471 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_internal_cmd(int cmd) { if (true) { _nocheck__trace_via1_rtc_internal_cmd(cmd); } } #define TRACE_VIA1_RTC_CMD_INVALID_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_INVALID) || \ false) static inline void _nocheck__trace_via1_rtc_cmd_invalid(int value) { if (trace_event_get_state(TRACE_VIA1_RTC_CMD_INVALID) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 312 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_cmd_invalid " "value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , value); #line 7498 "trace/trace-hw_misc.h" } else { #line 312 "../hw/misc/trace-events" qemu_log("via1_rtc_cmd_invalid " "value=0x%02x" "\n", value); #line 7502 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_cmd_invalid(int value) { if (true) { _nocheck__trace_via1_rtc_cmd_invalid(value); } } #define TRACE_VIA1_RTC_INTERNAL_TIME_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_TIME) || \ false) static inline void _nocheck__trace_via1_rtc_internal_time(uint32_t time) { if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_TIME) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 313 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_internal_time " "time=0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , time); #line 7529 "trace/trace-hw_misc.h" } else { #line 313 "../hw/misc/trace-events" qemu_log("via1_rtc_internal_time " "time=0x%08x" "\n", time); #line 7533 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_internal_time(uint32_t time) { if (true) { _nocheck__trace_via1_rtc_internal_time(time); } } #define TRACE_VIA1_RTC_INTERNAL_SET_CMD_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_SET_CMD) || \ false) static inline void _nocheck__trace_via1_rtc_internal_set_cmd(int cmd) { if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_SET_CMD) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 314 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_internal_set_cmd " "cmd=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cmd); #line 7560 "trace/trace-hw_misc.h" } else { #line 314 "../hw/misc/trace-events" qemu_log("via1_rtc_internal_set_cmd " "cmd=0x%02x" "\n", cmd); #line 7564 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_internal_set_cmd(int cmd) { if (true) { _nocheck__trace_via1_rtc_internal_set_cmd(cmd); } } #define TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD) || \ false) static inline void _nocheck__trace_via1_rtc_internal_ignore_cmd(int cmd) { if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_IGNORE_CMD) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 315 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_internal_ignore_cmd " "cmd=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , cmd); #line 7591 "trace/trace-hw_misc.h" } else { #line 315 "../hw/misc/trace-events" qemu_log("via1_rtc_internal_ignore_cmd " "cmd=0x%02x" "\n", cmd); #line 7595 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_internal_ignore_cmd(int cmd) { if (true) { _nocheck__trace_via1_rtc_internal_ignore_cmd(cmd); } } #define TRACE_VIA1_RTC_INTERNAL_SET_ALT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_INTERNAL_SET_ALT) || \ false) static inline void _nocheck__trace_via1_rtc_internal_set_alt(int alt, int sector, int offset) { if (trace_event_get_state(TRACE_VIA1_RTC_INTERNAL_SET_ALT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 316 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_internal_set_alt " "alt=0x%02x sector=%u offset=%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , alt, sector, offset); #line 7622 "trace/trace-hw_misc.h" } else { #line 316 "../hw/misc/trace-events" qemu_log("via1_rtc_internal_set_alt " "alt=0x%02x sector=%u offset=%u" "\n", alt, sector, offset); #line 7626 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_internal_set_alt(int alt, int sector, int offset) { if (true) { _nocheck__trace_via1_rtc_internal_set_alt(alt, sector, offset); } } #define TRACE_VIA1_RTC_CMD_SECONDS_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_SECONDS_READ) || \ false) static inline void _nocheck__trace_via1_rtc_cmd_seconds_read(int reg, int value) { if (trace_event_get_state(TRACE_VIA1_RTC_CMD_SECONDS_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 317 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_cmd_seconds_read " "reg=%d value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, value); #line 7653 "trace/trace-hw_misc.h" } else { #line 317 "../hw/misc/trace-events" qemu_log("via1_rtc_cmd_seconds_read " "reg=%d value=0x%02x" "\n", reg, value); #line 7657 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_cmd_seconds_read(int reg, int value) { if (true) { _nocheck__trace_via1_rtc_cmd_seconds_read(reg, value); } } #define TRACE_VIA1_RTC_CMD_SECONDS_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_SECONDS_WRITE) || \ false) static inline void _nocheck__trace_via1_rtc_cmd_seconds_write(int reg, int value) { if (trace_event_get_state(TRACE_VIA1_RTC_CMD_SECONDS_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 318 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_cmd_seconds_write " "reg=%d value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, value); #line 7684 "trace/trace-hw_misc.h" } else { #line 318 "../hw/misc/trace-events" qemu_log("via1_rtc_cmd_seconds_write " "reg=%d value=0x%02x" "\n", reg, value); #line 7688 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_cmd_seconds_write(int reg, int value) { if (true) { _nocheck__trace_via1_rtc_cmd_seconds_write(reg, value); } } #define TRACE_VIA1_RTC_CMD_TEST_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_TEST_WRITE) || \ false) static inline void _nocheck__trace_via1_rtc_cmd_test_write(int value) { if (trace_event_get_state(TRACE_VIA1_RTC_CMD_TEST_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 319 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_cmd_test_write " "value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , value); #line 7715 "trace/trace-hw_misc.h" } else { #line 319 "../hw/misc/trace-events" qemu_log("via1_rtc_cmd_test_write " "value=0x%02x" "\n", value); #line 7719 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_cmd_test_write(int value) { if (true) { _nocheck__trace_via1_rtc_cmd_test_write(value); } } #define TRACE_VIA1_RTC_CMD_WPROTECT_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_WPROTECT_WRITE) || \ false) static inline void _nocheck__trace_via1_rtc_cmd_wprotect_write(int value) { if (trace_event_get_state(TRACE_VIA1_RTC_CMD_WPROTECT_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 320 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_cmd_wprotect_write " "value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , value); #line 7746 "trace/trace-hw_misc.h" } else { #line 320 "../hw/misc/trace-events" qemu_log("via1_rtc_cmd_wprotect_write " "value=0x%02x" "\n", value); #line 7750 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_cmd_wprotect_write(int value) { if (true) { _nocheck__trace_via1_rtc_cmd_wprotect_write(value); } } #define TRACE_VIA1_RTC_CMD_PRAM_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_PRAM_READ) || \ false) static inline void _nocheck__trace_via1_rtc_cmd_pram_read(int addr, int value) { if (trace_event_get_state(TRACE_VIA1_RTC_CMD_PRAM_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 321 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_cmd_pram_read " "addr=%u value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, value); #line 7777 "trace/trace-hw_misc.h" } else { #line 321 "../hw/misc/trace-events" qemu_log("via1_rtc_cmd_pram_read " "addr=%u value=0x%02x" "\n", addr, value); #line 7781 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_cmd_pram_read(int addr, int value) { if (true) { _nocheck__trace_via1_rtc_cmd_pram_read(addr, value); } } #define TRACE_VIA1_RTC_CMD_PRAM_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_PRAM_WRITE) || \ false) static inline void _nocheck__trace_via1_rtc_cmd_pram_write(int addr, int value) { if (trace_event_get_state(TRACE_VIA1_RTC_CMD_PRAM_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 322 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_cmd_pram_write " "addr=%u value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, value); #line 7808 "trace/trace-hw_misc.h" } else { #line 322 "../hw/misc/trace-events" qemu_log("via1_rtc_cmd_pram_write " "addr=%u value=0x%02x" "\n", addr, value); #line 7812 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_cmd_pram_write(int addr, int value) { if (true) { _nocheck__trace_via1_rtc_cmd_pram_write(addr, value); } } #define TRACE_VIA1_RTC_CMD_PRAM_SECT_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_PRAM_SECT_READ) || \ false) static inline void _nocheck__trace_via1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value) { if (trace_event_get_state(TRACE_VIA1_RTC_CMD_PRAM_SECT_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 323 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_cmd_pram_sect_read " "sector=%u offset=%u addr=0x%x value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , sector, offset, addr, value); #line 7839 "trace/trace-hw_misc.h" } else { #line 323 "../hw/misc/trace-events" qemu_log("via1_rtc_cmd_pram_sect_read " "sector=%u offset=%u addr=0x%x value=0x%02x" "\n", sector, offset, addr, value); #line 7843 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value) { if (true) { _nocheck__trace_via1_rtc_cmd_pram_sect_read(sector, offset, addr, value); } } #define TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE) || \ false) static inline void _nocheck__trace_via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) { if (trace_event_get_state(TRACE_VIA1_RTC_CMD_PRAM_SECT_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 324 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_rtc_cmd_pram_sect_write " "sector=%u offset=%u addr=0x%x value=0x%02x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , sector, offset, addr, value); #line 7870 "trace/trace-hw_misc.h" } else { #line 324 "../hw/misc/trace-events" qemu_log("via1_rtc_cmd_pram_sect_write " "sector=%u offset=%u addr=0x%x value=0x%02x" "\n", sector, offset, addr, value); #line 7874 "trace/trace-hw_misc.h" } } } static inline void trace_via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) { if (true) { _nocheck__trace_via1_rtc_cmd_pram_sect_write(sector, offset, addr, value); } } #define TRACE_VIA1_ADB_SEND_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_ADB_SEND) || \ false) static inline void _nocheck__trace_via1_adb_send(const char * state, uint8_t data, const char * vadbint) { if (trace_event_get_state(TRACE_VIA1_ADB_SEND) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 325 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_adb_send " "state %s data=0x%02x vADBInt=%s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , state, data, vadbint); #line 7901 "trace/trace-hw_misc.h" } else { #line 325 "../hw/misc/trace-events" qemu_log("via1_adb_send " "state %s data=0x%02x vADBInt=%s" "\n", state, data, vadbint); #line 7905 "trace/trace-hw_misc.h" } } } static inline void trace_via1_adb_send(const char * state, uint8_t data, const char * vadbint) { if (true) { _nocheck__trace_via1_adb_send(state, data, vadbint); } } #define TRACE_VIA1_ADB_RECEIVE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_ADB_RECEIVE) || \ false) static inline void _nocheck__trace_via1_adb_receive(const char * state, uint8_t data, const char * vadbint, int status, int index, int size) { if (trace_event_get_state(TRACE_VIA1_ADB_RECEIVE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 326 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_adb_receive " "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , state, data, vadbint, status, index, size); #line 7932 "trace/trace-hw_misc.h" } else { #line 326 "../hw/misc/trace-events" qemu_log("via1_adb_receive " "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" "\n", state, data, vadbint, status, index, size); #line 7936 "trace/trace-hw_misc.h" } } } static inline void trace_via1_adb_receive(const char * state, uint8_t data, const char * vadbint, int status, int index, int size) { if (true) { _nocheck__trace_via1_adb_receive(state, data, vadbint, status, index, size); } } #define TRACE_VIA1_ADB_POLL_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_ADB_POLL) || \ false) static inline void _nocheck__trace_via1_adb_poll(uint8_t data, const char * vadbint, int status, int index, int size) { if (trace_event_get_state(TRACE_VIA1_ADB_POLL) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 327 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_adb_poll " "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , data, vadbint, status, index, size); #line 7963 "trace/trace-hw_misc.h" } else { #line 327 "../hw/misc/trace-events" qemu_log("via1_adb_poll " "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" "\n", data, vadbint, status, index, size); #line 7967 "trace/trace-hw_misc.h" } } } static inline void trace_via1_adb_poll(uint8_t data, const char * vadbint, int status, int index, int size) { if (true) { _nocheck__trace_via1_adb_poll(data, vadbint, status, index, size); } } #define TRACE_VIA1_ADB_NETBSD_ENUM_HACK_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_ADB_NETBSD_ENUM_HACK) || \ false) static inline void _nocheck__trace_via1_adb_netbsd_enum_hack(void) { if (trace_event_get_state(TRACE_VIA1_ADB_NETBSD_ENUM_HACK) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 328 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_adb_netbsd_enum_hack " "using NetBSD enum hack" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec ); #line 7994 "trace/trace-hw_misc.h" } else { #line 328 "../hw/misc/trace-events" qemu_log("via1_adb_netbsd_enum_hack " "using NetBSD enum hack" "\n"); #line 7998 "trace/trace-hw_misc.h" } } } static inline void trace_via1_adb_netbsd_enum_hack(void) { if (true) { _nocheck__trace_via1_adb_netbsd_enum_hack(); } } #define TRACE_VIA1_AUXMODE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_AUXMODE) || \ false) static inline void _nocheck__trace_via1_auxmode(int mode) { if (trace_event_get_state(TRACE_VIA1_AUXMODE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 329 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_auxmode " "setting auxmode to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , mode); #line 8025 "trace/trace-hw_misc.h" } else { #line 329 "../hw/misc/trace-events" qemu_log("via1_auxmode " "setting auxmode to %d" "\n", mode); #line 8029 "trace/trace-hw_misc.h" } } } static inline void trace_via1_auxmode(int mode) { if (true) { _nocheck__trace_via1_auxmode(mode); } } #define TRACE_VIA1_TIMER_HACK_STATE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIA1_TIMER_HACK_STATE) || \ false) static inline void _nocheck__trace_via1_timer_hack_state(int state) { if (trace_event_get_state(TRACE_VIA1_TIMER_HACK_STATE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 330 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:via1_timer_hack_state " "setting timer_hack_state to %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , state); #line 8056 "trace/trace-hw_misc.h" } else { #line 330 "../hw/misc/trace-events" qemu_log("via1_timer_hack_state " "setting timer_hack_state to %d" "\n", state); #line 8060 "trace/trace-hw_misc.h" } } } static inline void trace_via1_timer_hack_state(int state) { if (true) { _nocheck__trace_via1_timer_hack_state(state); } } #define TRACE_GRLIB_AHB_PNP_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GRLIB_AHB_PNP_READ) || \ false) static inline void _nocheck__trace_grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) { if (trace_event_get_state(TRACE_GRLIB_AHB_PNP_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 333 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:grlib_ahb_pnp_read " "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, size, value); #line 8087 "trace/trace-hw_misc.h" } else { #line 333 "../hw/misc/trace-events" qemu_log("grlib_ahb_pnp_read " "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" "\n", addr, size, value); #line 8091 "trace/trace-hw_misc.h" } } } static inline void trace_grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) { if (true) { _nocheck__trace_grlib_ahb_pnp_read(addr, size, value); } } #define TRACE_GRLIB_APB_PNP_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_GRLIB_APB_PNP_READ) || \ false) static inline void _nocheck__trace_grlib_apb_pnp_read(uint64_t addr, unsigned size, uint32_t value) { if (trace_event_get_state(TRACE_GRLIB_APB_PNP_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 334 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:grlib_apb_pnp_read " "APB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, size, value); #line 8118 "trace/trace-hw_misc.h" } else { #line 334 "../hw/misc/trace-events" qemu_log("grlib_apb_pnp_read " "APB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" "\n", addr, size, value); #line 8122 "trace/trace-hw_misc.h" } } } static inline void trace_grlib_apb_pnp_read(uint64_t addr, unsigned size, uint32_t value) { if (true) { _nocheck__trace_grlib_apb_pnp_read(addr, size, value); } } #define TRACE_LED_SET_INTENSITY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LED_SET_INTENSITY) || \ false) static inline void _nocheck__trace_led_set_intensity(const char * color, const char * desc, uint8_t intensity_percent) { if (trace_event_get_state(TRACE_LED_SET_INTENSITY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 337 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:led_set_intensity " "LED desc:'%s' color:%s intensity: %u%%" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , color, desc, intensity_percent); #line 8149 "trace/trace-hw_misc.h" } else { #line 337 "../hw/misc/trace-events" qemu_log("led_set_intensity " "LED desc:'%s' color:%s intensity: %u%%" "\n", color, desc, intensity_percent); #line 8153 "trace/trace-hw_misc.h" } } } static inline void trace_led_set_intensity(const char * color, const char * desc, uint8_t intensity_percent) { if (true) { _nocheck__trace_led_set_intensity(color, desc, intensity_percent); } } #define TRACE_LED_CHANGE_INTENSITY_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LED_CHANGE_INTENSITY) || \ false) static inline void _nocheck__trace_led_change_intensity(const char * color, const char * desc, uint8_t old_intensity_percent, uint8_t new_intensity_percent) { if (trace_event_get_state(TRACE_LED_CHANGE_INTENSITY) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 338 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:led_change_intensity " "LED desc:'%s' color:%s intensity %u%% -> %u%%" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , color, desc, old_intensity_percent, new_intensity_percent); #line 8180 "trace/trace-hw_misc.h" } else { #line 338 "../hw/misc/trace-events" qemu_log("led_change_intensity " "LED desc:'%s' color:%s intensity %u%% -> %u%%" "\n", color, desc, old_intensity_percent, new_intensity_percent); #line 8184 "trace/trace-hw_misc.h" } } } static inline void trace_led_change_intensity(const char * color, const char * desc, uint8_t old_intensity_percent, uint8_t new_intensity_percent) { if (true) { _nocheck__trace_led_change_intensity(color, desc, old_intensity_percent, new_intensity_percent); } } #define TRACE_BCM2835_CPRMAN_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_BCM2835_CPRMAN_READ) || \ false) static inline void _nocheck__trace_bcm2835_cprman_read(uint64_t offset, uint64_t value) { if (trace_event_get_state(TRACE_BCM2835_CPRMAN_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 341 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:bcm2835_cprman_read " "offset:0x%" PRIx64 " value:0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value); #line 8211 "trace/trace-hw_misc.h" } else { #line 341 "../hw/misc/trace-events" qemu_log("bcm2835_cprman_read " "offset:0x%" PRIx64 " value:0x%" PRIx64 "\n", offset, value); #line 8215 "trace/trace-hw_misc.h" } } } static inline void trace_bcm2835_cprman_read(uint64_t offset, uint64_t value) { if (true) { _nocheck__trace_bcm2835_cprman_read(offset, value); } } #define TRACE_BCM2835_CPRMAN_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_BCM2835_CPRMAN_WRITE) || \ false) static inline void _nocheck__trace_bcm2835_cprman_write(uint64_t offset, uint64_t value) { if (trace_event_get_state(TRACE_BCM2835_CPRMAN_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 342 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:bcm2835_cprman_write " "offset:0x%" PRIx64 " value:0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value); #line 8242 "trace/trace-hw_misc.h" } else { #line 342 "../hw/misc/trace-events" qemu_log("bcm2835_cprman_write " "offset:0x%" PRIx64 " value:0x%" PRIx64 "\n", offset, value); #line 8246 "trace/trace-hw_misc.h" } } } static inline void trace_bcm2835_cprman_write(uint64_t offset, uint64_t value) { if (true) { _nocheck__trace_bcm2835_cprman_write(offset, value); } } #define TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC) || \ false) static inline void _nocheck__trace_bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) { if (trace_event_get_state(TRACE_BCM2835_CPRMAN_WRITE_INVALID_MAGIC) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 343 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:bcm2835_cprman_write_invalid_magic " "offset:0x%" PRIx64 " value:0x%" PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, value); #line 8273 "trace/trace-hw_misc.h" } else { #line 343 "../hw/misc/trace-events" qemu_log("bcm2835_cprman_write_invalid_magic " "offset:0x%" PRIx64 " value:0x%" PRIx64 "\n", offset, value); #line 8277 "trace/trace-hw_misc.h" } } } static inline void trace_bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) { if (true) { _nocheck__trace_bcm2835_cprman_write_invalid_magic(offset, value); } } #define TRACE_VIRT_CTRL_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRT_CTRL_READ) || \ false) static inline void _nocheck__trace_virt_ctrl_read(void * dev, unsigned int addr, unsigned int size, uint64_t value) { if (trace_event_get_state(TRACE_VIRT_CTRL_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 346 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:virt_ctrl_read " "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dev, addr, size, value); #line 8304 "trace/trace-hw_misc.h" } else { #line 346 "../hw/misc/trace-events" qemu_log("virt_ctrl_read " "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", dev, addr, size, value); #line 8308 "trace/trace-hw_misc.h" } } } static inline void trace_virt_ctrl_read(void * dev, unsigned int addr, unsigned int size, uint64_t value) { if (true) { _nocheck__trace_virt_ctrl_read(dev, addr, size, value); } } #define TRACE_VIRT_CTRL_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRT_CTRL_WRITE) || \ false) static inline void _nocheck__trace_virt_ctrl_write(void * dev, unsigned int addr, unsigned int size, uint64_t value) { if (trace_event_get_state(TRACE_VIRT_CTRL_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 347 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:virt_ctrl_write " "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dev, addr, size, value); #line 8335 "trace/trace-hw_misc.h" } else { #line 347 "../hw/misc/trace-events" qemu_log("virt_ctrl_write " "ctrl: %p reg: 0x%02x size: %d value: 0x%"PRIx64 "\n", dev, addr, size, value); #line 8339 "trace/trace-hw_misc.h" } } } static inline void trace_virt_ctrl_write(void * dev, unsigned int addr, unsigned int size, uint64_t value) { if (true) { _nocheck__trace_virt_ctrl_write(dev, addr, size, value); } } #define TRACE_VIRT_CTRL_RESET_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRT_CTRL_RESET) || \ false) static inline void _nocheck__trace_virt_ctrl_reset(void * dev) { if (trace_event_get_state(TRACE_VIRT_CTRL_RESET) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 348 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:virt_ctrl_reset " "ctrl: %p" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dev); #line 8366 "trace/trace-hw_misc.h" } else { #line 348 "../hw/misc/trace-events" qemu_log("virt_ctrl_reset " "ctrl: %p" "\n", dev); #line 8370 "trace/trace-hw_misc.h" } } } static inline void trace_virt_ctrl_reset(void * dev) { if (true) { _nocheck__trace_virt_ctrl_reset(dev); } } #define TRACE_VIRT_CTRL_REALIZE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRT_CTRL_REALIZE) || \ false) static inline void _nocheck__trace_virt_ctrl_realize(void * dev) { if (trace_event_get_state(TRACE_VIRT_CTRL_REALIZE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 349 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:virt_ctrl_realize " "ctrl: %p" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dev); #line 8397 "trace/trace-hw_misc.h" } else { #line 349 "../hw/misc/trace-events" qemu_log("virt_ctrl_realize " "ctrl: %p" "\n", dev); #line 8401 "trace/trace-hw_misc.h" } } } static inline void trace_virt_ctrl_realize(void * dev) { if (true) { _nocheck__trace_virt_ctrl_realize(dev); } } #define TRACE_VIRT_CTRL_INSTANCE_INIT_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_VIRT_CTRL_INSTANCE_INIT) || \ false) static inline void _nocheck__trace_virt_ctrl_instance_init(void * dev) { if (trace_event_get_state(TRACE_VIRT_CTRL_INSTANCE_INIT) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 350 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:virt_ctrl_instance_init " "ctrl: %p" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , dev); #line 8428 "trace/trace-hw_misc.h" } else { #line 350 "../hw/misc/trace-events" qemu_log("virt_ctrl_instance_init " "ctrl: %p" "\n", dev); #line 8432 "trace/trace-hw_misc.h" } } } static inline void trace_virt_ctrl_instance_init(void * dev) { if (true) { _nocheck__trace_virt_ctrl_instance_init(dev); } } #define TRACE_LASI_CHIP_MEM_VALID_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LASI_CHIP_MEM_VALID) || \ false) static inline void _nocheck__trace_lasi_chip_mem_valid(uint64_t addr, uint32_t val) { if (trace_event_get_state(TRACE_LASI_CHIP_MEM_VALID) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 353 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:lasi_chip_mem_valid " "access to addr 0x%"PRIx64" is %d" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 8459 "trace/trace-hw_misc.h" } else { #line 353 "../hw/misc/trace-events" qemu_log("lasi_chip_mem_valid " "access to addr 0x%"PRIx64" is %d" "\n", addr, val); #line 8463 "trace/trace-hw_misc.h" } } } static inline void trace_lasi_chip_mem_valid(uint64_t addr, uint32_t val) { if (true) { _nocheck__trace_lasi_chip_mem_valid(addr, val); } } #define TRACE_LASI_CHIP_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LASI_CHIP_READ) || \ false) static inline void _nocheck__trace_lasi_chip_read(uint64_t addr, uint32_t val) { if (trace_event_get_state(TRACE_LASI_CHIP_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 354 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:lasi_chip_read " "addr 0x%"PRIx64" val 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 8490 "trace/trace-hw_misc.h" } else { #line 354 "../hw/misc/trace-events" qemu_log("lasi_chip_read " "addr 0x%"PRIx64" val 0x%08x" "\n", addr, val); #line 8494 "trace/trace-hw_misc.h" } } } static inline void trace_lasi_chip_read(uint64_t addr, uint32_t val) { if (true) { _nocheck__trace_lasi_chip_read(addr, val); } } #define TRACE_LASI_CHIP_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_LASI_CHIP_WRITE) || \ false) static inline void _nocheck__trace_lasi_chip_write(uint64_t addr, uint32_t val) { if (trace_event_get_state(TRACE_LASI_CHIP_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 355 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:lasi_chip_write " "addr 0x%"PRIx64" val 0x%08x" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , addr, val); #line 8521 "trace/trace-hw_misc.h" } else { #line 355 "../hw/misc/trace-events" qemu_log("lasi_chip_write " "addr 0x%"PRIx64" val 0x%08x" "\n", addr, val); #line 8525 "trace/trace-hw_misc.h" } } } static inline void trace_lasi_chip_write(uint64_t addr, uint32_t val) { if (true) { _nocheck__trace_lasi_chip_write(addr, val); } } #define TRACE_DJMEMC_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DJMEMC_READ) || \ false) static inline void _nocheck__trace_djmemc_read(int reg, uint64_t value, unsigned int size) { if (trace_event_get_state(TRACE_DJMEMC_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 358 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:djmemc_read " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, value, size); #line 8552 "trace/trace-hw_misc.h" } else { #line 358 "../hw/misc/trace-events" qemu_log("djmemc_read " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", reg, value, size); #line 8556 "trace/trace-hw_misc.h" } } } static inline void trace_djmemc_read(int reg, uint64_t value, unsigned int size) { if (true) { _nocheck__trace_djmemc_read(reg, value, size); } } #define TRACE_DJMEMC_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_DJMEMC_WRITE) || \ false) static inline void _nocheck__trace_djmemc_write(int reg, uint64_t value, unsigned int size) { if (trace_event_get_state(TRACE_DJMEMC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 359 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:djmemc_write " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, value, size); #line 8583 "trace/trace-hw_misc.h" } else { #line 359 "../hw/misc/trace-events" qemu_log("djmemc_write " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", reg, value, size); #line 8587 "trace/trace-hw_misc.h" } } } static inline void trace_djmemc_write(int reg, uint64_t value, unsigned int size) { if (true) { _nocheck__trace_djmemc_write(reg, value, size); } } #define TRACE_IOSB_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOSB_READ) || \ false) static inline void _nocheck__trace_iosb_read(int reg, uint64_t value, unsigned int size) { if (trace_event_get_state(TRACE_IOSB_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 362 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:iosb_read " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, value, size); #line 8614 "trace/trace-hw_misc.h" } else { #line 362 "../hw/misc/trace-events" qemu_log("iosb_read " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", reg, value, size); #line 8618 "trace/trace-hw_misc.h" } } } static inline void trace_iosb_read(int reg, uint64_t value, unsigned int size) { if (true) { _nocheck__trace_iosb_read(reg, value, size); } } #define TRACE_IOSB_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_IOSB_WRITE) || \ false) static inline void _nocheck__trace_iosb_write(int reg, uint64_t value, unsigned int size) { if (trace_event_get_state(TRACE_IOSB_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 363 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:iosb_write " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , reg, value, size); #line 8645 "trace/trace-hw_misc.h" } else { #line 363 "../hw/misc/trace-events" qemu_log("iosb_write " "reg=0x%x value=0x%"PRIx64" size=%u" "\n", reg, value, size); #line 8649 "trace/trace-hw_misc.h" } } } static inline void trace_iosb_write(int reg, uint64_t value, unsigned int size) { if (true) { _nocheck__trace_iosb_write(reg, value, size); } } #define TRACE_ASPEED_SLI_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SLI_WRITE) || \ false) static inline void _nocheck__trace_aspeed_sli_write(uint64_t offset, unsigned int size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_SLI_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 366 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_sli_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 8676 "trace/trace-hw_misc.h" } else { #line 366 "../hw/misc/trace-events" qemu_log("aspeed_sli_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 8680 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_sli_write(uint64_t offset, unsigned int size, uint32_t data) { if (true) { _nocheck__trace_aspeed_sli_write(offset, size, data); } } #define TRACE_ASPEED_SLI_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SLI_READ) || \ false) static inline void _nocheck__trace_aspeed_sli_read(uint64_t offset, unsigned int size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_SLI_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 367 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_sli_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 8707 "trace/trace-hw_misc.h" } else { #line 367 "../hw/misc/trace-events" qemu_log("aspeed_sli_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 8711 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_sli_read(uint64_t offset, unsigned int size, uint32_t data) { if (true) { _nocheck__trace_aspeed_sli_read(offset, size, data); } } #define TRACE_ASPEED_SLIIO_WRITE_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SLIIO_WRITE) || \ false) static inline void _nocheck__trace_aspeed_sliio_write(uint64_t offset, unsigned int size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_SLIIO_WRITE) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 368 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_sliio_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 8738 "trace/trace-hw_misc.h" } else { #line 368 "../hw/misc/trace-events" qemu_log("aspeed_sliio_write " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 8742 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_sliio_write(uint64_t offset, unsigned int size, uint32_t data) { if (true) { _nocheck__trace_aspeed_sliio_write(offset, size, data); } } #define TRACE_ASPEED_SLIIO_READ_BACKEND_DSTATE() ( \ trace_event_get_state_dynamic_by_id(TRACE_ASPEED_SLIIO_READ) || \ false) static inline void _nocheck__trace_aspeed_sliio_read(uint64_t offset, unsigned int size, uint32_t data) { if (trace_event_get_state(TRACE_ASPEED_SLIIO_READ) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); #line 369 "../hw/misc/trace-events" qemu_log("%d@%zu.%06zu:aspeed_sliio_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , offset, size, data); #line 8769 "trace/trace-hw_misc.h" } else { #line 369 "../hw/misc/trace-events" qemu_log("aspeed_sliio_read " "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 "\n", offset, size, data); #line 8773 "trace/trace-hw_misc.h" } } } static inline void trace_aspeed_sliio_read(uint64_t offset, unsigned int size, uint32_t data) { if (true) { _nocheck__trace_aspeed_sliio_read(offset, size, data); } } #endif /* TRACE_HW_MISC_GENERATED_TRACERS_H */