/* This file is autogenerated by tracetool, do not edit. */ #include "qemu/osdep.h" #include "qemu/module.h" #include "trace-hw_nvme.h" uint16_t _TRACE_PCI_NVME_IRQ_MSIX_DSTATE; uint16_t _TRACE_PCI_NVME_IRQ_PIN_DSTATE; uint16_t _TRACE_PCI_NVME_IRQ_MASKED_DSTATE; uint16_t _TRACE_PCI_NVME_DMA_READ_DSTATE; uint16_t _TRACE_PCI_NVME_DBBUF_CONFIG_DSTATE; uint16_t _TRACE_PCI_NVME_MAP_ADDR_DSTATE; uint16_t _TRACE_PCI_NVME_MAP_ADDR_CMB_DSTATE; uint16_t _TRACE_PCI_NVME_MAP_PRP_DSTATE; uint16_t _TRACE_PCI_NVME_MAP_SGL_DSTATE; uint16_t _TRACE_PCI_NVME_IO_CMD_DSTATE; uint16_t _TRACE_PCI_NVME_ADMIN_CMD_DSTATE; uint16_t _TRACE_PCI_NVME_FLUSH_NS_DSTATE; uint16_t _TRACE_PCI_NVME_FORMAT_SET_DSTATE; uint16_t _TRACE_PCI_NVME_READ_DSTATE; uint16_t _TRACE_PCI_NVME_WRITE_DSTATE; uint16_t _TRACE_PCI_NVME_RW_CB_DSTATE; uint16_t _TRACE_PCI_NVME_MISC_CB_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_RW_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_RW_CB_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_RW_MDATA_IN_CB_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_RW_MDATA_OUT_CB_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_RW_CHECK_CB_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC16_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC64_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_CHECK_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC16_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC64_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC16_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC64_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_PRCHK_APPTAG_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC16_DSTATE; uint16_t _TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC64_DSTATE; uint16_t _TRACE_PCI_NVME_COPY_DSTATE; uint16_t _TRACE_PCI_NVME_COPY_SOURCE_RANGE_DSTATE; uint16_t _TRACE_PCI_NVME_COPY_OUT_DSTATE; uint16_t _TRACE_PCI_NVME_VERIFY_DSTATE; uint16_t _TRACE_PCI_NVME_VERIFY_MDATA_IN_CB_DSTATE; uint16_t _TRACE_PCI_NVME_VERIFY_CB_DSTATE; uint16_t _TRACE_PCI_NVME_RW_COMPLETE_CB_DSTATE; uint16_t _TRACE_PCI_NVME_BLOCK_STATUS_DSTATE; uint16_t _TRACE_PCI_NVME_DSM_DSTATE; uint16_t _TRACE_PCI_NVME_DSM_DEALLOCATE_DSTATE; uint16_t _TRACE_PCI_NVME_DSM_SINGLE_RANGE_LIMIT_EXCEEDED_DSTATE; uint16_t _TRACE_PCI_NVME_COMPARE_DSTATE; uint16_t _TRACE_PCI_NVME_COMPARE_DATA_CB_DSTATE; uint16_t _TRACE_PCI_NVME_COMPARE_MDATA_CB_DSTATE; uint16_t _TRACE_PCI_NVME_AIO_DISCARD_CB_DSTATE; uint16_t _TRACE_PCI_NVME_AIO_COPY_IN_CB_DSTATE; uint16_t _TRACE_PCI_NVME_AIO_FLUSH_CB_DSTATE; uint16_t _TRACE_PCI_NVME_CREATE_SQ_DSTATE; uint16_t _TRACE_PCI_NVME_CREATE_CQ_DSTATE; uint16_t _TRACE_PCI_NVME_DEL_SQ_DSTATE; uint16_t _TRACE_PCI_NVME_DEL_CQ_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_CTRL_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_CTRL_CSI_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_NS_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_NS_IND_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_CTRL_LIST_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_PRI_CTRL_CAP_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_SEC_CTRL_LIST_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_NS_CSI_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_NSLIST_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_NSLIST_CSI_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_CMD_SET_DSTATE; uint16_t _TRACE_PCI_NVME_IDENTIFY_NS_DESCR_LIST_DSTATE; uint16_t _TRACE_PCI_NVME_GET_LOG_DSTATE; uint16_t _TRACE_PCI_NVME_GETFEAT_DSTATE; uint16_t _TRACE_PCI_NVME_SETFEAT_DSTATE; uint16_t _TRACE_PCI_NVME_GETFEAT_VWCACHE_DSTATE; uint16_t _TRACE_PCI_NVME_GETFEAT_NUMQ_DSTATE; uint16_t _TRACE_PCI_NVME_SETFEAT_NUMQ_DSTATE; uint16_t _TRACE_PCI_NVME_SETFEAT_TIMESTAMP_DSTATE; uint16_t _TRACE_PCI_NVME_GETFEAT_TIMESTAMP_DSTATE; uint16_t _TRACE_PCI_NVME_PROCESS_AERS_DSTATE; uint16_t _TRACE_PCI_NVME_AER_DSTATE; uint16_t _TRACE_PCI_NVME_AER_AERL_EXCEEDED_DSTATE; uint16_t _TRACE_PCI_NVME_AER_MASKED_DSTATE; uint16_t _TRACE_PCI_NVME_AER_POST_CQE_DSTATE; uint16_t _TRACE_PCI_NVME_NS_ATTACHMENT_DSTATE; uint16_t _TRACE_PCI_NVME_NS_ATTACHMENT_ATTACH_DSTATE; uint16_t _TRACE_PCI_NVME_ENQUEUE_EVENT_DSTATE; uint16_t _TRACE_PCI_NVME_ENQUEUE_EVENT_NOQUEUE_DSTATE; uint16_t _TRACE_PCI_NVME_ENQUEUE_EVENT_MASKED_DSTATE; uint16_t _TRACE_PCI_NVME_NO_OUTSTANDING_AERS_DSTATE; uint16_t _TRACE_PCI_NVME_ENQUEUE_REQ_COMPLETION_DSTATE; uint16_t _TRACE_PCI_NVME_UPDATE_CQ_EVENTIDX_DSTATE; uint16_t _TRACE_PCI_NVME_UPDATE_SQ_EVENTIDX_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_READ_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_WRITE_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_DOORBELL_CQ_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_DOORBELL_SQ_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_INTM_SET_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_INTM_CLR_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_CFG_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_AQATTR_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_ASQADDR_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_ACQADDR_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_ASQADDR_HI_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_ACQADDR_HI_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_START_SUCCESS_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_STOPPED_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_SHUTDOWN_SET_DSTATE; uint16_t _TRACE_PCI_NVME_MMIO_SHUTDOWN_CLEARED_DSTATE; uint16_t _TRACE_PCI_NVME_UPDATE_CQ_HEAD_DSTATE; uint16_t _TRACE_PCI_NVME_UPDATE_SQ_TAIL_DSTATE; uint16_t _TRACE_PCI_NVME_OPEN_ZONE_DSTATE; uint16_t _TRACE_PCI_NVME_CLOSE_ZONE_DSTATE; uint16_t _TRACE_PCI_NVME_FINISH_ZONE_DSTATE; uint16_t _TRACE_PCI_NVME_RESET_ZONE_DSTATE; uint16_t _TRACE_PCI_NVME_ZNS_ZONE_RESET_DSTATE; uint16_t _TRACE_PCI_NVME_OFFLINE_ZONE_DSTATE; uint16_t _TRACE_PCI_NVME_SET_DESCRIPTOR_EXTENSION_DSTATE; uint16_t _TRACE_PCI_NVME_ZD_EXTENSION_SET_DSTATE; uint16_t _TRACE_PCI_NVME_CLEAR_NS_CLOSE_DSTATE; uint16_t _TRACE_PCI_NVME_CLEAR_NS_RESET_DSTATE; uint16_t _TRACE_PCI_NVME_ZONED_ZRWA_IMPLICIT_FLUSH_DSTATE; uint16_t _TRACE_PCI_NVME_PCI_RESET_DSTATE; uint16_t _TRACE_PCI_NVME_VIRT_MNGMT_DSTATE; uint16_t _TRACE_PCI_NVME_FDP_RUH_CHANGE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_MDTS_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_ZASL_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_REQ_STATUS_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_ADDR_READ_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_ADDR_WRITE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_CFS_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_AIO_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_COPY_INVALID_FORMAT_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_SGLD_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_NUM_SGLD_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_SGL_EXCESS_LENGTH_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_DMA_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_PRPLIST_ENT_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_PRP2_ALIGN_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_OPC_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_ADMIN_OPC_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_LBA_RANGE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_OFFSET_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_CMB_INVALID_CBA_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_CMB_NOT_ENABLED_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_UNALIGNED_ZONE_CMD_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_ZONE_STATE_TRANSITION_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_WRITE_NOT_AT_WP_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_APPEND_NOT_AT_START_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_ZONE_IS_FULL_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_ZONE_IS_READ_ONLY_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_ZONE_IS_OFFLINE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_ZONE_BOUNDARY_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_ZONE_INVALID_WRITE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_ZONE_WRITE_NOT_OK_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_ZONE_READ_NOT_OK_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INSUFF_ACTIVE_RES_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INSUFF_OPEN_RES_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_ZD_EXTENSION_MAP_ERROR_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_IOCSCI_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_DEL_SQ_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_CQID_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SQID_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SIZE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_ADDR_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_QFLAGS_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_CQID_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_NOTEMPTY_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_CQID_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_SIZE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ADDR_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_VECTOR_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_QFLAGS_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ENTRY_SIZE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_IDENTIFY_CNS_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_GETFEAT_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_SETFEAT_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_CQ_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_SQ_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_ASQ_MISALIGNED_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_ACQ_MISALIGNED_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_SMALL_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_LARGE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_SMALL_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_LARGE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_SMALL_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_LARGE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_CSS_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_ASQENT_SZ_ZERO_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_ACQENT_SZ_ZERO_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_ZASL_TOO_SMALL_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_STARTFAIL_VIRT_STATE_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_INVALID_MGMT_ACTION_DSTATE; uint16_t _TRACE_PCI_NVME_ERR_IGNORED_MMIO_VF_OFFLINE_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_MISALIGNED32_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_TOOSMALL_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_INTMASK_WITH_MSIX_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_RO_CSTS_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_SSRESET_W1C_UNSUPPORTED_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_SSRESET_UNSUPPORTED_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_CMBLOC_RESERVED_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_CMBSZ_READONLY_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_PMRCAP_READONLY_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_PMRSTS_READONLY_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_PMREBS_READONLY_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_PMRSWTP_READONLY_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIOWR_INVALID_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIORD_MISALIGNED32_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIORD_TOOSMALL_DSTATE; uint16_t _TRACE_PCI_NVME_UB_MMIORD_INVALID_OFS_DSTATE; uint16_t _TRACE_PCI_NVME_UB_DB_WR_MISALIGNED_DSTATE; uint16_t _TRACE_PCI_NVME_UB_DB_WR_INVALID_CQ_DSTATE; uint16_t _TRACE_PCI_NVME_UB_DB_WR_INVALID_CQHEAD_DSTATE; uint16_t _TRACE_PCI_NVME_UB_DB_WR_INVALID_SQ_DSTATE; uint16_t _TRACE_PCI_NVME_UB_DB_WR_INVALID_SQTAIL_DSTATE; uint16_t _TRACE_PCI_NVME_UB_UNKNOWN_CSS_VALUE_DSTATE; uint16_t _TRACE_PCI_NVME_UB_TOO_MANY_MAPPINGS_DSTATE; TraceEvent _TRACE_PCI_NVME_IRQ_MSIX_EVENT = { .id = 0, .name = "pci_nvme_irq_msix", .sstate = TRACE_PCI_NVME_IRQ_MSIX_ENABLED, .dstate = &_TRACE_PCI_NVME_IRQ_MSIX_DSTATE }; TraceEvent _TRACE_PCI_NVME_IRQ_PIN_EVENT = { .id = 0, .name = "pci_nvme_irq_pin", .sstate = TRACE_PCI_NVME_IRQ_PIN_ENABLED, .dstate = &_TRACE_PCI_NVME_IRQ_PIN_DSTATE }; TraceEvent _TRACE_PCI_NVME_IRQ_MASKED_EVENT = { .id = 0, .name = "pci_nvme_irq_masked", .sstate = TRACE_PCI_NVME_IRQ_MASKED_ENABLED, .dstate = &_TRACE_PCI_NVME_IRQ_MASKED_DSTATE }; TraceEvent _TRACE_PCI_NVME_DMA_READ_EVENT = { .id = 0, .name = "pci_nvme_dma_read", .sstate = TRACE_PCI_NVME_DMA_READ_ENABLED, .dstate = &_TRACE_PCI_NVME_DMA_READ_DSTATE }; TraceEvent _TRACE_PCI_NVME_DBBUF_CONFIG_EVENT = { .id = 0, .name = "pci_nvme_dbbuf_config", .sstate = TRACE_PCI_NVME_DBBUF_CONFIG_ENABLED, .dstate = &_TRACE_PCI_NVME_DBBUF_CONFIG_DSTATE }; TraceEvent _TRACE_PCI_NVME_MAP_ADDR_EVENT = { .id = 0, .name = "pci_nvme_map_addr", .sstate = TRACE_PCI_NVME_MAP_ADDR_ENABLED, .dstate = &_TRACE_PCI_NVME_MAP_ADDR_DSTATE }; TraceEvent _TRACE_PCI_NVME_MAP_ADDR_CMB_EVENT = { .id = 0, .name = "pci_nvme_map_addr_cmb", .sstate = TRACE_PCI_NVME_MAP_ADDR_CMB_ENABLED, .dstate = &_TRACE_PCI_NVME_MAP_ADDR_CMB_DSTATE }; TraceEvent _TRACE_PCI_NVME_MAP_PRP_EVENT = { .id = 0, .name = "pci_nvme_map_prp", .sstate = TRACE_PCI_NVME_MAP_PRP_ENABLED, .dstate = &_TRACE_PCI_NVME_MAP_PRP_DSTATE }; TraceEvent _TRACE_PCI_NVME_MAP_SGL_EVENT = { .id = 0, .name = "pci_nvme_map_sgl", .sstate = TRACE_PCI_NVME_MAP_SGL_ENABLED, .dstate = &_TRACE_PCI_NVME_MAP_SGL_DSTATE }; TraceEvent _TRACE_PCI_NVME_IO_CMD_EVENT = { .id = 0, .name = "pci_nvme_io_cmd", .sstate = TRACE_PCI_NVME_IO_CMD_ENABLED, .dstate = &_TRACE_PCI_NVME_IO_CMD_DSTATE }; TraceEvent _TRACE_PCI_NVME_ADMIN_CMD_EVENT = { .id = 0, .name = "pci_nvme_admin_cmd", .sstate = TRACE_PCI_NVME_ADMIN_CMD_ENABLED, .dstate = &_TRACE_PCI_NVME_ADMIN_CMD_DSTATE }; TraceEvent _TRACE_PCI_NVME_FLUSH_NS_EVENT = { .id = 0, .name = "pci_nvme_flush_ns", .sstate = TRACE_PCI_NVME_FLUSH_NS_ENABLED, .dstate = &_TRACE_PCI_NVME_FLUSH_NS_DSTATE }; TraceEvent _TRACE_PCI_NVME_FORMAT_SET_EVENT = { .id = 0, .name = "pci_nvme_format_set", .sstate = TRACE_PCI_NVME_FORMAT_SET_ENABLED, .dstate = &_TRACE_PCI_NVME_FORMAT_SET_DSTATE }; TraceEvent _TRACE_PCI_NVME_READ_EVENT = { .id = 0, .name = "pci_nvme_read", .sstate = TRACE_PCI_NVME_READ_ENABLED, .dstate = &_TRACE_PCI_NVME_READ_DSTATE }; TraceEvent _TRACE_PCI_NVME_WRITE_EVENT = { .id = 0, .name = "pci_nvme_write", .sstate = TRACE_PCI_NVME_WRITE_ENABLED, .dstate = &_TRACE_PCI_NVME_WRITE_DSTATE }; TraceEvent _TRACE_PCI_NVME_RW_CB_EVENT = { .id = 0, .name = "pci_nvme_rw_cb", .sstate = TRACE_PCI_NVME_RW_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_RW_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_MISC_CB_EVENT = { .id = 0, .name = "pci_nvme_misc_cb", .sstate = TRACE_PCI_NVME_MISC_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_MISC_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_RW_EVENT = { .id = 0, .name = "pci_nvme_dif_rw", .sstate = TRACE_PCI_NVME_DIF_RW_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_RW_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_RW_CB_EVENT = { .id = 0, .name = "pci_nvme_dif_rw_cb", .sstate = TRACE_PCI_NVME_DIF_RW_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_RW_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_RW_MDATA_IN_CB_EVENT = { .id = 0, .name = "pci_nvme_dif_rw_mdata_in_cb", .sstate = TRACE_PCI_NVME_DIF_RW_MDATA_IN_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_RW_MDATA_IN_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_RW_MDATA_OUT_CB_EVENT = { .id = 0, .name = "pci_nvme_dif_rw_mdata_out_cb", .sstate = TRACE_PCI_NVME_DIF_RW_MDATA_OUT_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_RW_MDATA_OUT_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_RW_CHECK_CB_EVENT = { .id = 0, .name = "pci_nvme_dif_rw_check_cb", .sstate = TRACE_PCI_NVME_DIF_RW_CHECK_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_RW_CHECK_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC16_EVENT = { .id = 0, .name = "pci_nvme_dif_pract_generate_dif_crc16", .sstate = TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC16_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC16_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC64_EVENT = { .id = 0, .name = "pci_nvme_dif_pract_generate_dif_crc64", .sstate = TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC64_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC64_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_CHECK_EVENT = { .id = 0, .name = "pci_nvme_dif_check", .sstate = TRACE_PCI_NVME_DIF_CHECK_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_CHECK_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC16_EVENT = { .id = 0, .name = "pci_nvme_dif_prchk_disabled_crc16", .sstate = TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC16_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC16_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC64_EVENT = { .id = 0, .name = "pci_nvme_dif_prchk_disabled_crc64", .sstate = TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC64_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC64_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC16_EVENT = { .id = 0, .name = "pci_nvme_dif_prchk_guard_crc16", .sstate = TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC16_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC16_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC64_EVENT = { .id = 0, .name = "pci_nvme_dif_prchk_guard_crc64", .sstate = TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC64_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC64_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_APPTAG_EVENT = { .id = 0, .name = "pci_nvme_dif_prchk_apptag", .sstate = TRACE_PCI_NVME_DIF_PRCHK_APPTAG_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_PRCHK_APPTAG_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC16_EVENT = { .id = 0, .name = "pci_nvme_dif_prchk_reftag_crc16", .sstate = TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC16_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC16_DSTATE }; TraceEvent _TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC64_EVENT = { .id = 0, .name = "pci_nvme_dif_prchk_reftag_crc64", .sstate = TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC64_ENABLED, .dstate = &_TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC64_DSTATE }; TraceEvent _TRACE_PCI_NVME_COPY_EVENT = { .id = 0, .name = "pci_nvme_copy", .sstate = TRACE_PCI_NVME_COPY_ENABLED, .dstate = &_TRACE_PCI_NVME_COPY_DSTATE }; TraceEvent _TRACE_PCI_NVME_COPY_SOURCE_RANGE_EVENT = { .id = 0, .name = "pci_nvme_copy_source_range", .sstate = TRACE_PCI_NVME_COPY_SOURCE_RANGE_ENABLED, .dstate = &_TRACE_PCI_NVME_COPY_SOURCE_RANGE_DSTATE }; TraceEvent _TRACE_PCI_NVME_COPY_OUT_EVENT = { .id = 0, .name = "pci_nvme_copy_out", .sstate = TRACE_PCI_NVME_COPY_OUT_ENABLED, .dstate = &_TRACE_PCI_NVME_COPY_OUT_DSTATE }; TraceEvent _TRACE_PCI_NVME_VERIFY_EVENT = { .id = 0, .name = "pci_nvme_verify", .sstate = TRACE_PCI_NVME_VERIFY_ENABLED, .dstate = &_TRACE_PCI_NVME_VERIFY_DSTATE }; TraceEvent _TRACE_PCI_NVME_VERIFY_MDATA_IN_CB_EVENT = { .id = 0, .name = "pci_nvme_verify_mdata_in_cb", .sstate = TRACE_PCI_NVME_VERIFY_MDATA_IN_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_VERIFY_MDATA_IN_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_VERIFY_CB_EVENT = { .id = 0, .name = "pci_nvme_verify_cb", .sstate = TRACE_PCI_NVME_VERIFY_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_VERIFY_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_RW_COMPLETE_CB_EVENT = { .id = 0, .name = "pci_nvme_rw_complete_cb", .sstate = TRACE_PCI_NVME_RW_COMPLETE_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_RW_COMPLETE_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_BLOCK_STATUS_EVENT = { .id = 0, .name = "pci_nvme_block_status", .sstate = TRACE_PCI_NVME_BLOCK_STATUS_ENABLED, .dstate = &_TRACE_PCI_NVME_BLOCK_STATUS_DSTATE }; TraceEvent _TRACE_PCI_NVME_DSM_EVENT = { .id = 0, .name = "pci_nvme_dsm", .sstate = TRACE_PCI_NVME_DSM_ENABLED, .dstate = &_TRACE_PCI_NVME_DSM_DSTATE }; TraceEvent _TRACE_PCI_NVME_DSM_DEALLOCATE_EVENT = { .id = 0, .name = "pci_nvme_dsm_deallocate", .sstate = TRACE_PCI_NVME_DSM_DEALLOCATE_ENABLED, .dstate = &_TRACE_PCI_NVME_DSM_DEALLOCATE_DSTATE }; TraceEvent _TRACE_PCI_NVME_DSM_SINGLE_RANGE_LIMIT_EXCEEDED_EVENT = { .id = 0, .name = "pci_nvme_dsm_single_range_limit_exceeded", .sstate = TRACE_PCI_NVME_DSM_SINGLE_RANGE_LIMIT_EXCEEDED_ENABLED, .dstate = &_TRACE_PCI_NVME_DSM_SINGLE_RANGE_LIMIT_EXCEEDED_DSTATE }; TraceEvent _TRACE_PCI_NVME_COMPARE_EVENT = { .id = 0, .name = "pci_nvme_compare", .sstate = TRACE_PCI_NVME_COMPARE_ENABLED, .dstate = &_TRACE_PCI_NVME_COMPARE_DSTATE }; TraceEvent _TRACE_PCI_NVME_COMPARE_DATA_CB_EVENT = { .id = 0, .name = "pci_nvme_compare_data_cb", .sstate = TRACE_PCI_NVME_COMPARE_DATA_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_COMPARE_DATA_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_COMPARE_MDATA_CB_EVENT = { .id = 0, .name = "pci_nvme_compare_mdata_cb", .sstate = TRACE_PCI_NVME_COMPARE_MDATA_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_COMPARE_MDATA_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_AIO_DISCARD_CB_EVENT = { .id = 0, .name = "pci_nvme_aio_discard_cb", .sstate = TRACE_PCI_NVME_AIO_DISCARD_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_AIO_DISCARD_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_AIO_COPY_IN_CB_EVENT = { .id = 0, .name = "pci_nvme_aio_copy_in_cb", .sstate = TRACE_PCI_NVME_AIO_COPY_IN_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_AIO_COPY_IN_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_AIO_FLUSH_CB_EVENT = { .id = 0, .name = "pci_nvme_aio_flush_cb", .sstate = TRACE_PCI_NVME_AIO_FLUSH_CB_ENABLED, .dstate = &_TRACE_PCI_NVME_AIO_FLUSH_CB_DSTATE }; TraceEvent _TRACE_PCI_NVME_CREATE_SQ_EVENT = { .id = 0, .name = "pci_nvme_create_sq", .sstate = TRACE_PCI_NVME_CREATE_SQ_ENABLED, .dstate = &_TRACE_PCI_NVME_CREATE_SQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_CREATE_CQ_EVENT = { .id = 0, .name = "pci_nvme_create_cq", .sstate = TRACE_PCI_NVME_CREATE_CQ_ENABLED, .dstate = &_TRACE_PCI_NVME_CREATE_CQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_DEL_SQ_EVENT = { .id = 0, .name = "pci_nvme_del_sq", .sstate = TRACE_PCI_NVME_DEL_SQ_ENABLED, .dstate = &_TRACE_PCI_NVME_DEL_SQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_DEL_CQ_EVENT = { .id = 0, .name = "pci_nvme_del_cq", .sstate = TRACE_PCI_NVME_DEL_CQ_ENABLED, .dstate = &_TRACE_PCI_NVME_DEL_CQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_EVENT = { .id = 0, .name = "pci_nvme_identify", .sstate = TRACE_PCI_NVME_IDENTIFY_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_CTRL_EVENT = { .id = 0, .name = "pci_nvme_identify_ctrl", .sstate = TRACE_PCI_NVME_IDENTIFY_CTRL_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_CTRL_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_CTRL_CSI_EVENT = { .id = 0, .name = "pci_nvme_identify_ctrl_csi", .sstate = TRACE_PCI_NVME_IDENTIFY_CTRL_CSI_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_CTRL_CSI_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_NS_EVENT = { .id = 0, .name = "pci_nvme_identify_ns", .sstate = TRACE_PCI_NVME_IDENTIFY_NS_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_NS_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_NS_IND_EVENT = { .id = 0, .name = "pci_nvme_identify_ns_ind", .sstate = TRACE_PCI_NVME_IDENTIFY_NS_IND_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_NS_IND_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_CTRL_LIST_EVENT = { .id = 0, .name = "pci_nvme_identify_ctrl_list", .sstate = TRACE_PCI_NVME_IDENTIFY_CTRL_LIST_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_CTRL_LIST_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_PRI_CTRL_CAP_EVENT = { .id = 0, .name = "pci_nvme_identify_pri_ctrl_cap", .sstate = TRACE_PCI_NVME_IDENTIFY_PRI_CTRL_CAP_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_PRI_CTRL_CAP_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_SEC_CTRL_LIST_EVENT = { .id = 0, .name = "pci_nvme_identify_sec_ctrl_list", .sstate = TRACE_PCI_NVME_IDENTIFY_SEC_CTRL_LIST_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_SEC_CTRL_LIST_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_NS_CSI_EVENT = { .id = 0, .name = "pci_nvme_identify_ns_csi", .sstate = TRACE_PCI_NVME_IDENTIFY_NS_CSI_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_NS_CSI_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_NSLIST_EVENT = { .id = 0, .name = "pci_nvme_identify_nslist", .sstate = TRACE_PCI_NVME_IDENTIFY_NSLIST_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_NSLIST_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_NSLIST_CSI_EVENT = { .id = 0, .name = "pci_nvme_identify_nslist_csi", .sstate = TRACE_PCI_NVME_IDENTIFY_NSLIST_CSI_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_NSLIST_CSI_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_CMD_SET_EVENT = { .id = 0, .name = "pci_nvme_identify_cmd_set", .sstate = TRACE_PCI_NVME_IDENTIFY_CMD_SET_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_CMD_SET_DSTATE }; TraceEvent _TRACE_PCI_NVME_IDENTIFY_NS_DESCR_LIST_EVENT = { .id = 0, .name = "pci_nvme_identify_ns_descr_list", .sstate = TRACE_PCI_NVME_IDENTIFY_NS_DESCR_LIST_ENABLED, .dstate = &_TRACE_PCI_NVME_IDENTIFY_NS_DESCR_LIST_DSTATE }; TraceEvent _TRACE_PCI_NVME_GET_LOG_EVENT = { .id = 0, .name = "pci_nvme_get_log", .sstate = TRACE_PCI_NVME_GET_LOG_ENABLED, .dstate = &_TRACE_PCI_NVME_GET_LOG_DSTATE }; TraceEvent _TRACE_PCI_NVME_GETFEAT_EVENT = { .id = 0, .name = "pci_nvme_getfeat", .sstate = TRACE_PCI_NVME_GETFEAT_ENABLED, .dstate = &_TRACE_PCI_NVME_GETFEAT_DSTATE }; TraceEvent _TRACE_PCI_NVME_SETFEAT_EVENT = { .id = 0, .name = "pci_nvme_setfeat", .sstate = TRACE_PCI_NVME_SETFEAT_ENABLED, .dstate = &_TRACE_PCI_NVME_SETFEAT_DSTATE }; TraceEvent _TRACE_PCI_NVME_GETFEAT_VWCACHE_EVENT = { .id = 0, .name = "pci_nvme_getfeat_vwcache", .sstate = TRACE_PCI_NVME_GETFEAT_VWCACHE_ENABLED, .dstate = &_TRACE_PCI_NVME_GETFEAT_VWCACHE_DSTATE }; TraceEvent _TRACE_PCI_NVME_GETFEAT_NUMQ_EVENT = { .id = 0, .name = "pci_nvme_getfeat_numq", .sstate = TRACE_PCI_NVME_GETFEAT_NUMQ_ENABLED, .dstate = &_TRACE_PCI_NVME_GETFEAT_NUMQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_SETFEAT_NUMQ_EVENT = { .id = 0, .name = "pci_nvme_setfeat_numq", .sstate = TRACE_PCI_NVME_SETFEAT_NUMQ_ENABLED, .dstate = &_TRACE_PCI_NVME_SETFEAT_NUMQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_SETFEAT_TIMESTAMP_EVENT = { .id = 0, .name = "pci_nvme_setfeat_timestamp", .sstate = TRACE_PCI_NVME_SETFEAT_TIMESTAMP_ENABLED, .dstate = &_TRACE_PCI_NVME_SETFEAT_TIMESTAMP_DSTATE }; TraceEvent _TRACE_PCI_NVME_GETFEAT_TIMESTAMP_EVENT = { .id = 0, .name = "pci_nvme_getfeat_timestamp", .sstate = TRACE_PCI_NVME_GETFEAT_TIMESTAMP_ENABLED, .dstate = &_TRACE_PCI_NVME_GETFEAT_TIMESTAMP_DSTATE }; TraceEvent _TRACE_PCI_NVME_PROCESS_AERS_EVENT = { .id = 0, .name = "pci_nvme_process_aers", .sstate = TRACE_PCI_NVME_PROCESS_AERS_ENABLED, .dstate = &_TRACE_PCI_NVME_PROCESS_AERS_DSTATE }; TraceEvent _TRACE_PCI_NVME_AER_EVENT = { .id = 0, .name = "pci_nvme_aer", .sstate = TRACE_PCI_NVME_AER_ENABLED, .dstate = &_TRACE_PCI_NVME_AER_DSTATE }; TraceEvent _TRACE_PCI_NVME_AER_AERL_EXCEEDED_EVENT = { .id = 0, .name = "pci_nvme_aer_aerl_exceeded", .sstate = TRACE_PCI_NVME_AER_AERL_EXCEEDED_ENABLED, .dstate = &_TRACE_PCI_NVME_AER_AERL_EXCEEDED_DSTATE }; TraceEvent _TRACE_PCI_NVME_AER_MASKED_EVENT = { .id = 0, .name = "pci_nvme_aer_masked", .sstate = TRACE_PCI_NVME_AER_MASKED_ENABLED, .dstate = &_TRACE_PCI_NVME_AER_MASKED_DSTATE }; TraceEvent _TRACE_PCI_NVME_AER_POST_CQE_EVENT = { .id = 0, .name = "pci_nvme_aer_post_cqe", .sstate = TRACE_PCI_NVME_AER_POST_CQE_ENABLED, .dstate = &_TRACE_PCI_NVME_AER_POST_CQE_DSTATE }; TraceEvent _TRACE_PCI_NVME_NS_ATTACHMENT_EVENT = { .id = 0, .name = "pci_nvme_ns_attachment", .sstate = TRACE_PCI_NVME_NS_ATTACHMENT_ENABLED, .dstate = &_TRACE_PCI_NVME_NS_ATTACHMENT_DSTATE }; TraceEvent _TRACE_PCI_NVME_NS_ATTACHMENT_ATTACH_EVENT = { .id = 0, .name = "pci_nvme_ns_attachment_attach", .sstate = TRACE_PCI_NVME_NS_ATTACHMENT_ATTACH_ENABLED, .dstate = &_TRACE_PCI_NVME_NS_ATTACHMENT_ATTACH_DSTATE }; TraceEvent _TRACE_PCI_NVME_ENQUEUE_EVENT_EVENT = { .id = 0, .name = "pci_nvme_enqueue_event", .sstate = TRACE_PCI_NVME_ENQUEUE_EVENT_ENABLED, .dstate = &_TRACE_PCI_NVME_ENQUEUE_EVENT_DSTATE }; TraceEvent _TRACE_PCI_NVME_ENQUEUE_EVENT_NOQUEUE_EVENT = { .id = 0, .name = "pci_nvme_enqueue_event_noqueue", .sstate = TRACE_PCI_NVME_ENQUEUE_EVENT_NOQUEUE_ENABLED, .dstate = &_TRACE_PCI_NVME_ENQUEUE_EVENT_NOQUEUE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ENQUEUE_EVENT_MASKED_EVENT = { .id = 0, .name = "pci_nvme_enqueue_event_masked", .sstate = TRACE_PCI_NVME_ENQUEUE_EVENT_MASKED_ENABLED, .dstate = &_TRACE_PCI_NVME_ENQUEUE_EVENT_MASKED_DSTATE }; TraceEvent _TRACE_PCI_NVME_NO_OUTSTANDING_AERS_EVENT = { .id = 0, .name = "pci_nvme_no_outstanding_aers", .sstate = TRACE_PCI_NVME_NO_OUTSTANDING_AERS_ENABLED, .dstate = &_TRACE_PCI_NVME_NO_OUTSTANDING_AERS_DSTATE }; TraceEvent _TRACE_PCI_NVME_ENQUEUE_REQ_COMPLETION_EVENT = { .id = 0, .name = "pci_nvme_enqueue_req_completion", .sstate = TRACE_PCI_NVME_ENQUEUE_REQ_COMPLETION_ENABLED, .dstate = &_TRACE_PCI_NVME_ENQUEUE_REQ_COMPLETION_DSTATE }; TraceEvent _TRACE_PCI_NVME_UPDATE_CQ_EVENTIDX_EVENT = { .id = 0, .name = "pci_nvme_update_cq_eventidx", .sstate = TRACE_PCI_NVME_UPDATE_CQ_EVENTIDX_ENABLED, .dstate = &_TRACE_PCI_NVME_UPDATE_CQ_EVENTIDX_DSTATE }; TraceEvent _TRACE_PCI_NVME_UPDATE_SQ_EVENTIDX_EVENT = { .id = 0, .name = "pci_nvme_update_sq_eventidx", .sstate = TRACE_PCI_NVME_UPDATE_SQ_EVENTIDX_ENABLED, .dstate = &_TRACE_PCI_NVME_UPDATE_SQ_EVENTIDX_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_READ_EVENT = { .id = 0, .name = "pci_nvme_mmio_read", .sstate = TRACE_PCI_NVME_MMIO_READ_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_READ_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_WRITE_EVENT = { .id = 0, .name = "pci_nvme_mmio_write", .sstate = TRACE_PCI_NVME_MMIO_WRITE_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_WRITE_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_DOORBELL_CQ_EVENT = { .id = 0, .name = "pci_nvme_mmio_doorbell_cq", .sstate = TRACE_PCI_NVME_MMIO_DOORBELL_CQ_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_DOORBELL_CQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_DOORBELL_SQ_EVENT = { .id = 0, .name = "pci_nvme_mmio_doorbell_sq", .sstate = TRACE_PCI_NVME_MMIO_DOORBELL_SQ_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_DOORBELL_SQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_INTM_SET_EVENT = { .id = 0, .name = "pci_nvme_mmio_intm_set", .sstate = TRACE_PCI_NVME_MMIO_INTM_SET_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_INTM_SET_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_INTM_CLR_EVENT = { .id = 0, .name = "pci_nvme_mmio_intm_clr", .sstate = TRACE_PCI_NVME_MMIO_INTM_CLR_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_INTM_CLR_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_CFG_EVENT = { .id = 0, .name = "pci_nvme_mmio_cfg", .sstate = TRACE_PCI_NVME_MMIO_CFG_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_CFG_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_AQATTR_EVENT = { .id = 0, .name = "pci_nvme_mmio_aqattr", .sstate = TRACE_PCI_NVME_MMIO_AQATTR_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_AQATTR_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_ASQADDR_EVENT = { .id = 0, .name = "pci_nvme_mmio_asqaddr", .sstate = TRACE_PCI_NVME_MMIO_ASQADDR_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_ASQADDR_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_ACQADDR_EVENT = { .id = 0, .name = "pci_nvme_mmio_acqaddr", .sstate = TRACE_PCI_NVME_MMIO_ACQADDR_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_ACQADDR_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_ASQADDR_HI_EVENT = { .id = 0, .name = "pci_nvme_mmio_asqaddr_hi", .sstate = TRACE_PCI_NVME_MMIO_ASQADDR_HI_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_ASQADDR_HI_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_ACQADDR_HI_EVENT = { .id = 0, .name = "pci_nvme_mmio_acqaddr_hi", .sstate = TRACE_PCI_NVME_MMIO_ACQADDR_HI_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_ACQADDR_HI_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_START_SUCCESS_EVENT = { .id = 0, .name = "pci_nvme_mmio_start_success", .sstate = TRACE_PCI_NVME_MMIO_START_SUCCESS_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_START_SUCCESS_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_STOPPED_EVENT = { .id = 0, .name = "pci_nvme_mmio_stopped", .sstate = TRACE_PCI_NVME_MMIO_STOPPED_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_STOPPED_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_SHUTDOWN_SET_EVENT = { .id = 0, .name = "pci_nvme_mmio_shutdown_set", .sstate = TRACE_PCI_NVME_MMIO_SHUTDOWN_SET_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_SHUTDOWN_SET_DSTATE }; TraceEvent _TRACE_PCI_NVME_MMIO_SHUTDOWN_CLEARED_EVENT = { .id = 0, .name = "pci_nvme_mmio_shutdown_cleared", .sstate = TRACE_PCI_NVME_MMIO_SHUTDOWN_CLEARED_ENABLED, .dstate = &_TRACE_PCI_NVME_MMIO_SHUTDOWN_CLEARED_DSTATE }; TraceEvent _TRACE_PCI_NVME_UPDATE_CQ_HEAD_EVENT = { .id = 0, .name = "pci_nvme_update_cq_head", .sstate = TRACE_PCI_NVME_UPDATE_CQ_HEAD_ENABLED, .dstate = &_TRACE_PCI_NVME_UPDATE_CQ_HEAD_DSTATE }; TraceEvent _TRACE_PCI_NVME_UPDATE_SQ_TAIL_EVENT = { .id = 0, .name = "pci_nvme_update_sq_tail", .sstate = TRACE_PCI_NVME_UPDATE_SQ_TAIL_ENABLED, .dstate = &_TRACE_PCI_NVME_UPDATE_SQ_TAIL_DSTATE }; TraceEvent _TRACE_PCI_NVME_OPEN_ZONE_EVENT = { .id = 0, .name = "pci_nvme_open_zone", .sstate = TRACE_PCI_NVME_OPEN_ZONE_ENABLED, .dstate = &_TRACE_PCI_NVME_OPEN_ZONE_DSTATE }; TraceEvent _TRACE_PCI_NVME_CLOSE_ZONE_EVENT = { .id = 0, .name = "pci_nvme_close_zone", .sstate = TRACE_PCI_NVME_CLOSE_ZONE_ENABLED, .dstate = &_TRACE_PCI_NVME_CLOSE_ZONE_DSTATE }; TraceEvent _TRACE_PCI_NVME_FINISH_ZONE_EVENT = { .id = 0, .name = "pci_nvme_finish_zone", .sstate = TRACE_PCI_NVME_FINISH_ZONE_ENABLED, .dstate = &_TRACE_PCI_NVME_FINISH_ZONE_DSTATE }; TraceEvent _TRACE_PCI_NVME_RESET_ZONE_EVENT = { .id = 0, .name = "pci_nvme_reset_zone", .sstate = TRACE_PCI_NVME_RESET_ZONE_ENABLED, .dstate = &_TRACE_PCI_NVME_RESET_ZONE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ZNS_ZONE_RESET_EVENT = { .id = 0, .name = "pci_nvme_zns_zone_reset", .sstate = TRACE_PCI_NVME_ZNS_ZONE_RESET_ENABLED, .dstate = &_TRACE_PCI_NVME_ZNS_ZONE_RESET_DSTATE }; TraceEvent _TRACE_PCI_NVME_OFFLINE_ZONE_EVENT = { .id = 0, .name = "pci_nvme_offline_zone", .sstate = TRACE_PCI_NVME_OFFLINE_ZONE_ENABLED, .dstate = &_TRACE_PCI_NVME_OFFLINE_ZONE_DSTATE }; TraceEvent _TRACE_PCI_NVME_SET_DESCRIPTOR_EXTENSION_EVENT = { .id = 0, .name = "pci_nvme_set_descriptor_extension", .sstate = TRACE_PCI_NVME_SET_DESCRIPTOR_EXTENSION_ENABLED, .dstate = &_TRACE_PCI_NVME_SET_DESCRIPTOR_EXTENSION_DSTATE }; TraceEvent _TRACE_PCI_NVME_ZD_EXTENSION_SET_EVENT = { .id = 0, .name = "pci_nvme_zd_extension_set", .sstate = TRACE_PCI_NVME_ZD_EXTENSION_SET_ENABLED, .dstate = &_TRACE_PCI_NVME_ZD_EXTENSION_SET_DSTATE }; TraceEvent _TRACE_PCI_NVME_CLEAR_NS_CLOSE_EVENT = { .id = 0, .name = "pci_nvme_clear_ns_close", .sstate = TRACE_PCI_NVME_CLEAR_NS_CLOSE_ENABLED, .dstate = &_TRACE_PCI_NVME_CLEAR_NS_CLOSE_DSTATE }; TraceEvent _TRACE_PCI_NVME_CLEAR_NS_RESET_EVENT = { .id = 0, .name = "pci_nvme_clear_ns_reset", .sstate = TRACE_PCI_NVME_CLEAR_NS_RESET_ENABLED, .dstate = &_TRACE_PCI_NVME_CLEAR_NS_RESET_DSTATE }; TraceEvent _TRACE_PCI_NVME_ZONED_ZRWA_IMPLICIT_FLUSH_EVENT = { .id = 0, .name = "pci_nvme_zoned_zrwa_implicit_flush", .sstate = TRACE_PCI_NVME_ZONED_ZRWA_IMPLICIT_FLUSH_ENABLED, .dstate = &_TRACE_PCI_NVME_ZONED_ZRWA_IMPLICIT_FLUSH_DSTATE }; TraceEvent _TRACE_PCI_NVME_PCI_RESET_EVENT = { .id = 0, .name = "pci_nvme_pci_reset", .sstate = TRACE_PCI_NVME_PCI_RESET_ENABLED, .dstate = &_TRACE_PCI_NVME_PCI_RESET_DSTATE }; TraceEvent _TRACE_PCI_NVME_VIRT_MNGMT_EVENT = { .id = 0, .name = "pci_nvme_virt_mngmt", .sstate = TRACE_PCI_NVME_VIRT_MNGMT_ENABLED, .dstate = &_TRACE_PCI_NVME_VIRT_MNGMT_DSTATE }; TraceEvent _TRACE_PCI_NVME_FDP_RUH_CHANGE_EVENT = { .id = 0, .name = "pci_nvme_fdp_ruh_change", .sstate = TRACE_PCI_NVME_FDP_RUH_CHANGE_ENABLED, .dstate = &_TRACE_PCI_NVME_FDP_RUH_CHANGE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_MDTS_EVENT = { .id = 0, .name = "pci_nvme_err_mdts", .sstate = TRACE_PCI_NVME_ERR_MDTS_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_MDTS_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_ZASL_EVENT = { .id = 0, .name = "pci_nvme_err_zasl", .sstate = TRACE_PCI_NVME_ERR_ZASL_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_ZASL_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_REQ_STATUS_EVENT = { .id = 0, .name = "pci_nvme_err_req_status", .sstate = TRACE_PCI_NVME_ERR_REQ_STATUS_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_REQ_STATUS_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_ADDR_READ_EVENT = { .id = 0, .name = "pci_nvme_err_addr_read", .sstate = TRACE_PCI_NVME_ERR_ADDR_READ_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_ADDR_READ_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_ADDR_WRITE_EVENT = { .id = 0, .name = "pci_nvme_err_addr_write", .sstate = TRACE_PCI_NVME_ERR_ADDR_WRITE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_ADDR_WRITE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_CFS_EVENT = { .id = 0, .name = "pci_nvme_err_cfs", .sstate = TRACE_PCI_NVME_ERR_CFS_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_CFS_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_AIO_EVENT = { .id = 0, .name = "pci_nvme_err_aio", .sstate = TRACE_PCI_NVME_ERR_AIO_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_AIO_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_COPY_INVALID_FORMAT_EVENT = { .id = 0, .name = "pci_nvme_err_copy_invalid_format", .sstate = TRACE_PCI_NVME_ERR_COPY_INVALID_FORMAT_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_COPY_INVALID_FORMAT_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_SGLD_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_sgld", .sstate = TRACE_PCI_NVME_ERR_INVALID_SGLD_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_SGLD_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_NUM_SGLD_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_num_sgld", .sstate = TRACE_PCI_NVME_ERR_INVALID_NUM_SGLD_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_NUM_SGLD_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_SGL_EXCESS_LENGTH_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_sgl_excess_length", .sstate = TRACE_PCI_NVME_ERR_INVALID_SGL_EXCESS_LENGTH_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_SGL_EXCESS_LENGTH_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_DMA_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_dma", .sstate = TRACE_PCI_NVME_ERR_INVALID_DMA_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_DMA_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_PRPLIST_ENT_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_prplist_ent", .sstate = TRACE_PCI_NVME_ERR_INVALID_PRPLIST_ENT_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_PRPLIST_ENT_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_PRP2_ALIGN_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_prp2_align", .sstate = TRACE_PCI_NVME_ERR_INVALID_PRP2_ALIGN_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_PRP2_ALIGN_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_OPC_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_opc", .sstate = TRACE_PCI_NVME_ERR_INVALID_OPC_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_OPC_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_ADMIN_OPC_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_admin_opc", .sstate = TRACE_PCI_NVME_ERR_INVALID_ADMIN_OPC_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_ADMIN_OPC_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_LBA_RANGE_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_lba_range", .sstate = TRACE_PCI_NVME_ERR_INVALID_LBA_RANGE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_LBA_RANGE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_OFFSET_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_log_page_offset", .sstate = TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_OFFSET_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_OFFSET_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_CMB_INVALID_CBA_EVENT = { .id = 0, .name = "pci_nvme_err_cmb_invalid_cba", .sstate = TRACE_PCI_NVME_ERR_CMB_INVALID_CBA_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_CMB_INVALID_CBA_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_CMB_NOT_ENABLED_EVENT = { .id = 0, .name = "pci_nvme_err_cmb_not_enabled", .sstate = TRACE_PCI_NVME_ERR_CMB_NOT_ENABLED_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_CMB_NOT_ENABLED_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_UNALIGNED_ZONE_CMD_EVENT = { .id = 0, .name = "pci_nvme_err_unaligned_zone_cmd", .sstate = TRACE_PCI_NVME_ERR_UNALIGNED_ZONE_CMD_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_UNALIGNED_ZONE_CMD_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_ZONE_STATE_TRANSITION_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_zone_state_transition", .sstate = TRACE_PCI_NVME_ERR_INVALID_ZONE_STATE_TRANSITION_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_ZONE_STATE_TRANSITION_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_WRITE_NOT_AT_WP_EVENT = { .id = 0, .name = "pci_nvme_err_write_not_at_wp", .sstate = TRACE_PCI_NVME_ERR_WRITE_NOT_AT_WP_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_WRITE_NOT_AT_WP_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_APPEND_NOT_AT_START_EVENT = { .id = 0, .name = "pci_nvme_err_append_not_at_start", .sstate = TRACE_PCI_NVME_ERR_APPEND_NOT_AT_START_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_APPEND_NOT_AT_START_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_ZONE_IS_FULL_EVENT = { .id = 0, .name = "pci_nvme_err_zone_is_full", .sstate = TRACE_PCI_NVME_ERR_ZONE_IS_FULL_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_ZONE_IS_FULL_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_ZONE_IS_READ_ONLY_EVENT = { .id = 0, .name = "pci_nvme_err_zone_is_read_only", .sstate = TRACE_PCI_NVME_ERR_ZONE_IS_READ_ONLY_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_ZONE_IS_READ_ONLY_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_ZONE_IS_OFFLINE_EVENT = { .id = 0, .name = "pci_nvme_err_zone_is_offline", .sstate = TRACE_PCI_NVME_ERR_ZONE_IS_OFFLINE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_ZONE_IS_OFFLINE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_ZONE_BOUNDARY_EVENT = { .id = 0, .name = "pci_nvme_err_zone_boundary", .sstate = TRACE_PCI_NVME_ERR_ZONE_BOUNDARY_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_ZONE_BOUNDARY_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_ZONE_INVALID_WRITE_EVENT = { .id = 0, .name = "pci_nvme_err_zone_invalid_write", .sstate = TRACE_PCI_NVME_ERR_ZONE_INVALID_WRITE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_ZONE_INVALID_WRITE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_ZONE_WRITE_NOT_OK_EVENT = { .id = 0, .name = "pci_nvme_err_zone_write_not_ok", .sstate = TRACE_PCI_NVME_ERR_ZONE_WRITE_NOT_OK_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_ZONE_WRITE_NOT_OK_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_ZONE_READ_NOT_OK_EVENT = { .id = 0, .name = "pci_nvme_err_zone_read_not_ok", .sstate = TRACE_PCI_NVME_ERR_ZONE_READ_NOT_OK_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_ZONE_READ_NOT_OK_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INSUFF_ACTIVE_RES_EVENT = { .id = 0, .name = "pci_nvme_err_insuff_active_res", .sstate = TRACE_PCI_NVME_ERR_INSUFF_ACTIVE_RES_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INSUFF_ACTIVE_RES_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INSUFF_OPEN_RES_EVENT = { .id = 0, .name = "pci_nvme_err_insuff_open_res", .sstate = TRACE_PCI_NVME_ERR_INSUFF_OPEN_RES_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INSUFF_OPEN_RES_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_ZD_EXTENSION_MAP_ERROR_EVENT = { .id = 0, .name = "pci_nvme_err_zd_extension_map_error", .sstate = TRACE_PCI_NVME_ERR_ZD_EXTENSION_MAP_ERROR_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_ZD_EXTENSION_MAP_ERROR_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_IOCSCI_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_iocsci", .sstate = TRACE_PCI_NVME_ERR_INVALID_IOCSCI_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_IOCSCI_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_DEL_SQ_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_del_sq", .sstate = TRACE_PCI_NVME_ERR_INVALID_DEL_SQ_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_DEL_SQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_CQID_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_create_sq_cqid", .sstate = TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_CQID_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_CQID_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SQID_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_create_sq_sqid", .sstate = TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SQID_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SQID_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SIZE_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_create_sq_size", .sstate = TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SIZE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SIZE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_ADDR_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_create_sq_addr", .sstate = TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_ADDR_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_ADDR_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_QFLAGS_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_create_sq_qflags", .sstate = TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_QFLAGS_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_QFLAGS_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_CQID_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_del_cq_cqid", .sstate = TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_CQID_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_CQID_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_NOTEMPTY_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_del_cq_notempty", .sstate = TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_NOTEMPTY_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_NOTEMPTY_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_CQID_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_create_cq_cqid", .sstate = TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_CQID_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_CQID_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_SIZE_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_create_cq_size", .sstate = TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_SIZE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_SIZE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ADDR_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_create_cq_addr", .sstate = TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ADDR_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ADDR_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_VECTOR_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_create_cq_vector", .sstate = TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_VECTOR_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_VECTOR_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_QFLAGS_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_create_cq_qflags", .sstate = TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_QFLAGS_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_QFLAGS_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ENTRY_SIZE_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_create_cq_entry_size", .sstate = TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ENTRY_SIZE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ENTRY_SIZE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_IDENTIFY_CNS_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_identify_cns", .sstate = TRACE_PCI_NVME_ERR_INVALID_IDENTIFY_CNS_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_IDENTIFY_CNS_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_GETFEAT_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_getfeat", .sstate = TRACE_PCI_NVME_ERR_INVALID_GETFEAT_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_GETFEAT_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_SETFEAT_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_setfeat", .sstate = TRACE_PCI_NVME_ERR_INVALID_SETFEAT_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_SETFEAT_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_log_page", .sstate = TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_CQ_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_cq", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_CQ_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_CQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_SQ_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_sq", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_SQ_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_SQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_ASQ_MISALIGNED_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_asq_misaligned", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_ASQ_MISALIGNED_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_ASQ_MISALIGNED_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_ACQ_MISALIGNED_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_acq_misaligned", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_ACQ_MISALIGNED_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_ACQ_MISALIGNED_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_SMALL_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_page_too_small", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_SMALL_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_SMALL_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_LARGE_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_page_too_large", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_LARGE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_LARGE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_SMALL_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_cqent_too_small", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_SMALL_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_SMALL_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_LARGE_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_cqent_too_large", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_LARGE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_LARGE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_SMALL_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_sqent_too_small", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_SMALL_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_SMALL_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_LARGE_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_sqent_too_large", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_LARGE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_LARGE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_CSS_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_css", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_CSS_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_CSS_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_ASQENT_SZ_ZERO_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_asqent_sz_zero", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_ASQENT_SZ_ZERO_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_ASQENT_SZ_ZERO_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_ACQENT_SZ_ZERO_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_acqent_sz_zero", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_ACQENT_SZ_ZERO_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_ACQENT_SZ_ZERO_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_ZASL_TOO_SMALL_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_zasl_too_small", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_ZASL_TOO_SMALL_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_ZASL_TOO_SMALL_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_EVENT = { .id = 0, .name = "pci_nvme_err_startfail", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_STARTFAIL_VIRT_STATE_EVENT = { .id = 0, .name = "pci_nvme_err_startfail_virt_state", .sstate = TRACE_PCI_NVME_ERR_STARTFAIL_VIRT_STATE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_STARTFAIL_VIRT_STATE_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_INVALID_MGMT_ACTION_EVENT = { .id = 0, .name = "pci_nvme_err_invalid_mgmt_action", .sstate = TRACE_PCI_NVME_ERR_INVALID_MGMT_ACTION_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_INVALID_MGMT_ACTION_DSTATE }; TraceEvent _TRACE_PCI_NVME_ERR_IGNORED_MMIO_VF_OFFLINE_EVENT = { .id = 0, .name = "pci_nvme_err_ignored_mmio_vf_offline", .sstate = TRACE_PCI_NVME_ERR_IGNORED_MMIO_VF_OFFLINE_ENABLED, .dstate = &_TRACE_PCI_NVME_ERR_IGNORED_MMIO_VF_OFFLINE_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_MISALIGNED32_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_misaligned32", .sstate = TRACE_PCI_NVME_UB_MMIOWR_MISALIGNED32_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_MISALIGNED32_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_TOOSMALL_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_toosmall", .sstate = TRACE_PCI_NVME_UB_MMIOWR_TOOSMALL_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_TOOSMALL_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_INTMASK_WITH_MSIX_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_intmask_with_msix", .sstate = TRACE_PCI_NVME_UB_MMIOWR_INTMASK_WITH_MSIX_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_INTMASK_WITH_MSIX_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_RO_CSTS_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_ro_csts", .sstate = TRACE_PCI_NVME_UB_MMIOWR_RO_CSTS_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_RO_CSTS_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_SSRESET_W1C_UNSUPPORTED_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_ssreset_w1c_unsupported", .sstate = TRACE_PCI_NVME_UB_MMIOWR_SSRESET_W1C_UNSUPPORTED_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_SSRESET_W1C_UNSUPPORTED_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_SSRESET_UNSUPPORTED_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_ssreset_unsupported", .sstate = TRACE_PCI_NVME_UB_MMIOWR_SSRESET_UNSUPPORTED_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_SSRESET_UNSUPPORTED_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_CMBLOC_RESERVED_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_cmbloc_reserved", .sstate = TRACE_PCI_NVME_UB_MMIOWR_CMBLOC_RESERVED_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_CMBLOC_RESERVED_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_CMBSZ_READONLY_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_cmbsz_readonly", .sstate = TRACE_PCI_NVME_UB_MMIOWR_CMBSZ_READONLY_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_CMBSZ_READONLY_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_PMRCAP_READONLY_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_pmrcap_readonly", .sstate = TRACE_PCI_NVME_UB_MMIOWR_PMRCAP_READONLY_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_PMRCAP_READONLY_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_PMRSTS_READONLY_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_pmrsts_readonly", .sstate = TRACE_PCI_NVME_UB_MMIOWR_PMRSTS_READONLY_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_PMRSTS_READONLY_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_PMREBS_READONLY_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_pmrebs_readonly", .sstate = TRACE_PCI_NVME_UB_MMIOWR_PMREBS_READONLY_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_PMREBS_READONLY_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_PMRSWTP_READONLY_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_pmrswtp_readonly", .sstate = TRACE_PCI_NVME_UB_MMIOWR_PMRSWTP_READONLY_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_PMRSWTP_READONLY_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIOWR_INVALID_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiowr_invalid", .sstate = TRACE_PCI_NVME_UB_MMIOWR_INVALID_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIOWR_INVALID_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIORD_MISALIGNED32_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiord_misaligned32", .sstate = TRACE_PCI_NVME_UB_MMIORD_MISALIGNED32_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIORD_MISALIGNED32_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIORD_TOOSMALL_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiord_toosmall", .sstate = TRACE_PCI_NVME_UB_MMIORD_TOOSMALL_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIORD_TOOSMALL_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_MMIORD_INVALID_OFS_EVENT = { .id = 0, .name = "pci_nvme_ub_mmiord_invalid_ofs", .sstate = TRACE_PCI_NVME_UB_MMIORD_INVALID_OFS_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_MMIORD_INVALID_OFS_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_DB_WR_MISALIGNED_EVENT = { .id = 0, .name = "pci_nvme_ub_db_wr_misaligned", .sstate = TRACE_PCI_NVME_UB_DB_WR_MISALIGNED_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_DB_WR_MISALIGNED_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_DB_WR_INVALID_CQ_EVENT = { .id = 0, .name = "pci_nvme_ub_db_wr_invalid_cq", .sstate = TRACE_PCI_NVME_UB_DB_WR_INVALID_CQ_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_DB_WR_INVALID_CQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_DB_WR_INVALID_CQHEAD_EVENT = { .id = 0, .name = "pci_nvme_ub_db_wr_invalid_cqhead", .sstate = TRACE_PCI_NVME_UB_DB_WR_INVALID_CQHEAD_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_DB_WR_INVALID_CQHEAD_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_DB_WR_INVALID_SQ_EVENT = { .id = 0, .name = "pci_nvme_ub_db_wr_invalid_sq", .sstate = TRACE_PCI_NVME_UB_DB_WR_INVALID_SQ_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_DB_WR_INVALID_SQ_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_DB_WR_INVALID_SQTAIL_EVENT = { .id = 0, .name = "pci_nvme_ub_db_wr_invalid_sqtail", .sstate = TRACE_PCI_NVME_UB_DB_WR_INVALID_SQTAIL_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_DB_WR_INVALID_SQTAIL_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_UNKNOWN_CSS_VALUE_EVENT = { .id = 0, .name = "pci_nvme_ub_unknown_css_value", .sstate = TRACE_PCI_NVME_UB_UNKNOWN_CSS_VALUE_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_UNKNOWN_CSS_VALUE_DSTATE }; TraceEvent _TRACE_PCI_NVME_UB_TOO_MANY_MAPPINGS_EVENT = { .id = 0, .name = "pci_nvme_ub_too_many_mappings", .sstate = TRACE_PCI_NVME_UB_TOO_MANY_MAPPINGS_ENABLED, .dstate = &_TRACE_PCI_NVME_UB_TOO_MANY_MAPPINGS_DSTATE }; TraceEvent *hw_nvme_trace_events[] = { &_TRACE_PCI_NVME_IRQ_MSIX_EVENT, &_TRACE_PCI_NVME_IRQ_PIN_EVENT, &_TRACE_PCI_NVME_IRQ_MASKED_EVENT, &_TRACE_PCI_NVME_DMA_READ_EVENT, &_TRACE_PCI_NVME_DBBUF_CONFIG_EVENT, &_TRACE_PCI_NVME_MAP_ADDR_EVENT, &_TRACE_PCI_NVME_MAP_ADDR_CMB_EVENT, &_TRACE_PCI_NVME_MAP_PRP_EVENT, &_TRACE_PCI_NVME_MAP_SGL_EVENT, &_TRACE_PCI_NVME_IO_CMD_EVENT, &_TRACE_PCI_NVME_ADMIN_CMD_EVENT, &_TRACE_PCI_NVME_FLUSH_NS_EVENT, &_TRACE_PCI_NVME_FORMAT_SET_EVENT, &_TRACE_PCI_NVME_READ_EVENT, &_TRACE_PCI_NVME_WRITE_EVENT, &_TRACE_PCI_NVME_RW_CB_EVENT, &_TRACE_PCI_NVME_MISC_CB_EVENT, &_TRACE_PCI_NVME_DIF_RW_EVENT, &_TRACE_PCI_NVME_DIF_RW_CB_EVENT, &_TRACE_PCI_NVME_DIF_RW_MDATA_IN_CB_EVENT, &_TRACE_PCI_NVME_DIF_RW_MDATA_OUT_CB_EVENT, &_TRACE_PCI_NVME_DIF_RW_CHECK_CB_EVENT, &_TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC16_EVENT, &_TRACE_PCI_NVME_DIF_PRACT_GENERATE_DIF_CRC64_EVENT, &_TRACE_PCI_NVME_DIF_CHECK_EVENT, &_TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC16_EVENT, &_TRACE_PCI_NVME_DIF_PRCHK_DISABLED_CRC64_EVENT, &_TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC16_EVENT, &_TRACE_PCI_NVME_DIF_PRCHK_GUARD_CRC64_EVENT, &_TRACE_PCI_NVME_DIF_PRCHK_APPTAG_EVENT, &_TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC16_EVENT, &_TRACE_PCI_NVME_DIF_PRCHK_REFTAG_CRC64_EVENT, &_TRACE_PCI_NVME_COPY_EVENT, &_TRACE_PCI_NVME_COPY_SOURCE_RANGE_EVENT, &_TRACE_PCI_NVME_COPY_OUT_EVENT, &_TRACE_PCI_NVME_VERIFY_EVENT, &_TRACE_PCI_NVME_VERIFY_MDATA_IN_CB_EVENT, &_TRACE_PCI_NVME_VERIFY_CB_EVENT, &_TRACE_PCI_NVME_RW_COMPLETE_CB_EVENT, &_TRACE_PCI_NVME_BLOCK_STATUS_EVENT, &_TRACE_PCI_NVME_DSM_EVENT, &_TRACE_PCI_NVME_DSM_DEALLOCATE_EVENT, &_TRACE_PCI_NVME_DSM_SINGLE_RANGE_LIMIT_EXCEEDED_EVENT, &_TRACE_PCI_NVME_COMPARE_EVENT, &_TRACE_PCI_NVME_COMPARE_DATA_CB_EVENT, &_TRACE_PCI_NVME_COMPARE_MDATA_CB_EVENT, &_TRACE_PCI_NVME_AIO_DISCARD_CB_EVENT, &_TRACE_PCI_NVME_AIO_COPY_IN_CB_EVENT, &_TRACE_PCI_NVME_AIO_FLUSH_CB_EVENT, &_TRACE_PCI_NVME_CREATE_SQ_EVENT, &_TRACE_PCI_NVME_CREATE_CQ_EVENT, &_TRACE_PCI_NVME_DEL_SQ_EVENT, &_TRACE_PCI_NVME_DEL_CQ_EVENT, &_TRACE_PCI_NVME_IDENTIFY_EVENT, &_TRACE_PCI_NVME_IDENTIFY_CTRL_EVENT, &_TRACE_PCI_NVME_IDENTIFY_CTRL_CSI_EVENT, &_TRACE_PCI_NVME_IDENTIFY_NS_EVENT, &_TRACE_PCI_NVME_IDENTIFY_NS_IND_EVENT, &_TRACE_PCI_NVME_IDENTIFY_CTRL_LIST_EVENT, &_TRACE_PCI_NVME_IDENTIFY_PRI_CTRL_CAP_EVENT, &_TRACE_PCI_NVME_IDENTIFY_SEC_CTRL_LIST_EVENT, &_TRACE_PCI_NVME_IDENTIFY_NS_CSI_EVENT, &_TRACE_PCI_NVME_IDENTIFY_NSLIST_EVENT, &_TRACE_PCI_NVME_IDENTIFY_NSLIST_CSI_EVENT, &_TRACE_PCI_NVME_IDENTIFY_CMD_SET_EVENT, &_TRACE_PCI_NVME_IDENTIFY_NS_DESCR_LIST_EVENT, &_TRACE_PCI_NVME_GET_LOG_EVENT, &_TRACE_PCI_NVME_GETFEAT_EVENT, &_TRACE_PCI_NVME_SETFEAT_EVENT, &_TRACE_PCI_NVME_GETFEAT_VWCACHE_EVENT, &_TRACE_PCI_NVME_GETFEAT_NUMQ_EVENT, &_TRACE_PCI_NVME_SETFEAT_NUMQ_EVENT, &_TRACE_PCI_NVME_SETFEAT_TIMESTAMP_EVENT, &_TRACE_PCI_NVME_GETFEAT_TIMESTAMP_EVENT, &_TRACE_PCI_NVME_PROCESS_AERS_EVENT, &_TRACE_PCI_NVME_AER_EVENT, &_TRACE_PCI_NVME_AER_AERL_EXCEEDED_EVENT, &_TRACE_PCI_NVME_AER_MASKED_EVENT, &_TRACE_PCI_NVME_AER_POST_CQE_EVENT, &_TRACE_PCI_NVME_NS_ATTACHMENT_EVENT, &_TRACE_PCI_NVME_NS_ATTACHMENT_ATTACH_EVENT, &_TRACE_PCI_NVME_ENQUEUE_EVENT_EVENT, &_TRACE_PCI_NVME_ENQUEUE_EVENT_NOQUEUE_EVENT, &_TRACE_PCI_NVME_ENQUEUE_EVENT_MASKED_EVENT, &_TRACE_PCI_NVME_NO_OUTSTANDING_AERS_EVENT, &_TRACE_PCI_NVME_ENQUEUE_REQ_COMPLETION_EVENT, &_TRACE_PCI_NVME_UPDATE_CQ_EVENTIDX_EVENT, &_TRACE_PCI_NVME_UPDATE_SQ_EVENTIDX_EVENT, &_TRACE_PCI_NVME_MMIO_READ_EVENT, &_TRACE_PCI_NVME_MMIO_WRITE_EVENT, &_TRACE_PCI_NVME_MMIO_DOORBELL_CQ_EVENT, &_TRACE_PCI_NVME_MMIO_DOORBELL_SQ_EVENT, &_TRACE_PCI_NVME_MMIO_INTM_SET_EVENT, &_TRACE_PCI_NVME_MMIO_INTM_CLR_EVENT, &_TRACE_PCI_NVME_MMIO_CFG_EVENT, &_TRACE_PCI_NVME_MMIO_AQATTR_EVENT, &_TRACE_PCI_NVME_MMIO_ASQADDR_EVENT, &_TRACE_PCI_NVME_MMIO_ACQADDR_EVENT, &_TRACE_PCI_NVME_MMIO_ASQADDR_HI_EVENT, &_TRACE_PCI_NVME_MMIO_ACQADDR_HI_EVENT, &_TRACE_PCI_NVME_MMIO_START_SUCCESS_EVENT, &_TRACE_PCI_NVME_MMIO_STOPPED_EVENT, &_TRACE_PCI_NVME_MMIO_SHUTDOWN_SET_EVENT, &_TRACE_PCI_NVME_MMIO_SHUTDOWN_CLEARED_EVENT, &_TRACE_PCI_NVME_UPDATE_CQ_HEAD_EVENT, &_TRACE_PCI_NVME_UPDATE_SQ_TAIL_EVENT, &_TRACE_PCI_NVME_OPEN_ZONE_EVENT, &_TRACE_PCI_NVME_CLOSE_ZONE_EVENT, &_TRACE_PCI_NVME_FINISH_ZONE_EVENT, &_TRACE_PCI_NVME_RESET_ZONE_EVENT, &_TRACE_PCI_NVME_ZNS_ZONE_RESET_EVENT, &_TRACE_PCI_NVME_OFFLINE_ZONE_EVENT, &_TRACE_PCI_NVME_SET_DESCRIPTOR_EXTENSION_EVENT, &_TRACE_PCI_NVME_ZD_EXTENSION_SET_EVENT, &_TRACE_PCI_NVME_CLEAR_NS_CLOSE_EVENT, &_TRACE_PCI_NVME_CLEAR_NS_RESET_EVENT, &_TRACE_PCI_NVME_ZONED_ZRWA_IMPLICIT_FLUSH_EVENT, &_TRACE_PCI_NVME_PCI_RESET_EVENT, &_TRACE_PCI_NVME_VIRT_MNGMT_EVENT, &_TRACE_PCI_NVME_FDP_RUH_CHANGE_EVENT, &_TRACE_PCI_NVME_ERR_MDTS_EVENT, &_TRACE_PCI_NVME_ERR_ZASL_EVENT, &_TRACE_PCI_NVME_ERR_REQ_STATUS_EVENT, &_TRACE_PCI_NVME_ERR_ADDR_READ_EVENT, &_TRACE_PCI_NVME_ERR_ADDR_WRITE_EVENT, &_TRACE_PCI_NVME_ERR_CFS_EVENT, &_TRACE_PCI_NVME_ERR_AIO_EVENT, &_TRACE_PCI_NVME_ERR_COPY_INVALID_FORMAT_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_SGLD_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_NUM_SGLD_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_SGL_EXCESS_LENGTH_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_DMA_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_PRPLIST_ENT_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_PRP2_ALIGN_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_OPC_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_ADMIN_OPC_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_LBA_RANGE_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_OFFSET_EVENT, &_TRACE_PCI_NVME_ERR_CMB_INVALID_CBA_EVENT, &_TRACE_PCI_NVME_ERR_CMB_NOT_ENABLED_EVENT, &_TRACE_PCI_NVME_ERR_UNALIGNED_ZONE_CMD_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_ZONE_STATE_TRANSITION_EVENT, &_TRACE_PCI_NVME_ERR_WRITE_NOT_AT_WP_EVENT, &_TRACE_PCI_NVME_ERR_APPEND_NOT_AT_START_EVENT, &_TRACE_PCI_NVME_ERR_ZONE_IS_FULL_EVENT, &_TRACE_PCI_NVME_ERR_ZONE_IS_READ_ONLY_EVENT, &_TRACE_PCI_NVME_ERR_ZONE_IS_OFFLINE_EVENT, &_TRACE_PCI_NVME_ERR_ZONE_BOUNDARY_EVENT, &_TRACE_PCI_NVME_ERR_ZONE_INVALID_WRITE_EVENT, &_TRACE_PCI_NVME_ERR_ZONE_WRITE_NOT_OK_EVENT, &_TRACE_PCI_NVME_ERR_ZONE_READ_NOT_OK_EVENT, &_TRACE_PCI_NVME_ERR_INSUFF_ACTIVE_RES_EVENT, &_TRACE_PCI_NVME_ERR_INSUFF_OPEN_RES_EVENT, &_TRACE_PCI_NVME_ERR_ZD_EXTENSION_MAP_ERROR_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_IOCSCI_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_DEL_SQ_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_CQID_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SQID_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_SIZE_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_ADDR_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_CREATE_SQ_QFLAGS_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_CQID_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_DEL_CQ_NOTEMPTY_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_CQID_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_SIZE_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ADDR_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_VECTOR_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_QFLAGS_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_CREATE_CQ_ENTRY_SIZE_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_IDENTIFY_CNS_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_GETFEAT_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_SETFEAT_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_LOG_PAGE_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_CQ_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_SQ_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_ASQ_MISALIGNED_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_ACQ_MISALIGNED_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_SMALL_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_PAGE_TOO_LARGE_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_SMALL_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_CQENT_TOO_LARGE_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_SMALL_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_SQENT_TOO_LARGE_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_CSS_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_ASQENT_SZ_ZERO_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_ACQENT_SZ_ZERO_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_ZASL_TOO_SMALL_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_EVENT, &_TRACE_PCI_NVME_ERR_STARTFAIL_VIRT_STATE_EVENT, &_TRACE_PCI_NVME_ERR_INVALID_MGMT_ACTION_EVENT, &_TRACE_PCI_NVME_ERR_IGNORED_MMIO_VF_OFFLINE_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_MISALIGNED32_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_TOOSMALL_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_INTMASK_WITH_MSIX_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_RO_CSTS_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_SSRESET_W1C_UNSUPPORTED_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_SSRESET_UNSUPPORTED_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_CMBLOC_RESERVED_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_CMBSZ_READONLY_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_PMRCAP_READONLY_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_PMRSTS_READONLY_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_PMREBS_READONLY_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_PMRSWTP_READONLY_EVENT, &_TRACE_PCI_NVME_UB_MMIOWR_INVALID_EVENT, &_TRACE_PCI_NVME_UB_MMIORD_MISALIGNED32_EVENT, &_TRACE_PCI_NVME_UB_MMIORD_TOOSMALL_EVENT, &_TRACE_PCI_NVME_UB_MMIORD_INVALID_OFS_EVENT, &_TRACE_PCI_NVME_UB_DB_WR_MISALIGNED_EVENT, &_TRACE_PCI_NVME_UB_DB_WR_INVALID_CQ_EVENT, &_TRACE_PCI_NVME_UB_DB_WR_INVALID_CQHEAD_EVENT, &_TRACE_PCI_NVME_UB_DB_WR_INVALID_SQ_EVENT, &_TRACE_PCI_NVME_UB_DB_WR_INVALID_SQTAIL_EVENT, &_TRACE_PCI_NVME_UB_UNKNOWN_CSS_VALUE_EVENT, &_TRACE_PCI_NVME_UB_TOO_MANY_MAPPINGS_EVENT, NULL, }; static void trace_hw_nvme_register_events(void) { trace_event_register_group(hw_nvme_trace_events); } trace_init(trace_hw_nvme_register_events)