/* This file is autogenerated by tracetool, do not edit. */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_pci.h"

uint16_t _TRACE_PCI_UPDATE_MAPPINGS_DEL_DSTATE;
uint16_t _TRACE_PCI_UPDATE_MAPPINGS_ADD_DSTATE;
uint16_t _TRACE_PCI_ROUTE_IRQ_DSTATE;
uint16_t _TRACE_PCI_CFG_READ_DSTATE;
uint16_t _TRACE_PCI_CFG_WRITE_DSTATE;
uint16_t _TRACE_MSIX_WRITE_CONFIG_DSTATE;
uint16_t _TRACE_SRIOV_REGISTER_VFS_DSTATE;
uint16_t _TRACE_SRIOV_UNREGISTER_VFS_DSTATE;
uint16_t _TRACE_SRIOV_CONFIG_WRITE_DSTATE;
uint16_t _TRACE_PCIE_CAP_SLOT_WRITE_CONFIG_DSTATE;
uint16_t _TRACE_SHPC_SLOT_COMMAND_DSTATE;
TraceEvent _TRACE_PCI_UPDATE_MAPPINGS_DEL_EVENT = {
    .id = 0,
    .name = "pci_update_mappings_del",
    .sstate = TRACE_PCI_UPDATE_MAPPINGS_DEL_ENABLED,
    .dstate = &_TRACE_PCI_UPDATE_MAPPINGS_DEL_DSTATE 
};
TraceEvent _TRACE_PCI_UPDATE_MAPPINGS_ADD_EVENT = {
    .id = 0,
    .name = "pci_update_mappings_add",
    .sstate = TRACE_PCI_UPDATE_MAPPINGS_ADD_ENABLED,
    .dstate = &_TRACE_PCI_UPDATE_MAPPINGS_ADD_DSTATE 
};
TraceEvent _TRACE_PCI_ROUTE_IRQ_EVENT = {
    .id = 0,
    .name = "pci_route_irq",
    .sstate = TRACE_PCI_ROUTE_IRQ_ENABLED,
    .dstate = &_TRACE_PCI_ROUTE_IRQ_DSTATE 
};
TraceEvent _TRACE_PCI_CFG_READ_EVENT = {
    .id = 0,
    .name = "pci_cfg_read",
    .sstate = TRACE_PCI_CFG_READ_ENABLED,
    .dstate = &_TRACE_PCI_CFG_READ_DSTATE 
};
TraceEvent _TRACE_PCI_CFG_WRITE_EVENT = {
    .id = 0,
    .name = "pci_cfg_write",
    .sstate = TRACE_PCI_CFG_WRITE_ENABLED,
    .dstate = &_TRACE_PCI_CFG_WRITE_DSTATE 
};
TraceEvent _TRACE_MSIX_WRITE_CONFIG_EVENT = {
    .id = 0,
    .name = "msix_write_config",
    .sstate = TRACE_MSIX_WRITE_CONFIG_ENABLED,
    .dstate = &_TRACE_MSIX_WRITE_CONFIG_DSTATE 
};
TraceEvent _TRACE_SRIOV_REGISTER_VFS_EVENT = {
    .id = 0,
    .name = "sriov_register_vfs",
    .sstate = TRACE_SRIOV_REGISTER_VFS_ENABLED,
    .dstate = &_TRACE_SRIOV_REGISTER_VFS_DSTATE 
};
TraceEvent _TRACE_SRIOV_UNREGISTER_VFS_EVENT = {
    .id = 0,
    .name = "sriov_unregister_vfs",
    .sstate = TRACE_SRIOV_UNREGISTER_VFS_ENABLED,
    .dstate = &_TRACE_SRIOV_UNREGISTER_VFS_DSTATE 
};
TraceEvent _TRACE_SRIOV_CONFIG_WRITE_EVENT = {
    .id = 0,
    .name = "sriov_config_write",
    .sstate = TRACE_SRIOV_CONFIG_WRITE_ENABLED,
    .dstate = &_TRACE_SRIOV_CONFIG_WRITE_DSTATE 
};
TraceEvent _TRACE_PCIE_CAP_SLOT_WRITE_CONFIG_EVENT = {
    .id = 0,
    .name = "pcie_cap_slot_write_config",
    .sstate = TRACE_PCIE_CAP_SLOT_WRITE_CONFIG_ENABLED,
    .dstate = &_TRACE_PCIE_CAP_SLOT_WRITE_CONFIG_DSTATE 
};
TraceEvent _TRACE_SHPC_SLOT_COMMAND_EVENT = {
    .id = 0,
    .name = "shpc_slot_command",
    .sstate = TRACE_SHPC_SLOT_COMMAND_ENABLED,
    .dstate = &_TRACE_SHPC_SLOT_COMMAND_DSTATE 
};
TraceEvent *hw_pci_trace_events[] = {
    &_TRACE_PCI_UPDATE_MAPPINGS_DEL_EVENT,
    &_TRACE_PCI_UPDATE_MAPPINGS_ADD_EVENT,
    &_TRACE_PCI_ROUTE_IRQ_EVENT,
    &_TRACE_PCI_CFG_READ_EVENT,
    &_TRACE_PCI_CFG_WRITE_EVENT,
    &_TRACE_MSIX_WRITE_CONFIG_EVENT,
    &_TRACE_SRIOV_REGISTER_VFS_EVENT,
    &_TRACE_SRIOV_UNREGISTER_VFS_EVENT,
    &_TRACE_SRIOV_CONFIG_WRITE_EVENT,
    &_TRACE_PCIE_CAP_SLOT_WRITE_CONFIG_EVENT,
    &_TRACE_SHPC_SLOT_COMMAND_EVENT,
  NULL,
};

static void trace_hw_pci_register_events(void)
{
    trace_event_register_group(hw_pci_trace_events);
}
trace_init(trace_hw_pci_register_events)