/* This file is autogenerated by tracetool, do not edit. */

#ifndef TRACE_HW_PCI_HOST_GENERATED_TRACERS_H
#define TRACE_HW_PCI_HOST_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_BONITO_SPCICONF_SMALL_ACCESS_EVENT;
extern TraceEvent _TRACE_GRACKLE_SET_IRQ_EVENT;
extern TraceEvent _TRACE_GT64120_READ_EVENT;
extern TraceEvent _TRACE_GT64120_WRITE_EVENT;
extern TraceEvent _TRACE_GT64120_READ_INTREG_EVENT;
extern TraceEvent _TRACE_GT64120_WRITE_INTREG_EVENT;
extern TraceEvent _TRACE_GT64120_ISD_REMAP_EVENT;
extern TraceEvent _TRACE_MV64361_REGION_MAP_EVENT;
extern TraceEvent _TRACE_MV64361_REGION_ENABLE_EVENT;
extern TraceEvent _TRACE_MV64361_REG_READ_EVENT;
extern TraceEvent _TRACE_MV64361_REG_WRITE_EVENT;
extern TraceEvent _TRACE_SABRE_SET_REQUEST_EVENT;
extern TraceEvent _TRACE_SABRE_CLEAR_REQUEST_EVENT;
extern TraceEvent _TRACE_SABRE_CONFIG_WRITE_EVENT;
extern TraceEvent _TRACE_SABRE_CONFIG_READ_EVENT;
extern TraceEvent _TRACE_SABRE_PCI_CONFIG_WRITE_EVENT;
extern TraceEvent _TRACE_SABRE_PCI_CONFIG_READ_EVENT;
extern TraceEvent _TRACE_SABRE_PCI_SET_IRQ_EVENT;
extern TraceEvent _TRACE_SABRE_PCI_SET_OBIO_IRQ_EVENT;
extern TraceEvent _TRACE_UNIN_SET_IRQ_EVENT;
extern TraceEvent _TRACE_UNIN_GET_CONFIG_REG_EVENT;
extern TraceEvent _TRACE_UNIN_DATA_WRITE_EVENT;
extern TraceEvent _TRACE_UNIN_DATA_READ_EVENT;
extern TraceEvent _TRACE_UNIN_WRITE_EVENT;
extern TraceEvent _TRACE_UNIN_READ_EVENT;
extern TraceEvent _TRACE_PPC4XX_PCI_MAP_IRQ_EVENT;
extern TraceEvent _TRACE_PPC4XX_PCI_SET_IRQ_EVENT;
extern TraceEvent _TRACE_PPC440_PCIX_MAP_IRQ_EVENT;
extern TraceEvent _TRACE_PPC440_PCIX_SET_IRQ_EVENT;
extern TraceEvent _TRACE_PPC440_PCIX_UPDATE_PIM_EVENT;
extern TraceEvent _TRACE_PPC440_PCIX_UPDATE_POM_EVENT;
extern TraceEvent _TRACE_PPC440_PCIX_REG_READ_EVENT;
extern TraceEvent _TRACE_PPC440_PCIX_REG_WRITE_EVENT;
extern TraceEvent _TRACE_PNV_PHB4_XIVE_NOTIFY_EVENT;
extern TraceEvent _TRACE_PNV_PHB4_XIVE_NOTIFY_IC_EVENT;
extern TraceEvent _TRACE_PNV_PHB4_XIVE_NOTIFY_ABT_EVENT;
extern TraceEvent _TRACE_DINO_CHIP_MEM_VALID_EVENT;
extern TraceEvent _TRACE_DINO_CHIP_READ_EVENT;
extern TraceEvent _TRACE_DINO_CHIP_WRITE_EVENT;
extern TraceEvent _TRACE_ASTRO_CHIP_MEM_VALID_EVENT;
extern TraceEvent _TRACE_ASTRO_CHIP_READ_EVENT;
extern TraceEvent _TRACE_ASTRO_CHIP_WRITE_EVENT;
extern TraceEvent _TRACE_ELROY_READ_EVENT;
extern TraceEvent _TRACE_ELROY_WRITE_EVENT;
extern TraceEvent _TRACE_ELROY_PCI_CONFIG_DATA_READ_EVENT;
extern TraceEvent _TRACE_ELROY_PCI_CONFIG_DATA_WRITE_EVENT;
extern TraceEvent _TRACE_IOSAPIC_REG_WRITE_EVENT;
extern TraceEvent _TRACE_IOSAPIC_REG_READ_EVENT;
extern uint16_t _TRACE_BONITO_SPCICONF_SMALL_ACCESS_DSTATE;
extern uint16_t _TRACE_GRACKLE_SET_IRQ_DSTATE;
extern uint16_t _TRACE_GT64120_READ_DSTATE;
extern uint16_t _TRACE_GT64120_WRITE_DSTATE;
extern uint16_t _TRACE_GT64120_READ_INTREG_DSTATE;
extern uint16_t _TRACE_GT64120_WRITE_INTREG_DSTATE;
extern uint16_t _TRACE_GT64120_ISD_REMAP_DSTATE;
extern uint16_t _TRACE_MV64361_REGION_MAP_DSTATE;
extern uint16_t _TRACE_MV64361_REGION_ENABLE_DSTATE;
extern uint16_t _TRACE_MV64361_REG_READ_DSTATE;
extern uint16_t _TRACE_MV64361_REG_WRITE_DSTATE;
extern uint16_t _TRACE_SABRE_SET_REQUEST_DSTATE;
extern uint16_t _TRACE_SABRE_CLEAR_REQUEST_DSTATE;
extern uint16_t _TRACE_SABRE_CONFIG_WRITE_DSTATE;
extern uint16_t _TRACE_SABRE_CONFIG_READ_DSTATE;
extern uint16_t _TRACE_SABRE_PCI_CONFIG_WRITE_DSTATE;
extern uint16_t _TRACE_SABRE_PCI_CONFIG_READ_DSTATE;
extern uint16_t _TRACE_SABRE_PCI_SET_IRQ_DSTATE;
extern uint16_t _TRACE_SABRE_PCI_SET_OBIO_IRQ_DSTATE;
extern uint16_t _TRACE_UNIN_SET_IRQ_DSTATE;
extern uint16_t _TRACE_UNIN_GET_CONFIG_REG_DSTATE;
extern uint16_t _TRACE_UNIN_DATA_WRITE_DSTATE;
extern uint16_t _TRACE_UNIN_DATA_READ_DSTATE;
extern uint16_t _TRACE_UNIN_WRITE_DSTATE;
extern uint16_t _TRACE_UNIN_READ_DSTATE;
extern uint16_t _TRACE_PPC4XX_PCI_MAP_IRQ_DSTATE;
extern uint16_t _TRACE_PPC4XX_PCI_SET_IRQ_DSTATE;
extern uint16_t _TRACE_PPC440_PCIX_MAP_IRQ_DSTATE;
extern uint16_t _TRACE_PPC440_PCIX_SET_IRQ_DSTATE;
extern uint16_t _TRACE_PPC440_PCIX_UPDATE_PIM_DSTATE;
extern uint16_t _TRACE_PPC440_PCIX_UPDATE_POM_DSTATE;
extern uint16_t _TRACE_PPC440_PCIX_REG_READ_DSTATE;
extern uint16_t _TRACE_PPC440_PCIX_REG_WRITE_DSTATE;
extern uint16_t _TRACE_PNV_PHB4_XIVE_NOTIFY_DSTATE;
extern uint16_t _TRACE_PNV_PHB4_XIVE_NOTIFY_IC_DSTATE;
extern uint16_t _TRACE_PNV_PHB4_XIVE_NOTIFY_ABT_DSTATE;
extern uint16_t _TRACE_DINO_CHIP_MEM_VALID_DSTATE;
extern uint16_t _TRACE_DINO_CHIP_READ_DSTATE;
extern uint16_t _TRACE_DINO_CHIP_WRITE_DSTATE;
extern uint16_t _TRACE_ASTRO_CHIP_MEM_VALID_DSTATE;
extern uint16_t _TRACE_ASTRO_CHIP_READ_DSTATE;
extern uint16_t _TRACE_ASTRO_CHIP_WRITE_DSTATE;
extern uint16_t _TRACE_ELROY_READ_DSTATE;
extern uint16_t _TRACE_ELROY_WRITE_DSTATE;
extern uint16_t _TRACE_ELROY_PCI_CONFIG_DATA_READ_DSTATE;
extern uint16_t _TRACE_ELROY_PCI_CONFIG_DATA_WRITE_DSTATE;
extern uint16_t _TRACE_IOSAPIC_REG_WRITE_DSTATE;
extern uint16_t _TRACE_IOSAPIC_REG_READ_DSTATE;
#define TRACE_BONITO_SPCICONF_SMALL_ACCESS_ENABLED 1
#define TRACE_GRACKLE_SET_IRQ_ENABLED 1
#define TRACE_GT64120_READ_ENABLED 1
#define TRACE_GT64120_WRITE_ENABLED 1
#define TRACE_GT64120_READ_INTREG_ENABLED 1
#define TRACE_GT64120_WRITE_INTREG_ENABLED 1
#define TRACE_GT64120_ISD_REMAP_ENABLED 1
#define TRACE_MV64361_REGION_MAP_ENABLED 1
#define TRACE_MV64361_REGION_ENABLE_ENABLED 1
#define TRACE_MV64361_REG_READ_ENABLED 1
#define TRACE_MV64361_REG_WRITE_ENABLED 1
#define TRACE_SABRE_SET_REQUEST_ENABLED 1
#define TRACE_SABRE_CLEAR_REQUEST_ENABLED 1
#define TRACE_SABRE_CONFIG_WRITE_ENABLED 1
#define TRACE_SABRE_CONFIG_READ_ENABLED 1
#define TRACE_SABRE_PCI_CONFIG_WRITE_ENABLED 1
#define TRACE_SABRE_PCI_CONFIG_READ_ENABLED 1
#define TRACE_SABRE_PCI_SET_IRQ_ENABLED 1
#define TRACE_SABRE_PCI_SET_OBIO_IRQ_ENABLED 1
#define TRACE_UNIN_SET_IRQ_ENABLED 1
#define TRACE_UNIN_GET_CONFIG_REG_ENABLED 1
#define TRACE_UNIN_DATA_WRITE_ENABLED 1
#define TRACE_UNIN_DATA_READ_ENABLED 1
#define TRACE_UNIN_WRITE_ENABLED 1
#define TRACE_UNIN_READ_ENABLED 1
#define TRACE_PPC4XX_PCI_MAP_IRQ_ENABLED 1
#define TRACE_PPC4XX_PCI_SET_IRQ_ENABLED 1
#define TRACE_PPC440_PCIX_MAP_IRQ_ENABLED 1
#define TRACE_PPC440_PCIX_SET_IRQ_ENABLED 1
#define TRACE_PPC440_PCIX_UPDATE_PIM_ENABLED 1
#define TRACE_PPC440_PCIX_UPDATE_POM_ENABLED 1
#define TRACE_PPC440_PCIX_REG_READ_ENABLED 1
#define TRACE_PPC440_PCIX_REG_WRITE_ENABLED 1
#define TRACE_PNV_PHB4_XIVE_NOTIFY_ENABLED 1
#define TRACE_PNV_PHB4_XIVE_NOTIFY_IC_ENABLED 1
#define TRACE_PNV_PHB4_XIVE_NOTIFY_ABT_ENABLED 1
#define TRACE_DINO_CHIP_MEM_VALID_ENABLED 1
#define TRACE_DINO_CHIP_READ_ENABLED 1
#define TRACE_DINO_CHIP_WRITE_ENABLED 1
#define TRACE_ASTRO_CHIP_MEM_VALID_ENABLED 1
#define TRACE_ASTRO_CHIP_READ_ENABLED 1
#define TRACE_ASTRO_CHIP_WRITE_ENABLED 1
#define TRACE_ELROY_READ_ENABLED 1
#define TRACE_ELROY_WRITE_ENABLED 1
#define TRACE_ELROY_PCI_CONFIG_DATA_READ_ENABLED 1
#define TRACE_ELROY_PCI_CONFIG_DATA_WRITE_ENABLED 1
#define TRACE_IOSAPIC_REG_WRITE_ENABLED 1
#define TRACE_IOSAPIC_REG_READ_ENABLED 1
#include "qemu/log-for-trace.h"
#include "qemu/error-report.h"


#define TRACE_BONITO_SPCICONF_SMALL_ACCESS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_BONITO_SPCICONF_SMALL_ACCESS) || \
    false)

static inline void _nocheck__trace_bonito_spciconf_small_access(uint64_t addr, unsigned size)
{
    if (trace_event_get_state(TRACE_BONITO_SPCICONF_SMALL_ACCESS) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 4 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:bonito_spciconf_small_access " "PCI config address is smaller then 32-bit, addr: 0x%"PRIx64", size: %u" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, size);
#line 172 "trace/trace-hw_pci_host.h"
        } else {
#line 4 "../hw/pci-host/trace-events"
            qemu_log("bonito_spciconf_small_access " "PCI config address is smaller then 32-bit, addr: 0x%"PRIx64", size: %u" "\n", addr, size);
#line 176 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_bonito_spciconf_small_access(uint64_t addr, unsigned size)
{
    if (true) {
        _nocheck__trace_bonito_spciconf_small_access(addr, size);
    }
}

#define TRACE_GRACKLE_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GRACKLE_SET_IRQ) || \
    false)

static inline void _nocheck__trace_grackle_set_irq(int irq_num, int level)
{
    if (trace_event_get_state(TRACE_GRACKLE_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 7 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:grackle_set_irq " "set_irq num %d level %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , irq_num, level);
#line 203 "trace/trace-hw_pci_host.h"
        } else {
#line 7 "../hw/pci-host/trace-events"
            qemu_log("grackle_set_irq " "set_irq num %d level %d" "\n", irq_num, level);
#line 207 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_grackle_set_irq(int irq_num, int level)
{
    if (true) {
        _nocheck__trace_grackle_set_irq(irq_num, level);
    }
}

#define TRACE_GT64120_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GT64120_READ) || \
    false)

static inline void _nocheck__trace_gt64120_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_GT64120_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 10 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:gt64120_read " "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, value);
#line 234 "trace/trace-hw_pci_host.h"
        } else {
#line 10 "../hw/pci-host/trace-events"
            qemu_log("gt64120_read " "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64 "\n", addr, value);
#line 238 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_gt64120_read(uint64_t addr, uint64_t value)
{
    if (true) {
        _nocheck__trace_gt64120_read(addr, value);
    }
}

#define TRACE_GT64120_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GT64120_WRITE) || \
    false)

static inline void _nocheck__trace_gt64120_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_GT64120_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 11 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:gt64120_write " "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, value);
#line 265 "trace/trace-hw_pci_host.h"
        } else {
#line 11 "../hw/pci-host/trace-events"
            qemu_log("gt64120_write " "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64 "\n", addr, value);
#line 269 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_gt64120_write(uint64_t addr, uint64_t value)
{
    if (true) {
        _nocheck__trace_gt64120_write(addr, value);
    }
}

#define TRACE_GT64120_READ_INTREG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GT64120_READ_INTREG) || \
    false)

static inline void _nocheck__trace_gt64120_read_intreg(const char * regname, unsigned size, uint64_t value)
{
    if (trace_event_get_state(TRACE_GT64120_READ_INTREG) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 12 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:gt64120_read_intreg " "gt64120 read %s size:%u value:0x%08" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , regname, size, value);
#line 296 "trace/trace-hw_pci_host.h"
        } else {
#line 12 "../hw/pci-host/trace-events"
            qemu_log("gt64120_read_intreg " "gt64120 read %s size:%u value:0x%08" PRIx64 "\n", regname, size, value);
#line 300 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_gt64120_read_intreg(const char * regname, unsigned size, uint64_t value)
{
    if (true) {
        _nocheck__trace_gt64120_read_intreg(regname, size, value);
    }
}

#define TRACE_GT64120_WRITE_INTREG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GT64120_WRITE_INTREG) || \
    false)

static inline void _nocheck__trace_gt64120_write_intreg(const char * regname, unsigned size, uint64_t value)
{
    if (trace_event_get_state(TRACE_GT64120_WRITE_INTREG) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 13 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:gt64120_write_intreg " "gt64120 write %s size:%u value:0x%08" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , regname, size, value);
#line 327 "trace/trace-hw_pci_host.h"
        } else {
#line 13 "../hw/pci-host/trace-events"
            qemu_log("gt64120_write_intreg " "gt64120 write %s size:%u value:0x%08" PRIx64 "\n", regname, size, value);
#line 331 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_gt64120_write_intreg(const char * regname, unsigned size, uint64_t value)
{
    if (true) {
        _nocheck__trace_gt64120_write_intreg(regname, size, value);
    }
}

#define TRACE_GT64120_ISD_REMAP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_GT64120_ISD_REMAP) || \
    false)

static inline void _nocheck__trace_gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr)
{
    if (trace_event_get_state(TRACE_GT64120_ISD_REMAP) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 14 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:gt64120_isd_remap " "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , from_length, from_addr, to_length, to_addr);
#line 358 "trace/trace-hw_pci_host.h"
        } else {
#line 14 "../hw/pci-host/trace-events"
            qemu_log("gt64120_isd_remap " "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 "\n", from_length, from_addr, to_length, to_addr);
#line 362 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr)
{
    if (true) {
        _nocheck__trace_gt64120_isd_remap(from_length, from_addr, to_length, to_addr);
    }
}

#define TRACE_MV64361_REGION_MAP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MV64361_REGION_MAP) || \
    false)

static inline void _nocheck__trace_mv64361_region_map(const char * name, uint64_t poffs, uint64_t size, uint64_t moffs)
{
    if (trace_event_get_state(TRACE_MV64361_REGION_MAP) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 17 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:mv64361_region_map " "Mapping %s 0x%"PRIx64"+0x%"PRIx64" @ 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , name, poffs, size, moffs);
#line 389 "trace/trace-hw_pci_host.h"
        } else {
#line 17 "../hw/pci-host/trace-events"
            qemu_log("mv64361_region_map " "Mapping %s 0x%"PRIx64"+0x%"PRIx64" @ 0x%"PRIx64 "\n", name, poffs, size, moffs);
#line 393 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_mv64361_region_map(const char * name, uint64_t poffs, uint64_t size, uint64_t moffs)
{
    if (true) {
        _nocheck__trace_mv64361_region_map(name, poffs, size, moffs);
    }
}

#define TRACE_MV64361_REGION_ENABLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MV64361_REGION_ENABLE) || \
    false)

static inline void _nocheck__trace_mv64361_region_enable(const char * op, int num)
{
    if (trace_event_get_state(TRACE_MV64361_REGION_ENABLE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 18 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:mv64361_region_enable " "Should %s region %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , op, num);
#line 420 "trace/trace-hw_pci_host.h"
        } else {
#line 18 "../hw/pci-host/trace-events"
            qemu_log("mv64361_region_enable " "Should %s region %d" "\n", op, num);
#line 424 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_mv64361_region_enable(const char * op, int num)
{
    if (true) {
        _nocheck__trace_mv64361_region_enable(op, num);
    }
}

#define TRACE_MV64361_REG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MV64361_REG_READ) || \
    false)

static inline void _nocheck__trace_mv64361_reg_read(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_MV64361_REG_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 19 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:mv64361_reg_read " "0x%"PRIx64" -> 0x%x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val);
#line 451 "trace/trace-hw_pci_host.h"
        } else {
#line 19 "../hw/pci-host/trace-events"
            qemu_log("mv64361_reg_read " "0x%"PRIx64" -> 0x%x" "\n", addr, val);
#line 455 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_mv64361_reg_read(uint64_t addr, uint32_t val)
{
    if (true) {
        _nocheck__trace_mv64361_reg_read(addr, val);
    }
}

#define TRACE_MV64361_REG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MV64361_REG_WRITE) || \
    false)

static inline void _nocheck__trace_mv64361_reg_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_MV64361_REG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 20 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:mv64361_reg_write " "0x%"PRIx64" <- 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val);
#line 482 "trace/trace-hw_pci_host.h"
        } else {
#line 20 "../hw/pci-host/trace-events"
            qemu_log("mv64361_reg_write " "0x%"PRIx64" <- 0x%"PRIx64 "\n", addr, val);
#line 486 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_mv64361_reg_write(uint64_t addr, uint64_t val)
{
    if (true) {
        _nocheck__trace_mv64361_reg_write(addr, val);
    }
}

#define TRACE_SABRE_SET_REQUEST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SABRE_SET_REQUEST) || \
    false)

static inline void _nocheck__trace_sabre_set_request(int irq_num)
{
    if (trace_event_get_state(TRACE_SABRE_SET_REQUEST) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 23 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:sabre_set_request " "request irq %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , irq_num);
#line 513 "trace/trace-hw_pci_host.h"
        } else {
#line 23 "../hw/pci-host/trace-events"
            qemu_log("sabre_set_request " "request irq %d" "\n", irq_num);
#line 517 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_sabre_set_request(int irq_num)
{
    if (true) {
        _nocheck__trace_sabre_set_request(irq_num);
    }
}

#define TRACE_SABRE_CLEAR_REQUEST_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SABRE_CLEAR_REQUEST) || \
    false)

static inline void _nocheck__trace_sabre_clear_request(int irq_num)
{
    if (trace_event_get_state(TRACE_SABRE_CLEAR_REQUEST) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 24 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:sabre_clear_request " "clear request irq %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , irq_num);
#line 544 "trace/trace-hw_pci_host.h"
        } else {
#line 24 "../hw/pci-host/trace-events"
            qemu_log("sabre_clear_request " "clear request irq %d" "\n", irq_num);
#line 548 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_sabre_clear_request(int irq_num)
{
    if (true) {
        _nocheck__trace_sabre_clear_request(irq_num);
    }
}

#define TRACE_SABRE_CONFIG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SABRE_CONFIG_WRITE) || \
    false)

static inline void _nocheck__trace_sabre_config_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SABRE_CONFIG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 25 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:sabre_config_write " "addr 0x%"PRIx64" val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val);
#line 575 "trace/trace-hw_pci_host.h"
        } else {
#line 25 "../hw/pci-host/trace-events"
            qemu_log("sabre_config_write " "addr 0x%"PRIx64" val 0x%"PRIx64 "\n", addr, val);
#line 579 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_sabre_config_write(uint64_t addr, uint64_t val)
{
    if (true) {
        _nocheck__trace_sabre_config_write(addr, val);
    }
}

#define TRACE_SABRE_CONFIG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SABRE_CONFIG_READ) || \
    false)

static inline void _nocheck__trace_sabre_config_read(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SABRE_CONFIG_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 26 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:sabre_config_read " "addr 0x%"PRIx64" val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val);
#line 606 "trace/trace-hw_pci_host.h"
        } else {
#line 26 "../hw/pci-host/trace-events"
            qemu_log("sabre_config_read " "addr 0x%"PRIx64" val 0x%"PRIx64 "\n", addr, val);
#line 610 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_sabre_config_read(uint64_t addr, uint64_t val)
{
    if (true) {
        _nocheck__trace_sabre_config_read(addr, val);
    }
}

#define TRACE_SABRE_PCI_CONFIG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SABRE_PCI_CONFIG_WRITE) || \
    false)

static inline void _nocheck__trace_sabre_pci_config_write(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SABRE_PCI_CONFIG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 27 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:sabre_pci_config_write " "addr 0x%"PRIx64" val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val);
#line 637 "trace/trace-hw_pci_host.h"
        } else {
#line 27 "../hw/pci-host/trace-events"
            qemu_log("sabre_pci_config_write " "addr 0x%"PRIx64" val 0x%"PRIx64 "\n", addr, val);
#line 641 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_sabre_pci_config_write(uint64_t addr, uint64_t val)
{
    if (true) {
        _nocheck__trace_sabre_pci_config_write(addr, val);
    }
}

#define TRACE_SABRE_PCI_CONFIG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SABRE_PCI_CONFIG_READ) || \
    false)

static inline void _nocheck__trace_sabre_pci_config_read(uint64_t addr, uint64_t val)
{
    if (trace_event_get_state(TRACE_SABRE_PCI_CONFIG_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 28 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:sabre_pci_config_read " "addr 0x%"PRIx64" val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val);
#line 668 "trace/trace-hw_pci_host.h"
        } else {
#line 28 "../hw/pci-host/trace-events"
            qemu_log("sabre_pci_config_read " "addr 0x%"PRIx64" val 0x%"PRIx64 "\n", addr, val);
#line 672 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_sabre_pci_config_read(uint64_t addr, uint64_t val)
{
    if (true) {
        _nocheck__trace_sabre_pci_config_read(addr, val);
    }
}

#define TRACE_SABRE_PCI_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SABRE_PCI_SET_IRQ) || \
    false)

static inline void _nocheck__trace_sabre_pci_set_irq(int irq_num, int level)
{
    if (trace_event_get_state(TRACE_SABRE_PCI_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 29 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:sabre_pci_set_irq " "set irq_in %d level %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , irq_num, level);
#line 699 "trace/trace-hw_pci_host.h"
        } else {
#line 29 "../hw/pci-host/trace-events"
            qemu_log("sabre_pci_set_irq " "set irq_in %d level %d" "\n", irq_num, level);
#line 703 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_sabre_pci_set_irq(int irq_num, int level)
{
    if (true) {
        _nocheck__trace_sabre_pci_set_irq(irq_num, level);
    }
}

#define TRACE_SABRE_PCI_SET_OBIO_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_SABRE_PCI_SET_OBIO_IRQ) || \
    false)

static inline void _nocheck__trace_sabre_pci_set_obio_irq(int irq_num, int level)
{
    if (trace_event_get_state(TRACE_SABRE_PCI_SET_OBIO_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 30 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:sabre_pci_set_obio_irq " "set irq %d level %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , irq_num, level);
#line 730 "trace/trace-hw_pci_host.h"
        } else {
#line 30 "../hw/pci-host/trace-events"
            qemu_log("sabre_pci_set_obio_irq " "set irq %d level %d" "\n", irq_num, level);
#line 734 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_sabre_pci_set_obio_irq(int irq_num, int level)
{
    if (true) {
        _nocheck__trace_sabre_pci_set_obio_irq(irq_num, level);
    }
}

#define TRACE_UNIN_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_UNIN_SET_IRQ) || \
    false)

static inline void _nocheck__trace_unin_set_irq(int irq_num, int level)
{
    if (trace_event_get_state(TRACE_UNIN_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 33 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:unin_set_irq " "setting INT %d = %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , irq_num, level);
#line 761 "trace/trace-hw_pci_host.h"
        } else {
#line 33 "../hw/pci-host/trace-events"
            qemu_log("unin_set_irq " "setting INT %d = %d" "\n", irq_num, level);
#line 765 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_unin_set_irq(int irq_num, int level)
{
    if (true) {
        _nocheck__trace_unin_set_irq(irq_num, level);
    }
}

#define TRACE_UNIN_GET_CONFIG_REG_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_UNIN_GET_CONFIG_REG) || \
    false)

static inline void _nocheck__trace_unin_get_config_reg(uint32_t reg, uint32_t addr, uint32_t retval)
{
    if (trace_event_get_state(TRACE_UNIN_GET_CONFIG_REG) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 34 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:unin_get_config_reg " "converted config space accessor 0x%"PRIx32 "/0x%"PRIx32 " -> 0x%"PRIx32 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , reg, addr, retval);
#line 792 "trace/trace-hw_pci_host.h"
        } else {
#line 34 "../hw/pci-host/trace-events"
            qemu_log("unin_get_config_reg " "converted config space accessor 0x%"PRIx32 "/0x%"PRIx32 " -> 0x%"PRIx32 "\n", reg, addr, retval);
#line 796 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_unin_get_config_reg(uint32_t reg, uint32_t addr, uint32_t retval)
{
    if (true) {
        _nocheck__trace_unin_get_config_reg(reg, addr, retval);
    }
}

#define TRACE_UNIN_DATA_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_UNIN_DATA_WRITE) || \
    false)

static inline void _nocheck__trace_unin_data_write(uint64_t addr, unsigned len, uint64_t val)
{
    if (trace_event_get_state(TRACE_UNIN_DATA_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 35 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:unin_data_write " "write addr 0x%"PRIx64 " len %d val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, len, val);
#line 823 "trace/trace-hw_pci_host.h"
        } else {
#line 35 "../hw/pci-host/trace-events"
            qemu_log("unin_data_write " "write addr 0x%"PRIx64 " len %d val 0x%"PRIx64 "\n", addr, len, val);
#line 827 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_unin_data_write(uint64_t addr, unsigned len, uint64_t val)
{
    if (true) {
        _nocheck__trace_unin_data_write(addr, len, val);
    }
}

#define TRACE_UNIN_DATA_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_UNIN_DATA_READ) || \
    false)

static inline void _nocheck__trace_unin_data_read(uint64_t addr, unsigned len, uint64_t val)
{
    if (trace_event_get_state(TRACE_UNIN_DATA_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 36 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:unin_data_read " "read addr 0x%"PRIx64 " len %d val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, len, val);
#line 854 "trace/trace-hw_pci_host.h"
        } else {
#line 36 "../hw/pci-host/trace-events"
            qemu_log("unin_data_read " "read addr 0x%"PRIx64 " len %d val 0x%"PRIx64 "\n", addr, len, val);
#line 858 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_unin_data_read(uint64_t addr, unsigned len, uint64_t val)
{
    if (true) {
        _nocheck__trace_unin_data_read(addr, len, val);
    }
}

#define TRACE_UNIN_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_UNIN_WRITE) || \
    false)

static inline void _nocheck__trace_unin_write(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_UNIN_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 37 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:unin_write " "addr=0x%" PRIx64 " val=0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, value);
#line 885 "trace/trace-hw_pci_host.h"
        } else {
#line 37 "../hw/pci-host/trace-events"
            qemu_log("unin_write " "addr=0x%" PRIx64 " val=0x%"PRIx64 "\n", addr, value);
#line 889 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_unin_write(uint64_t addr, uint64_t value)
{
    if (true) {
        _nocheck__trace_unin_write(addr, value);
    }
}

#define TRACE_UNIN_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_UNIN_READ) || \
    false)

static inline void _nocheck__trace_unin_read(uint64_t addr, uint64_t value)
{
    if (trace_event_get_state(TRACE_UNIN_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 38 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:unin_read " "addr=0x%" PRIx64 " val=0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, value);
#line 916 "trace/trace-hw_pci_host.h"
        } else {
#line 38 "../hw/pci-host/trace-events"
            qemu_log("unin_read " "addr=0x%" PRIx64 " val=0x%"PRIx64 "\n", addr, value);
#line 920 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_unin_read(uint64_t addr, uint64_t value)
{
    if (true) {
        _nocheck__trace_unin_read(addr, value);
    }
}

#define TRACE_PPC4XX_PCI_MAP_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PPC4XX_PCI_MAP_IRQ) || \
    false)

static inline void _nocheck__trace_ppc4xx_pci_map_irq(int32_t devfn, int irq_num, int slot)
{
    if (trace_event_get_state(TRACE_PPC4XX_PCI_MAP_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 41 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:ppc4xx_pci_map_irq " "devfn 0x%x irq %d -> %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , devfn, irq_num, slot);
#line 947 "trace/trace-hw_pci_host.h"
        } else {
#line 41 "../hw/pci-host/trace-events"
            qemu_log("ppc4xx_pci_map_irq " "devfn 0x%x irq %d -> %d" "\n", devfn, irq_num, slot);
#line 951 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_ppc4xx_pci_map_irq(int32_t devfn, int irq_num, int slot)
{
    if (true) {
        _nocheck__trace_ppc4xx_pci_map_irq(devfn, irq_num, slot);
    }
}

#define TRACE_PPC4XX_PCI_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PPC4XX_PCI_SET_IRQ) || \
    false)

static inline void _nocheck__trace_ppc4xx_pci_set_irq(int irq_num)
{
    if (trace_event_get_state(TRACE_PPC4XX_PCI_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 42 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:ppc4xx_pci_set_irq " "PCI irq %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , irq_num);
#line 978 "trace/trace-hw_pci_host.h"
        } else {
#line 42 "../hw/pci-host/trace-events"
            qemu_log("ppc4xx_pci_set_irq " "PCI irq %d" "\n", irq_num);
#line 982 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_ppc4xx_pci_set_irq(int irq_num)
{
    if (true) {
        _nocheck__trace_ppc4xx_pci_set_irq(irq_num);
    }
}

#define TRACE_PPC440_PCIX_MAP_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PPC440_PCIX_MAP_IRQ) || \
    false)

static inline void _nocheck__trace_ppc440_pcix_map_irq(int32_t devfn, int irq_num, int slot)
{
    if (trace_event_get_state(TRACE_PPC440_PCIX_MAP_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 45 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:ppc440_pcix_map_irq " "devfn 0x%x irq %d -> %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , devfn, irq_num, slot);
#line 1009 "trace/trace-hw_pci_host.h"
        } else {
#line 45 "../hw/pci-host/trace-events"
            qemu_log("ppc440_pcix_map_irq " "devfn 0x%x irq %d -> %d" "\n", devfn, irq_num, slot);
#line 1013 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_ppc440_pcix_map_irq(int32_t devfn, int irq_num, int slot)
{
    if (true) {
        _nocheck__trace_ppc440_pcix_map_irq(devfn, irq_num, slot);
    }
}

#define TRACE_PPC440_PCIX_SET_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PPC440_PCIX_SET_IRQ) || \
    false)

static inline void _nocheck__trace_ppc440_pcix_set_irq(int irq_num)
{
    if (trace_event_get_state(TRACE_PPC440_PCIX_SET_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 46 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:ppc440_pcix_set_irq " "PCI irq %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , irq_num);
#line 1040 "trace/trace-hw_pci_host.h"
        } else {
#line 46 "../hw/pci-host/trace-events"
            qemu_log("ppc440_pcix_set_irq " "PCI irq %d" "\n", irq_num);
#line 1044 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_ppc440_pcix_set_irq(int irq_num)
{
    if (true) {
        _nocheck__trace_ppc440_pcix_set_irq(irq_num);
    }
}

#define TRACE_PPC440_PCIX_UPDATE_PIM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PPC440_PCIX_UPDATE_PIM) || \
    false)

static inline void _nocheck__trace_ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la)
{
    if (trace_event_get_state(TRACE_PPC440_PCIX_UPDATE_PIM) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 47 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:ppc440_pcix_update_pim " "Added window %d of size=0x%" PRIx64 " to CPU=0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , idx, size, la);
#line 1071 "trace/trace-hw_pci_host.h"
        } else {
#line 47 "../hw/pci-host/trace-events"
            qemu_log("ppc440_pcix_update_pim " "Added window %d of size=0x%" PRIx64 " to CPU=0x%" PRIx64 "\n", idx, size, la);
#line 1075 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la)
{
    if (true) {
        _nocheck__trace_ppc440_pcix_update_pim(idx, size, la);
    }
}

#define TRACE_PPC440_PCIX_UPDATE_POM_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PPC440_PCIX_UPDATE_POM) || \
    false)

static inline void _nocheck__trace_ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia)
{
    if (trace_event_get_state(TRACE_PPC440_PCIX_UPDATE_POM) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 48 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:ppc440_pcix_update_pom " "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , idx, size, la, pcia);
#line 1102 "trace/trace-hw_pci_host.h"
        } else {
#line 48 "../hw/pci-host/trace-events"
            qemu_log("ppc440_pcix_update_pom " "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64 "\n", idx, size, la, pcia);
#line 1106 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia)
{
    if (true) {
        _nocheck__trace_ppc440_pcix_update_pom(idx, size, la, pcia);
    }
}

#define TRACE_PPC440_PCIX_REG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PPC440_PCIX_REG_READ) || \
    false)

static inline void _nocheck__trace_ppc440_pcix_reg_read(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_PPC440_PCIX_REG_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 49 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:ppc440_pcix_reg_read " "addr 0x%" PRIx64 " = 0x%" PRIx32 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val);
#line 1133 "trace/trace-hw_pci_host.h"
        } else {
#line 49 "../hw/pci-host/trace-events"
            qemu_log("ppc440_pcix_reg_read " "addr 0x%" PRIx64 " = 0x%" PRIx32 "\n", addr, val);
#line 1137 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_ppc440_pcix_reg_read(uint64_t addr, uint32_t val)
{
    if (true) {
        _nocheck__trace_ppc440_pcix_reg_read(addr, val);
    }
}

#define TRACE_PPC440_PCIX_REG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PPC440_PCIX_REG_WRITE) || \
    false)

static inline void _nocheck__trace_ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size)
{
    if (trace_event_get_state(TRACE_PPC440_PCIX_REG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 50 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:ppc440_pcix_reg_write " "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val, size);
#line 1164 "trace/trace-hw_pci_host.h"
        } else {
#line 50 "../hw/pci-host/trace-events"
            qemu_log("ppc440_pcix_reg_write " "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32 "\n", addr, val, size);
#line 1168 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size)
{
    if (true) {
        _nocheck__trace_ppc440_pcix_reg_write(addr, val, size);
    }
}

#define TRACE_PNV_PHB4_XIVE_NOTIFY_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PNV_PHB4_XIVE_NOTIFY) || \
    false)

static inline void _nocheck__trace_pnv_phb4_xive_notify(uint64_t notif_port, uint64_t data)
{
    if (trace_event_get_state(TRACE_PNV_PHB4_XIVE_NOTIFY) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 53 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:pnv_phb4_xive_notify " "notif=@0x%"PRIx64" data=0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , notif_port, data);
#line 1195 "trace/trace-hw_pci_host.h"
        } else {
#line 53 "../hw/pci-host/trace-events"
            qemu_log("pnv_phb4_xive_notify " "notif=@0x%"PRIx64" data=0x%"PRIx64 "\n", notif_port, data);
#line 1199 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_pnv_phb4_xive_notify(uint64_t notif_port, uint64_t data)
{
    if (true) {
        _nocheck__trace_pnv_phb4_xive_notify(notif_port, data);
    }
}

#define TRACE_PNV_PHB4_XIVE_NOTIFY_IC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PNV_PHB4_XIVE_NOTIFY_IC) || \
    false)

static inline void _nocheck__trace_pnv_phb4_xive_notify_ic(uint64_t addr, uint64_t data)
{
    if (trace_event_get_state(TRACE_PNV_PHB4_XIVE_NOTIFY_IC) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 54 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:pnv_phb4_xive_notify_ic " "addr=@0x%"PRIx64" data=0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, data);
#line 1226 "trace/trace-hw_pci_host.h"
        } else {
#line 54 "../hw/pci-host/trace-events"
            qemu_log("pnv_phb4_xive_notify_ic " "addr=@0x%"PRIx64" data=0x%"PRIx64 "\n", addr, data);
#line 1230 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_pnv_phb4_xive_notify_ic(uint64_t addr, uint64_t data)
{
    if (true) {
        _nocheck__trace_pnv_phb4_xive_notify_ic(addr, data);
    }
}

#define TRACE_PNV_PHB4_XIVE_NOTIFY_ABT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PNV_PHB4_XIVE_NOTIFY_ABT) || \
    false)

static inline void _nocheck__trace_pnv_phb4_xive_notify_abt(uint64_t notif_port, uint64_t data)
{
    if (trace_event_get_state(TRACE_PNV_PHB4_XIVE_NOTIFY_ABT) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 55 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:pnv_phb4_xive_notify_abt " "notif=@0x%"PRIx64" data=0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , notif_port, data);
#line 1257 "trace/trace-hw_pci_host.h"
        } else {
#line 55 "../hw/pci-host/trace-events"
            qemu_log("pnv_phb4_xive_notify_abt " "notif=@0x%"PRIx64" data=0x%"PRIx64 "\n", notif_port, data);
#line 1261 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_pnv_phb4_xive_notify_abt(uint64_t notif_port, uint64_t data)
{
    if (true) {
        _nocheck__trace_pnv_phb4_xive_notify_abt(notif_port, data);
    }
}

#define TRACE_DINO_CHIP_MEM_VALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DINO_CHIP_MEM_VALID) || \
    false)

static inline void _nocheck__trace_dino_chip_mem_valid(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_DINO_CHIP_MEM_VALID) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 58 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:dino_chip_mem_valid " "access to addr 0x%"PRIx64" is %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val);
#line 1288 "trace/trace-hw_pci_host.h"
        } else {
#line 58 "../hw/pci-host/trace-events"
            qemu_log("dino_chip_mem_valid " "access to addr 0x%"PRIx64" is %d" "\n", addr, val);
#line 1292 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_dino_chip_mem_valid(uint64_t addr, uint32_t val)
{
    if (true) {
        _nocheck__trace_dino_chip_mem_valid(addr, val);
    }
}

#define TRACE_DINO_CHIP_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DINO_CHIP_READ) || \
    false)

static inline void _nocheck__trace_dino_chip_read(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_DINO_CHIP_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 59 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:dino_chip_read " "addr 0x%"PRIx64" val 0x%08x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val);
#line 1319 "trace/trace-hw_pci_host.h"
        } else {
#line 59 "../hw/pci-host/trace-events"
            qemu_log("dino_chip_read " "addr 0x%"PRIx64" val 0x%08x" "\n", addr, val);
#line 1323 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_dino_chip_read(uint64_t addr, uint32_t val)
{
    if (true) {
        _nocheck__trace_dino_chip_read(addr, val);
    }
}

#define TRACE_DINO_CHIP_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_DINO_CHIP_WRITE) || \
    false)

static inline void _nocheck__trace_dino_chip_write(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_DINO_CHIP_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 60 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:dino_chip_write " "addr 0x%"PRIx64" val 0x%08x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val);
#line 1350 "trace/trace-hw_pci_host.h"
        } else {
#line 60 "../hw/pci-host/trace-events"
            qemu_log("dino_chip_write " "addr 0x%"PRIx64" val 0x%08x" "\n", addr, val);
#line 1354 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_dino_chip_write(uint64_t addr, uint32_t val)
{
    if (true) {
        _nocheck__trace_dino_chip_write(addr, val);
    }
}

#define TRACE_ASTRO_CHIP_MEM_VALID_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASTRO_CHIP_MEM_VALID) || \
    false)

static inline void _nocheck__trace_astro_chip_mem_valid(uint64_t addr, uint32_t val)
{
    if (trace_event_get_state(TRACE_ASTRO_CHIP_MEM_VALID) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 63 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:astro_chip_mem_valid " "access to addr 0x%"PRIx64" is %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, val);
#line 1381 "trace/trace-hw_pci_host.h"
        } else {
#line 63 "../hw/pci-host/trace-events"
            qemu_log("astro_chip_mem_valid " "access to addr 0x%"PRIx64" is %d" "\n", addr, val);
#line 1385 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_astro_chip_mem_valid(uint64_t addr, uint32_t val)
{
    if (true) {
        _nocheck__trace_astro_chip_mem_valid(addr, val);
    }
}

#define TRACE_ASTRO_CHIP_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASTRO_CHIP_READ) || \
    false)

static inline void _nocheck__trace_astro_chip_read(uint64_t addr, int size, uint64_t val)
{
    if (trace_event_get_state(TRACE_ASTRO_CHIP_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 64 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:astro_chip_read " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, size, val);
#line 1412 "trace/trace-hw_pci_host.h"
        } else {
#line 64 "../hw/pci-host/trace-events"
            qemu_log("astro_chip_read " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n", addr, size, val);
#line 1416 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_astro_chip_read(uint64_t addr, int size, uint64_t val)
{
    if (true) {
        _nocheck__trace_astro_chip_read(addr, size, val);
    }
}

#define TRACE_ASTRO_CHIP_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ASTRO_CHIP_WRITE) || \
    false)

static inline void _nocheck__trace_astro_chip_write(uint64_t addr, int size, uint64_t val)
{
    if (trace_event_get_state(TRACE_ASTRO_CHIP_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 65 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:astro_chip_write " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, size, val);
#line 1443 "trace/trace-hw_pci_host.h"
        } else {
#line 65 "../hw/pci-host/trace-events"
            qemu_log("astro_chip_write " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n", addr, size, val);
#line 1447 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_astro_chip_write(uint64_t addr, int size, uint64_t val)
{
    if (true) {
        _nocheck__trace_astro_chip_write(addr, size, val);
    }
}

#define TRACE_ELROY_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ELROY_READ) || \
    false)

static inline void _nocheck__trace_elroy_read(uint64_t addr, int size, uint64_t val)
{
    if (trace_event_get_state(TRACE_ELROY_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 66 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:elroy_read " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, size, val);
#line 1474 "trace/trace-hw_pci_host.h"
        } else {
#line 66 "../hw/pci-host/trace-events"
            qemu_log("elroy_read " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n", addr, size, val);
#line 1478 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_elroy_read(uint64_t addr, int size, uint64_t val)
{
    if (true) {
        _nocheck__trace_elroy_read(addr, size, val);
    }
}

#define TRACE_ELROY_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ELROY_WRITE) || \
    false)

static inline void _nocheck__trace_elroy_write(uint64_t addr, int size, uint64_t val)
{
    if (trace_event_get_state(TRACE_ELROY_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 67 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:elroy_write " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, size, val);
#line 1505 "trace/trace-hw_pci_host.h"
        } else {
#line 67 "../hw/pci-host/trace-events"
            qemu_log("elroy_write " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n", addr, size, val);
#line 1509 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_elroy_write(uint64_t addr, int size, uint64_t val)
{
    if (true) {
        _nocheck__trace_elroy_write(addr, size, val);
    }
}

#define TRACE_ELROY_PCI_CONFIG_DATA_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ELROY_PCI_CONFIG_DATA_READ) || \
    false)

static inline void _nocheck__trace_elroy_pci_config_data_read(uint64_t addr, int size, uint64_t val)
{
    if (trace_event_get_state(TRACE_ELROY_PCI_CONFIG_DATA_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 68 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:elroy_pci_config_data_read " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, size, val);
#line 1536 "trace/trace-hw_pci_host.h"
        } else {
#line 68 "../hw/pci-host/trace-events"
            qemu_log("elroy_pci_config_data_read " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n", addr, size, val);
#line 1540 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_elroy_pci_config_data_read(uint64_t addr, int size, uint64_t val)
{
    if (true) {
        _nocheck__trace_elroy_pci_config_data_read(addr, size, val);
    }
}

#define TRACE_ELROY_PCI_CONFIG_DATA_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ELROY_PCI_CONFIG_DATA_WRITE) || \
    false)

static inline void _nocheck__trace_elroy_pci_config_data_write(uint64_t addr, int size, uint64_t val)
{
    if (trace_event_get_state(TRACE_ELROY_PCI_CONFIG_DATA_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 69 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:elroy_pci_config_data_write " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , addr, size, val);
#line 1567 "trace/trace-hw_pci_host.h"
        } else {
#line 69 "../hw/pci-host/trace-events"
            qemu_log("elroy_pci_config_data_write " "addr 0x%"PRIx64" size %d val 0x%"PRIx64 "\n", addr, size, val);
#line 1571 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_elroy_pci_config_data_write(uint64_t addr, int size, uint64_t val)
{
    if (true) {
        _nocheck__trace_elroy_pci_config_data_write(addr, size, val);
    }
}

#define TRACE_IOSAPIC_REG_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOSAPIC_REG_WRITE) || \
    false)

static inline void _nocheck__trace_iosapic_reg_write(uint64_t reg_select, int size, uint64_t val)
{
    if (trace_event_get_state(TRACE_IOSAPIC_REG_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 70 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:iosapic_reg_write " "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , reg_select, size, val);
#line 1598 "trace/trace-hw_pci_host.h"
        } else {
#line 70 "../hw/pci-host/trace-events"
            qemu_log("iosapic_reg_write " "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64 "\n", reg_select, size, val);
#line 1602 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_iosapic_reg_write(uint64_t reg_select, int size, uint64_t val)
{
    if (true) {
        _nocheck__trace_iosapic_reg_write(reg_select, size, val);
    }
}

#define TRACE_IOSAPIC_REG_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_IOSAPIC_REG_READ) || \
    false)

static inline void _nocheck__trace_iosapic_reg_read(uint64_t reg_select, int size, uint64_t val)
{
    if (trace_event_get_state(TRACE_IOSAPIC_REG_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 71 "../hw/pci-host/trace-events"
            qemu_log("%d@%zu.%06zu:iosapic_reg_read " "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , reg_select, size, val);
#line 1629 "trace/trace-hw_pci_host.h"
        } else {
#line 71 "../hw/pci-host/trace-events"
            qemu_log("iosapic_reg_read " "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64 "\n", reg_select, size, val);
#line 1633 "trace/trace-hw_pci_host.h"
        }
    }
}

static inline void trace_iosapic_reg_read(uint64_t reg_select, int size, uint64_t val)
{
    if (true) {
        _nocheck__trace_iosapic_reg_read(reg_select, size, val);
    }
}
#endif /* TRACE_HW_PCI_HOST_GENERATED_TRACERS_H */