/* This file is autogenerated by tracetool, do not edit. */

#ifndef TRACE_HW_RISCV_GENERATED_TRACERS_H
#define TRACE_HW_RISCV_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_RISCV_IOMMU_NEW_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_FLT_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_PRI_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_DMA_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_MSI_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_MRIF_NOTIFICATION_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_CMD_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_NOTIFIER_ADD_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_NOTIFIER_DEL_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_NOTIFY_INT_VECTOR_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_ICVEC_WRITE_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_ATS_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_ATS_INVAL_EVENT;
extern TraceEvent _TRACE_RISCV_IOMMU_ATS_PRGR_EVENT;
extern uint16_t _TRACE_RISCV_IOMMU_NEW_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_FLT_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_PRI_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_DMA_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_MSI_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_MRIF_NOTIFICATION_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_CMD_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_NOTIFIER_ADD_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_NOTIFIER_DEL_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_NOTIFY_INT_VECTOR_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_ICVEC_WRITE_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_ATS_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_ATS_INVAL_DSTATE;
extern uint16_t _TRACE_RISCV_IOMMU_ATS_PRGR_DSTATE;
#define TRACE_RISCV_IOMMU_NEW_ENABLED 1
#define TRACE_RISCV_IOMMU_FLT_ENABLED 1
#define TRACE_RISCV_IOMMU_PRI_ENABLED 1
#define TRACE_RISCV_IOMMU_DMA_ENABLED 1
#define TRACE_RISCV_IOMMU_MSI_ENABLED 1
#define TRACE_RISCV_IOMMU_MRIF_NOTIFICATION_ENABLED 1
#define TRACE_RISCV_IOMMU_CMD_ENABLED 1
#define TRACE_RISCV_IOMMU_NOTIFIER_ADD_ENABLED 1
#define TRACE_RISCV_IOMMU_NOTIFIER_DEL_ENABLED 1
#define TRACE_RISCV_IOMMU_NOTIFY_INT_VECTOR_ENABLED 1
#define TRACE_RISCV_IOMMU_ICVEC_WRITE_ENABLED 1
#define TRACE_RISCV_IOMMU_ATS_ENABLED 1
#define TRACE_RISCV_IOMMU_ATS_INVAL_ENABLED 1
#define TRACE_RISCV_IOMMU_ATS_PRGR_ENABLED 1
#include "qemu/log-for-trace.h"
#include "qemu/error-report.h"


#define TRACE_RISCV_IOMMU_NEW_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_NEW) || \
    false)

static inline void _nocheck__trace_riscv_iommu_new(const char * id, unsigned b, unsigned d, unsigned f)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_NEW) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 4 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_new " "%s: device attached %04x:%02x.%d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, b, d, f);
#line 70 "trace/trace-hw_riscv.h"
        } else {
#line 4 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_new " "%s: device attached %04x:%02x.%d" "\n", id, b, d, f);
#line 74 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_new(const char * id, unsigned b, unsigned d, unsigned f)
{
    if (true) {
        _nocheck__trace_riscv_iommu_new(id, b, d, f);
    }
}

#define TRACE_RISCV_IOMMU_FLT_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_FLT) || \
    false)

static inline void _nocheck__trace_riscv_iommu_flt(const char * id, unsigned b, unsigned d, unsigned f, uint64_t reason, uint64_t iova)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_FLT) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 5 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_flt " "%s: fault %04x:%02x.%u reason: 0x%"PRIx64" iova: 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, b, d, f, reason, iova);
#line 101 "trace/trace-hw_riscv.h"
        } else {
#line 5 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_flt " "%s: fault %04x:%02x.%u reason: 0x%"PRIx64" iova: 0x%"PRIx64 "\n", id, b, d, f, reason, iova);
#line 105 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_flt(const char * id, unsigned b, unsigned d, unsigned f, uint64_t reason, uint64_t iova)
{
    if (true) {
        _nocheck__trace_riscv_iommu_flt(id, b, d, f, reason, iova);
    }
}

#define TRACE_RISCV_IOMMU_PRI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_PRI) || \
    false)

static inline void _nocheck__trace_riscv_iommu_pri(const char * id, unsigned b, unsigned d, unsigned f, uint64_t iova)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_PRI) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 6 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_pri " "%s: page request %04x:%02x.%u iova: 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, b, d, f, iova);
#line 132 "trace/trace-hw_riscv.h"
        } else {
#line 6 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_pri " "%s: page request %04x:%02x.%u iova: 0x%"PRIx64 "\n", id, b, d, f, iova);
#line 136 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_pri(const char * id, unsigned b, unsigned d, unsigned f, uint64_t iova)
{
    if (true) {
        _nocheck__trace_riscv_iommu_pri(id, b, d, f, iova);
    }
}

#define TRACE_RISCV_IOMMU_DMA_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_DMA) || \
    false)

static inline void _nocheck__trace_riscv_iommu_dma(const char * id, unsigned b, unsigned d, unsigned f, unsigned pasid, const char * dir, uint64_t iova, uint64_t phys)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_DMA) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 7 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_dma " "%s: translate %04x:%02x.%u #%u %s 0x%"PRIx64" -> 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, b, d, f, pasid, dir, iova, phys);
#line 163 "trace/trace-hw_riscv.h"
        } else {
#line 7 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_dma " "%s: translate %04x:%02x.%u #%u %s 0x%"PRIx64" -> 0x%"PRIx64 "\n", id, b, d, f, pasid, dir, iova, phys);
#line 167 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_dma(const char * id, unsigned b, unsigned d, unsigned f, unsigned pasid, const char * dir, uint64_t iova, uint64_t phys)
{
    if (true) {
        _nocheck__trace_riscv_iommu_dma(id, b, d, f, pasid, dir, iova, phys);
    }
}

#define TRACE_RISCV_IOMMU_MSI_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_MSI) || \
    false)

static inline void _nocheck__trace_riscv_iommu_msi(const char * id, unsigned b, unsigned d, unsigned f, uint64_t iova, uint64_t phys)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_MSI) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 8 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_msi " "%s: translate %04x:%02x.%u MSI 0x%"PRIx64" -> 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, b, d, f, iova, phys);
#line 194 "trace/trace-hw_riscv.h"
        } else {
#line 8 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_msi " "%s: translate %04x:%02x.%u MSI 0x%"PRIx64" -> 0x%"PRIx64 "\n", id, b, d, f, iova, phys);
#line 198 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_msi(const char * id, unsigned b, unsigned d, unsigned f, uint64_t iova, uint64_t phys)
{
    if (true) {
        _nocheck__trace_riscv_iommu_msi(id, b, d, f, iova, phys);
    }
}

#define TRACE_RISCV_IOMMU_MRIF_NOTIFICATION_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_MRIF_NOTIFICATION) || \
    false)

static inline void _nocheck__trace_riscv_iommu_mrif_notification(const char * id, uint32_t nid, uint64_t phys)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_MRIF_NOTIFICATION) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 9 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_mrif_notification " "%s: sent MRIF notification 0x%x to 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, nid, phys);
#line 225 "trace/trace-hw_riscv.h"
        } else {
#line 9 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_mrif_notification " "%s: sent MRIF notification 0x%x to 0x%"PRIx64 "\n", id, nid, phys);
#line 229 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_mrif_notification(const char * id, uint32_t nid, uint64_t phys)
{
    if (true) {
        _nocheck__trace_riscv_iommu_mrif_notification(id, nid, phys);
    }
}

#define TRACE_RISCV_IOMMU_CMD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_CMD) || \
    false)

static inline void _nocheck__trace_riscv_iommu_cmd(const char * id, uint64_t l, uint64_t u)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_CMD) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 10 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_cmd " "%s: command 0x%"PRIx64" 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, l, u);
#line 256 "trace/trace-hw_riscv.h"
        } else {
#line 10 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_cmd " "%s: command 0x%"PRIx64" 0x%"PRIx64 "\n", id, l, u);
#line 260 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_cmd(const char * id, uint64_t l, uint64_t u)
{
    if (true) {
        _nocheck__trace_riscv_iommu_cmd(id, l, u);
    }
}

#define TRACE_RISCV_IOMMU_NOTIFIER_ADD_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_NOTIFIER_ADD) || \
    false)

static inline void _nocheck__trace_riscv_iommu_notifier_add(const char * id)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_NOTIFIER_ADD) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 11 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_notifier_add " "%s: dev-iotlb notifier added" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id);
#line 287 "trace/trace-hw_riscv.h"
        } else {
#line 11 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_notifier_add " "%s: dev-iotlb notifier added" "\n", id);
#line 291 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_notifier_add(const char * id)
{
    if (true) {
        _nocheck__trace_riscv_iommu_notifier_add(id);
    }
}

#define TRACE_RISCV_IOMMU_NOTIFIER_DEL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_NOTIFIER_DEL) || \
    false)

static inline void _nocheck__trace_riscv_iommu_notifier_del(const char * id)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_NOTIFIER_DEL) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 12 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_notifier_del " "%s: dev-iotlb notifier removed" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id);
#line 318 "trace/trace-hw_riscv.h"
        } else {
#line 12 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_notifier_del " "%s: dev-iotlb notifier removed" "\n", id);
#line 322 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_notifier_del(const char * id)
{
    if (true) {
        _nocheck__trace_riscv_iommu_notifier_del(id);
    }
}

#define TRACE_RISCV_IOMMU_NOTIFY_INT_VECTOR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_NOTIFY_INT_VECTOR) || \
    false)

static inline void _nocheck__trace_riscv_iommu_notify_int_vector(uint32_t cause, uint32_t vector)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_NOTIFY_INT_VECTOR) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 13 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_notify_int_vector " "Interrupt cause 0x%x sent via vector 0x%x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , cause, vector);
#line 349 "trace/trace-hw_riscv.h"
        } else {
#line 13 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_notify_int_vector " "Interrupt cause 0x%x sent via vector 0x%x" "\n", cause, vector);
#line 353 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_notify_int_vector(uint32_t cause, uint32_t vector)
{
    if (true) {
        _nocheck__trace_riscv_iommu_notify_int_vector(cause, vector);
    }
}

#define TRACE_RISCV_IOMMU_ICVEC_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_ICVEC_WRITE) || \
    false)

static inline void _nocheck__trace_riscv_iommu_icvec_write(uint32_t orig, uint32_t actual)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_ICVEC_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 14 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_icvec_write " "ICVEC write: incoming 0x%x actual 0x%x" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , orig, actual);
#line 380 "trace/trace-hw_riscv.h"
        } else {
#line 14 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_icvec_write " "ICVEC write: incoming 0x%x actual 0x%x" "\n", orig, actual);
#line 384 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_icvec_write(uint32_t orig, uint32_t actual)
{
    if (true) {
        _nocheck__trace_riscv_iommu_icvec_write(orig, actual);
    }
}

#define TRACE_RISCV_IOMMU_ATS_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_ATS) || \
    false)

static inline void _nocheck__trace_riscv_iommu_ats(const char * id, unsigned b, unsigned d, unsigned f, uint64_t iova)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_ATS) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 15 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_ats " "%s: translate request %04x:%02x.%u iova: 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id, b, d, f, iova);
#line 411 "trace/trace-hw_riscv.h"
        } else {
#line 15 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_ats " "%s: translate request %04x:%02x.%u iova: 0x%"PRIx64 "\n", id, b, d, f, iova);
#line 415 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_ats(const char * id, unsigned b, unsigned d, unsigned f, uint64_t iova)
{
    if (true) {
        _nocheck__trace_riscv_iommu_ats(id, b, d, f, iova);
    }
}

#define TRACE_RISCV_IOMMU_ATS_INVAL_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_ATS_INVAL) || \
    false)

static inline void _nocheck__trace_riscv_iommu_ats_inval(const char * id)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_ATS_INVAL) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 16 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_ats_inval " "%s: dev-iotlb invalidate" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id);
#line 442 "trace/trace-hw_riscv.h"
        } else {
#line 16 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_ats_inval " "%s: dev-iotlb invalidate" "\n", id);
#line 446 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_ats_inval(const char * id)
{
    if (true) {
        _nocheck__trace_riscv_iommu_ats_inval(id);
    }
}

#define TRACE_RISCV_IOMMU_ATS_PRGR_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_IOMMU_ATS_PRGR) || \
    false)

static inline void _nocheck__trace_riscv_iommu_ats_prgr(const char * id)
{
    if (trace_event_get_state(TRACE_RISCV_IOMMU_ATS_PRGR) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 17 "../hw/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_iommu_ats_prgr " "%s: dev-iotlb page request group response" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , id);
#line 473 "trace/trace-hw_riscv.h"
        } else {
#line 17 "../hw/riscv/trace-events"
            qemu_log("riscv_iommu_ats_prgr " "%s: dev-iotlb page request group response" "\n", id);
#line 477 "trace/trace-hw_riscv.h"
        }
    }
}

static inline void trace_riscv_iommu_ats_prgr(const char * id)
{
    if (true) {
        _nocheck__trace_riscv_iommu_ats_prgr(id);
    }
}
#endif /* TRACE_HW_RISCV_GENERATED_TRACERS_H */