/* This file is autogenerated by tracetool, do not edit. */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_sparc.h"

uint16_t _TRACE_SUN4M_CPU_SET_IRQ_RAISE_DSTATE;
uint16_t _TRACE_SUN4M_CPU_SET_IRQ_LOWER_DSTATE;
uint16_t _TRACE_SUN4M_IOMMU_MEM_READL_DSTATE;
uint16_t _TRACE_SUN4M_IOMMU_MEM_WRITEL_DSTATE;
uint16_t _TRACE_SUN4M_IOMMU_MEM_WRITEL_CTRL_DSTATE;
uint16_t _TRACE_SUN4M_IOMMU_MEM_WRITEL_TLBFLUSH_DSTATE;
uint16_t _TRACE_SUN4M_IOMMU_MEM_WRITEL_PGFLUSH_DSTATE;
uint16_t _TRACE_SUN4M_IOMMU_PAGE_GET_FLAGS_DSTATE;
uint16_t _TRACE_SUN4M_IOMMU_TRANSLATE_PA_DSTATE;
uint16_t _TRACE_SUN4M_IOMMU_BAD_ADDR_DSTATE;
uint16_t _TRACE_LEON3_SET_IRQ_DSTATE;
uint16_t _TRACE_LEON3_RESET_IRQ_DSTATE;
uint16_t _TRACE_INT_HELPER_ICACHE_FREEZE_DSTATE;
uint16_t _TRACE_INT_HELPER_DCACHE_FREEZE_DSTATE;
TraceEvent _TRACE_SUN4M_CPU_SET_IRQ_RAISE_EVENT = {
    .id = 0,
    .name = "sun4m_cpu_set_irq_raise",
    .sstate = TRACE_SUN4M_CPU_SET_IRQ_RAISE_ENABLED,
    .dstate = &_TRACE_SUN4M_CPU_SET_IRQ_RAISE_DSTATE 
};
TraceEvent _TRACE_SUN4M_CPU_SET_IRQ_LOWER_EVENT = {
    .id = 0,
    .name = "sun4m_cpu_set_irq_lower",
    .sstate = TRACE_SUN4M_CPU_SET_IRQ_LOWER_ENABLED,
    .dstate = &_TRACE_SUN4M_CPU_SET_IRQ_LOWER_DSTATE 
};
TraceEvent _TRACE_SUN4M_IOMMU_MEM_READL_EVENT = {
    .id = 0,
    .name = "sun4m_iommu_mem_readl",
    .sstate = TRACE_SUN4M_IOMMU_MEM_READL_ENABLED,
    .dstate = &_TRACE_SUN4M_IOMMU_MEM_READL_DSTATE 
};
TraceEvent _TRACE_SUN4M_IOMMU_MEM_WRITEL_EVENT = {
    .id = 0,
    .name = "sun4m_iommu_mem_writel",
    .sstate = TRACE_SUN4M_IOMMU_MEM_WRITEL_ENABLED,
    .dstate = &_TRACE_SUN4M_IOMMU_MEM_WRITEL_DSTATE 
};
TraceEvent _TRACE_SUN4M_IOMMU_MEM_WRITEL_CTRL_EVENT = {
    .id = 0,
    .name = "sun4m_iommu_mem_writel_ctrl",
    .sstate = TRACE_SUN4M_IOMMU_MEM_WRITEL_CTRL_ENABLED,
    .dstate = &_TRACE_SUN4M_IOMMU_MEM_WRITEL_CTRL_DSTATE 
};
TraceEvent _TRACE_SUN4M_IOMMU_MEM_WRITEL_TLBFLUSH_EVENT = {
    .id = 0,
    .name = "sun4m_iommu_mem_writel_tlbflush",
    .sstate = TRACE_SUN4M_IOMMU_MEM_WRITEL_TLBFLUSH_ENABLED,
    .dstate = &_TRACE_SUN4M_IOMMU_MEM_WRITEL_TLBFLUSH_DSTATE 
};
TraceEvent _TRACE_SUN4M_IOMMU_MEM_WRITEL_PGFLUSH_EVENT = {
    .id = 0,
    .name = "sun4m_iommu_mem_writel_pgflush",
    .sstate = TRACE_SUN4M_IOMMU_MEM_WRITEL_PGFLUSH_ENABLED,
    .dstate = &_TRACE_SUN4M_IOMMU_MEM_WRITEL_PGFLUSH_DSTATE 
};
TraceEvent _TRACE_SUN4M_IOMMU_PAGE_GET_FLAGS_EVENT = {
    .id = 0,
    .name = "sun4m_iommu_page_get_flags",
    .sstate = TRACE_SUN4M_IOMMU_PAGE_GET_FLAGS_ENABLED,
    .dstate = &_TRACE_SUN4M_IOMMU_PAGE_GET_FLAGS_DSTATE 
};
TraceEvent _TRACE_SUN4M_IOMMU_TRANSLATE_PA_EVENT = {
    .id = 0,
    .name = "sun4m_iommu_translate_pa",
    .sstate = TRACE_SUN4M_IOMMU_TRANSLATE_PA_ENABLED,
    .dstate = &_TRACE_SUN4M_IOMMU_TRANSLATE_PA_DSTATE 
};
TraceEvent _TRACE_SUN4M_IOMMU_BAD_ADDR_EVENT = {
    .id = 0,
    .name = "sun4m_iommu_bad_addr",
    .sstate = TRACE_SUN4M_IOMMU_BAD_ADDR_ENABLED,
    .dstate = &_TRACE_SUN4M_IOMMU_BAD_ADDR_DSTATE 
};
TraceEvent _TRACE_LEON3_SET_IRQ_EVENT = {
    .id = 0,
    .name = "leon3_set_irq",
    .sstate = TRACE_LEON3_SET_IRQ_ENABLED,
    .dstate = &_TRACE_LEON3_SET_IRQ_DSTATE 
};
TraceEvent _TRACE_LEON3_RESET_IRQ_EVENT = {
    .id = 0,
    .name = "leon3_reset_irq",
    .sstate = TRACE_LEON3_RESET_IRQ_ENABLED,
    .dstate = &_TRACE_LEON3_RESET_IRQ_DSTATE 
};
TraceEvent _TRACE_INT_HELPER_ICACHE_FREEZE_EVENT = {
    .id = 0,
    .name = "int_helper_icache_freeze",
    .sstate = TRACE_INT_HELPER_ICACHE_FREEZE_ENABLED,
    .dstate = &_TRACE_INT_HELPER_ICACHE_FREEZE_DSTATE 
};
TraceEvent _TRACE_INT_HELPER_DCACHE_FREEZE_EVENT = {
    .id = 0,
    .name = "int_helper_dcache_freeze",
    .sstate = TRACE_INT_HELPER_DCACHE_FREEZE_ENABLED,
    .dstate = &_TRACE_INT_HELPER_DCACHE_FREEZE_DSTATE 
};
TraceEvent *hw_sparc_trace_events[] = {
    &_TRACE_SUN4M_CPU_SET_IRQ_RAISE_EVENT,
    &_TRACE_SUN4M_CPU_SET_IRQ_LOWER_EVENT,
    &_TRACE_SUN4M_IOMMU_MEM_READL_EVENT,
    &_TRACE_SUN4M_IOMMU_MEM_WRITEL_EVENT,
    &_TRACE_SUN4M_IOMMU_MEM_WRITEL_CTRL_EVENT,
    &_TRACE_SUN4M_IOMMU_MEM_WRITEL_TLBFLUSH_EVENT,
    &_TRACE_SUN4M_IOMMU_MEM_WRITEL_PGFLUSH_EVENT,
    &_TRACE_SUN4M_IOMMU_PAGE_GET_FLAGS_EVENT,
    &_TRACE_SUN4M_IOMMU_TRANSLATE_PA_EVENT,
    &_TRACE_SUN4M_IOMMU_BAD_ADDR_EVENT,
    &_TRACE_LEON3_SET_IRQ_EVENT,
    &_TRACE_LEON3_RESET_IRQ_EVENT,
    &_TRACE_INT_HELPER_ICACHE_FREEZE_EVENT,
    &_TRACE_INT_HELPER_DCACHE_FREEZE_EVENT,
  NULL,
};

static void trace_hw_sparc_register_events(void)
{
    trace_event_register_group(hw_sparc_trace_events);
}
trace_init(trace_hw_sparc_register_events)