/* This file is autogenerated by tracetool, do not edit. */ #include "qemu/osdep.h" #include "qemu/module.h" #include "trace-hw_ssi.h" uint16_t _TRACE_ASPEED_SMC_FLASH_SET_SEGMENT_DSTATE; uint16_t _TRACE_ASPEED_SMC_FLASH_READ_DSTATE; uint16_t _TRACE_ASPEED_SMC_DO_SNOOP_DSTATE; uint16_t _TRACE_ASPEED_SMC_FLASH_WRITE_DSTATE; uint16_t _TRACE_ASPEED_SMC_READ_DSTATE; uint16_t _TRACE_ASPEED_SMC_DMA_CHECKSUM_DSTATE; uint16_t _TRACE_ASPEED_SMC_DMA_RW_DSTATE; uint16_t _TRACE_ASPEED_SMC_WRITE_DSTATE; uint16_t _TRACE_ASPEED_SMC_FLASH_SELECT_DSTATE; uint16_t _TRACE_NPCM7XX_FIU_ENTER_RESET_DSTATE; uint16_t _TRACE_NPCM7XX_FIU_HOLD_RESET_DSTATE; uint16_t _TRACE_NPCM7XX_FIU_SELECT_DSTATE; uint16_t _TRACE_NPCM7XX_FIU_DESELECT_DSTATE; uint16_t _TRACE_NPCM7XX_FIU_CTRL_READ_DSTATE; uint16_t _TRACE_NPCM7XX_FIU_CTRL_WRITE_DSTATE; uint16_t _TRACE_NPCM7XX_FIU_FLASH_READ_DSTATE; uint16_t _TRACE_NPCM7XX_FIU_FLASH_WRITE_DSTATE; uint16_t _TRACE_NPCM_PSPI_ENTER_RESET_DSTATE; uint16_t _TRACE_NPCM_PSPI_CTRL_READ_DSTATE; uint16_t _TRACE_NPCM_PSPI_CTRL_WRITE_DSTATE; uint16_t _TRACE_IBEX_SPI_HOST_RESET_DSTATE; uint16_t _TRACE_IBEX_SPI_HOST_TRANSFER_DSTATE; uint16_t _TRACE_IBEX_SPI_HOST_WRITE_DSTATE; uint16_t _TRACE_IBEX_SPI_HOST_READ_DSTATE; uint16_t _TRACE_PNV_SPI_READ_DSTATE; uint16_t _TRACE_PNV_SPI_WRITE_DSTATE; uint16_t _TRACE_PNV_SPI_READ_RDR_DSTATE; uint16_t _TRACE_PNV_SPI_WRITE_TDR_DSTATE; uint16_t _TRACE_PNV_SPI_START_SEQUENCER_DSTATE; uint16_t _TRACE_PNV_SPI_RESET_DSTATE; uint16_t _TRACE_PNV_SPI_SEQUENCER_OP_DSTATE; uint16_t _TRACE_PNV_SPI_SHIFTER_STATING_DSTATE; uint16_t _TRACE_PNV_SPI_SHIFTER_DONE_DSTATE; uint16_t _TRACE_PNV_SPI_LOG_NCOUNTS_DSTATE; uint16_t _TRACE_PNV_SPI_TX_APPEND_DSTATE; uint16_t _TRACE_PNV_SPI_TX_APPEND_FF_DSTATE; uint16_t _TRACE_PNV_SPI_TX_REQUEST_DSTATE; uint16_t _TRACE_PNV_SPI_RX_RECEIVED_DSTATE; uint16_t _TRACE_PNV_SPI_RX_READ_N1FRAME_DSTATE; uint16_t _TRACE_PNV_SPI_RX_READ_N2FRAME_DSTATE; uint16_t _TRACE_PNV_SPI_SHIFT_RX_DSTATE; uint16_t _TRACE_PNV_SPI_SEQUENCER_STOP_REQUESTED_DSTATE; uint16_t _TRACE_PNV_SPI_RDR_MATCH_DSTATE; uint16_t _TRACE_ALLWINNER_A10_SPI_UPDATE_IRQ_DSTATE; uint16_t _TRACE_ALLWINNER_A10_SPI_FLUSH_TXFIFO_BEGIN_DSTATE; uint16_t _TRACE_ALLWINNER_A10_SPI_FLUSH_TXFIFO_END_DSTATE; uint16_t _TRACE_ALLWINNER_A10_SPI_BURST_LENGTH_DSTATE; uint16_t _TRACE_ALLWINNER_A10_SPI_TX_DSTATE; uint16_t _TRACE_ALLWINNER_A10_SPI_RX_DSTATE; uint16_t _TRACE_ALLWINNER_A10_SPI_READ_DSTATE; uint16_t _TRACE_ALLWINNER_A10_SPI_WRITE_DSTATE; TraceEvent _TRACE_ASPEED_SMC_FLASH_SET_SEGMENT_EVENT = { .id = 0, .name = "aspeed_smc_flash_set_segment", .sstate = TRACE_ASPEED_SMC_FLASH_SET_SEGMENT_ENABLED, .dstate = &_TRACE_ASPEED_SMC_FLASH_SET_SEGMENT_DSTATE }; TraceEvent _TRACE_ASPEED_SMC_FLASH_READ_EVENT = { .id = 0, .name = "aspeed_smc_flash_read", .sstate = TRACE_ASPEED_SMC_FLASH_READ_ENABLED, .dstate = &_TRACE_ASPEED_SMC_FLASH_READ_DSTATE }; TraceEvent _TRACE_ASPEED_SMC_DO_SNOOP_EVENT = { .id = 0, .name = "aspeed_smc_do_snoop", .sstate = TRACE_ASPEED_SMC_DO_SNOOP_ENABLED, .dstate = &_TRACE_ASPEED_SMC_DO_SNOOP_DSTATE }; TraceEvent _TRACE_ASPEED_SMC_FLASH_WRITE_EVENT = { .id = 0, .name = "aspeed_smc_flash_write", .sstate = TRACE_ASPEED_SMC_FLASH_WRITE_ENABLED, .dstate = &_TRACE_ASPEED_SMC_FLASH_WRITE_DSTATE }; TraceEvent _TRACE_ASPEED_SMC_READ_EVENT = { .id = 0, .name = "aspeed_smc_read", .sstate = TRACE_ASPEED_SMC_READ_ENABLED, .dstate = &_TRACE_ASPEED_SMC_READ_DSTATE }; TraceEvent _TRACE_ASPEED_SMC_DMA_CHECKSUM_EVENT = { .id = 0, .name = "aspeed_smc_dma_checksum", .sstate = TRACE_ASPEED_SMC_DMA_CHECKSUM_ENABLED, .dstate = &_TRACE_ASPEED_SMC_DMA_CHECKSUM_DSTATE }; TraceEvent _TRACE_ASPEED_SMC_DMA_RW_EVENT = { .id = 0, .name = "aspeed_smc_dma_rw", .sstate = TRACE_ASPEED_SMC_DMA_RW_ENABLED, .dstate = &_TRACE_ASPEED_SMC_DMA_RW_DSTATE }; TraceEvent _TRACE_ASPEED_SMC_WRITE_EVENT = { .id = 0, .name = "aspeed_smc_write", .sstate = TRACE_ASPEED_SMC_WRITE_ENABLED, .dstate = &_TRACE_ASPEED_SMC_WRITE_DSTATE }; TraceEvent _TRACE_ASPEED_SMC_FLASH_SELECT_EVENT = { .id = 0, .name = "aspeed_smc_flash_select", .sstate = TRACE_ASPEED_SMC_FLASH_SELECT_ENABLED, .dstate = &_TRACE_ASPEED_SMC_FLASH_SELECT_DSTATE }; TraceEvent _TRACE_NPCM7XX_FIU_ENTER_RESET_EVENT = { .id = 0, .name = "npcm7xx_fiu_enter_reset", .sstate = TRACE_NPCM7XX_FIU_ENTER_RESET_ENABLED, .dstate = &_TRACE_NPCM7XX_FIU_ENTER_RESET_DSTATE }; TraceEvent _TRACE_NPCM7XX_FIU_HOLD_RESET_EVENT = { .id = 0, .name = "npcm7xx_fiu_hold_reset", .sstate = TRACE_NPCM7XX_FIU_HOLD_RESET_ENABLED, .dstate = &_TRACE_NPCM7XX_FIU_HOLD_RESET_DSTATE }; TraceEvent _TRACE_NPCM7XX_FIU_SELECT_EVENT = { .id = 0, .name = "npcm7xx_fiu_select", .sstate = TRACE_NPCM7XX_FIU_SELECT_ENABLED, .dstate = &_TRACE_NPCM7XX_FIU_SELECT_DSTATE }; TraceEvent _TRACE_NPCM7XX_FIU_DESELECT_EVENT = { .id = 0, .name = "npcm7xx_fiu_deselect", .sstate = TRACE_NPCM7XX_FIU_DESELECT_ENABLED, .dstate = &_TRACE_NPCM7XX_FIU_DESELECT_DSTATE }; TraceEvent _TRACE_NPCM7XX_FIU_CTRL_READ_EVENT = { .id = 0, .name = "npcm7xx_fiu_ctrl_read", .sstate = TRACE_NPCM7XX_FIU_CTRL_READ_ENABLED, .dstate = &_TRACE_NPCM7XX_FIU_CTRL_READ_DSTATE }; TraceEvent _TRACE_NPCM7XX_FIU_CTRL_WRITE_EVENT = { .id = 0, .name = "npcm7xx_fiu_ctrl_write", .sstate = TRACE_NPCM7XX_FIU_CTRL_WRITE_ENABLED, .dstate = &_TRACE_NPCM7XX_FIU_CTRL_WRITE_DSTATE }; TraceEvent _TRACE_NPCM7XX_FIU_FLASH_READ_EVENT = { .id = 0, .name = "npcm7xx_fiu_flash_read", .sstate = TRACE_NPCM7XX_FIU_FLASH_READ_ENABLED, .dstate = &_TRACE_NPCM7XX_FIU_FLASH_READ_DSTATE }; TraceEvent _TRACE_NPCM7XX_FIU_FLASH_WRITE_EVENT = { .id = 0, .name = "npcm7xx_fiu_flash_write", .sstate = TRACE_NPCM7XX_FIU_FLASH_WRITE_ENABLED, .dstate = &_TRACE_NPCM7XX_FIU_FLASH_WRITE_DSTATE }; TraceEvent _TRACE_NPCM_PSPI_ENTER_RESET_EVENT = { .id = 0, .name = "npcm_pspi_enter_reset", .sstate = TRACE_NPCM_PSPI_ENTER_RESET_ENABLED, .dstate = &_TRACE_NPCM_PSPI_ENTER_RESET_DSTATE }; TraceEvent _TRACE_NPCM_PSPI_CTRL_READ_EVENT = { .id = 0, .name = "npcm_pspi_ctrl_read", .sstate = TRACE_NPCM_PSPI_CTRL_READ_ENABLED, .dstate = &_TRACE_NPCM_PSPI_CTRL_READ_DSTATE }; TraceEvent _TRACE_NPCM_PSPI_CTRL_WRITE_EVENT = { .id = 0, .name = "npcm_pspi_ctrl_write", .sstate = TRACE_NPCM_PSPI_CTRL_WRITE_ENABLED, .dstate = &_TRACE_NPCM_PSPI_CTRL_WRITE_DSTATE }; TraceEvent _TRACE_IBEX_SPI_HOST_RESET_EVENT = { .id = 0, .name = "ibex_spi_host_reset", .sstate = TRACE_IBEX_SPI_HOST_RESET_ENABLED, .dstate = &_TRACE_IBEX_SPI_HOST_RESET_DSTATE }; TraceEvent _TRACE_IBEX_SPI_HOST_TRANSFER_EVENT = { .id = 0, .name = "ibex_spi_host_transfer", .sstate = TRACE_IBEX_SPI_HOST_TRANSFER_ENABLED, .dstate = &_TRACE_IBEX_SPI_HOST_TRANSFER_DSTATE }; TraceEvent _TRACE_IBEX_SPI_HOST_WRITE_EVENT = { .id = 0, .name = "ibex_spi_host_write", .sstate = TRACE_IBEX_SPI_HOST_WRITE_ENABLED, .dstate = &_TRACE_IBEX_SPI_HOST_WRITE_DSTATE }; TraceEvent _TRACE_IBEX_SPI_HOST_READ_EVENT = { .id = 0, .name = "ibex_spi_host_read", .sstate = TRACE_IBEX_SPI_HOST_READ_ENABLED, .dstate = &_TRACE_IBEX_SPI_HOST_READ_DSTATE }; TraceEvent _TRACE_PNV_SPI_READ_EVENT = { .id = 0, .name = "pnv_spi_read", .sstate = TRACE_PNV_SPI_READ_ENABLED, .dstate = &_TRACE_PNV_SPI_READ_DSTATE }; TraceEvent _TRACE_PNV_SPI_WRITE_EVENT = { .id = 0, .name = "pnv_spi_write", .sstate = TRACE_PNV_SPI_WRITE_ENABLED, .dstate = &_TRACE_PNV_SPI_WRITE_DSTATE }; TraceEvent _TRACE_PNV_SPI_READ_RDR_EVENT = { .id = 0, .name = "pnv_spi_read_RDR", .sstate = TRACE_PNV_SPI_READ_RDR_ENABLED, .dstate = &_TRACE_PNV_SPI_READ_RDR_DSTATE }; TraceEvent _TRACE_PNV_SPI_WRITE_TDR_EVENT = { .id = 0, .name = "pnv_spi_write_TDR", .sstate = TRACE_PNV_SPI_WRITE_TDR_ENABLED, .dstate = &_TRACE_PNV_SPI_WRITE_TDR_DSTATE }; TraceEvent _TRACE_PNV_SPI_START_SEQUENCER_EVENT = { .id = 0, .name = "pnv_spi_start_sequencer", .sstate = TRACE_PNV_SPI_START_SEQUENCER_ENABLED, .dstate = &_TRACE_PNV_SPI_START_SEQUENCER_DSTATE }; TraceEvent _TRACE_PNV_SPI_RESET_EVENT = { .id = 0, .name = "pnv_spi_reset", .sstate = TRACE_PNV_SPI_RESET_ENABLED, .dstate = &_TRACE_PNV_SPI_RESET_DSTATE }; TraceEvent _TRACE_PNV_SPI_SEQUENCER_OP_EVENT = { .id = 0, .name = "pnv_spi_sequencer_op", .sstate = TRACE_PNV_SPI_SEQUENCER_OP_ENABLED, .dstate = &_TRACE_PNV_SPI_SEQUENCER_OP_DSTATE }; TraceEvent _TRACE_PNV_SPI_SHIFTER_STATING_EVENT = { .id = 0, .name = "pnv_spi_shifter_stating", .sstate = TRACE_PNV_SPI_SHIFTER_STATING_ENABLED, .dstate = &_TRACE_PNV_SPI_SHIFTER_STATING_DSTATE }; TraceEvent _TRACE_PNV_SPI_SHIFTER_DONE_EVENT = { .id = 0, .name = "pnv_spi_shifter_done", .sstate = TRACE_PNV_SPI_SHIFTER_DONE_ENABLED, .dstate = &_TRACE_PNV_SPI_SHIFTER_DONE_DSTATE }; TraceEvent _TRACE_PNV_SPI_LOG_NCOUNTS_EVENT = { .id = 0, .name = "pnv_spi_log_Ncounts", .sstate = TRACE_PNV_SPI_LOG_NCOUNTS_ENABLED, .dstate = &_TRACE_PNV_SPI_LOG_NCOUNTS_DSTATE }; TraceEvent _TRACE_PNV_SPI_TX_APPEND_EVENT = { .id = 0, .name = "pnv_spi_tx_append", .sstate = TRACE_PNV_SPI_TX_APPEND_ENABLED, .dstate = &_TRACE_PNV_SPI_TX_APPEND_DSTATE }; TraceEvent _TRACE_PNV_SPI_TX_APPEND_FF_EVENT = { .id = 0, .name = "pnv_spi_tx_append_FF", .sstate = TRACE_PNV_SPI_TX_APPEND_FF_ENABLED, .dstate = &_TRACE_PNV_SPI_TX_APPEND_FF_DSTATE }; TraceEvent _TRACE_PNV_SPI_TX_REQUEST_EVENT = { .id = 0, .name = "pnv_spi_tx_request", .sstate = TRACE_PNV_SPI_TX_REQUEST_ENABLED, .dstate = &_TRACE_PNV_SPI_TX_REQUEST_DSTATE }; TraceEvent _TRACE_PNV_SPI_RX_RECEIVED_EVENT = { .id = 0, .name = "pnv_spi_rx_received", .sstate = TRACE_PNV_SPI_RX_RECEIVED_ENABLED, .dstate = &_TRACE_PNV_SPI_RX_RECEIVED_DSTATE }; TraceEvent _TRACE_PNV_SPI_RX_READ_N1FRAME_EVENT = { .id = 0, .name = "pnv_spi_rx_read_N1frame", .sstate = TRACE_PNV_SPI_RX_READ_N1FRAME_ENABLED, .dstate = &_TRACE_PNV_SPI_RX_READ_N1FRAME_DSTATE }; TraceEvent _TRACE_PNV_SPI_RX_READ_N2FRAME_EVENT = { .id = 0, .name = "pnv_spi_rx_read_N2frame", .sstate = TRACE_PNV_SPI_RX_READ_N2FRAME_ENABLED, .dstate = &_TRACE_PNV_SPI_RX_READ_N2FRAME_DSTATE }; TraceEvent _TRACE_PNV_SPI_SHIFT_RX_EVENT = { .id = 0, .name = "pnv_spi_shift_rx", .sstate = TRACE_PNV_SPI_SHIFT_RX_ENABLED, .dstate = &_TRACE_PNV_SPI_SHIFT_RX_DSTATE }; TraceEvent _TRACE_PNV_SPI_SEQUENCER_STOP_REQUESTED_EVENT = { .id = 0, .name = "pnv_spi_sequencer_stop_requested", .sstate = TRACE_PNV_SPI_SEQUENCER_STOP_REQUESTED_ENABLED, .dstate = &_TRACE_PNV_SPI_SEQUENCER_STOP_REQUESTED_DSTATE }; TraceEvent _TRACE_PNV_SPI_RDR_MATCH_EVENT = { .id = 0, .name = "pnv_spi_RDR_match", .sstate = TRACE_PNV_SPI_RDR_MATCH_ENABLED, .dstate = &_TRACE_PNV_SPI_RDR_MATCH_DSTATE }; TraceEvent _TRACE_ALLWINNER_A10_SPI_UPDATE_IRQ_EVENT = { .id = 0, .name = "allwinner_a10_spi_update_irq", .sstate = TRACE_ALLWINNER_A10_SPI_UPDATE_IRQ_ENABLED, .dstate = &_TRACE_ALLWINNER_A10_SPI_UPDATE_IRQ_DSTATE }; TraceEvent _TRACE_ALLWINNER_A10_SPI_FLUSH_TXFIFO_BEGIN_EVENT = { .id = 0, .name = "allwinner_a10_spi_flush_txfifo_begin", .sstate = TRACE_ALLWINNER_A10_SPI_FLUSH_TXFIFO_BEGIN_ENABLED, .dstate = &_TRACE_ALLWINNER_A10_SPI_FLUSH_TXFIFO_BEGIN_DSTATE }; TraceEvent _TRACE_ALLWINNER_A10_SPI_FLUSH_TXFIFO_END_EVENT = { .id = 0, .name = "allwinner_a10_spi_flush_txfifo_end", .sstate = TRACE_ALLWINNER_A10_SPI_FLUSH_TXFIFO_END_ENABLED, .dstate = &_TRACE_ALLWINNER_A10_SPI_FLUSH_TXFIFO_END_DSTATE }; TraceEvent _TRACE_ALLWINNER_A10_SPI_BURST_LENGTH_EVENT = { .id = 0, .name = "allwinner_a10_spi_burst_length", .sstate = TRACE_ALLWINNER_A10_SPI_BURST_LENGTH_ENABLED, .dstate = &_TRACE_ALLWINNER_A10_SPI_BURST_LENGTH_DSTATE }; TraceEvent _TRACE_ALLWINNER_A10_SPI_TX_EVENT = { .id = 0, .name = "allwinner_a10_spi_tx", .sstate = TRACE_ALLWINNER_A10_SPI_TX_ENABLED, .dstate = &_TRACE_ALLWINNER_A10_SPI_TX_DSTATE }; TraceEvent _TRACE_ALLWINNER_A10_SPI_RX_EVENT = { .id = 0, .name = "allwinner_a10_spi_rx", .sstate = TRACE_ALLWINNER_A10_SPI_RX_ENABLED, .dstate = &_TRACE_ALLWINNER_A10_SPI_RX_DSTATE }; TraceEvent _TRACE_ALLWINNER_A10_SPI_READ_EVENT = { .id = 0, .name = "allwinner_a10_spi_read", .sstate = TRACE_ALLWINNER_A10_SPI_READ_ENABLED, .dstate = &_TRACE_ALLWINNER_A10_SPI_READ_DSTATE }; TraceEvent _TRACE_ALLWINNER_A10_SPI_WRITE_EVENT = { .id = 0, .name = "allwinner_a10_spi_write", .sstate = TRACE_ALLWINNER_A10_SPI_WRITE_ENABLED, .dstate = &_TRACE_ALLWINNER_A10_SPI_WRITE_DSTATE }; TraceEvent *hw_ssi_trace_events[] = { &_TRACE_ASPEED_SMC_FLASH_SET_SEGMENT_EVENT, &_TRACE_ASPEED_SMC_FLASH_READ_EVENT, &_TRACE_ASPEED_SMC_DO_SNOOP_EVENT, &_TRACE_ASPEED_SMC_FLASH_WRITE_EVENT, &_TRACE_ASPEED_SMC_READ_EVENT, &_TRACE_ASPEED_SMC_DMA_CHECKSUM_EVENT, &_TRACE_ASPEED_SMC_DMA_RW_EVENT, &_TRACE_ASPEED_SMC_WRITE_EVENT, &_TRACE_ASPEED_SMC_FLASH_SELECT_EVENT, &_TRACE_NPCM7XX_FIU_ENTER_RESET_EVENT, &_TRACE_NPCM7XX_FIU_HOLD_RESET_EVENT, &_TRACE_NPCM7XX_FIU_SELECT_EVENT, &_TRACE_NPCM7XX_FIU_DESELECT_EVENT, &_TRACE_NPCM7XX_FIU_CTRL_READ_EVENT, &_TRACE_NPCM7XX_FIU_CTRL_WRITE_EVENT, &_TRACE_NPCM7XX_FIU_FLASH_READ_EVENT, &_TRACE_NPCM7XX_FIU_FLASH_WRITE_EVENT, &_TRACE_NPCM_PSPI_ENTER_RESET_EVENT, &_TRACE_NPCM_PSPI_CTRL_READ_EVENT, &_TRACE_NPCM_PSPI_CTRL_WRITE_EVENT, &_TRACE_IBEX_SPI_HOST_RESET_EVENT, &_TRACE_IBEX_SPI_HOST_TRANSFER_EVENT, &_TRACE_IBEX_SPI_HOST_WRITE_EVENT, &_TRACE_IBEX_SPI_HOST_READ_EVENT, &_TRACE_PNV_SPI_READ_EVENT, &_TRACE_PNV_SPI_WRITE_EVENT, &_TRACE_PNV_SPI_READ_RDR_EVENT, &_TRACE_PNV_SPI_WRITE_TDR_EVENT, &_TRACE_PNV_SPI_START_SEQUENCER_EVENT, &_TRACE_PNV_SPI_RESET_EVENT, &_TRACE_PNV_SPI_SEQUENCER_OP_EVENT, &_TRACE_PNV_SPI_SHIFTER_STATING_EVENT, &_TRACE_PNV_SPI_SHIFTER_DONE_EVENT, &_TRACE_PNV_SPI_LOG_NCOUNTS_EVENT, &_TRACE_PNV_SPI_TX_APPEND_EVENT, &_TRACE_PNV_SPI_TX_APPEND_FF_EVENT, &_TRACE_PNV_SPI_TX_REQUEST_EVENT, &_TRACE_PNV_SPI_RX_RECEIVED_EVENT, &_TRACE_PNV_SPI_RX_READ_N1FRAME_EVENT, &_TRACE_PNV_SPI_RX_READ_N2FRAME_EVENT, &_TRACE_PNV_SPI_SHIFT_RX_EVENT, &_TRACE_PNV_SPI_SEQUENCER_STOP_REQUESTED_EVENT, &_TRACE_PNV_SPI_RDR_MATCH_EVENT, &_TRACE_ALLWINNER_A10_SPI_UPDATE_IRQ_EVENT, &_TRACE_ALLWINNER_A10_SPI_FLUSH_TXFIFO_BEGIN_EVENT, &_TRACE_ALLWINNER_A10_SPI_FLUSH_TXFIFO_END_EVENT, &_TRACE_ALLWINNER_A10_SPI_BURST_LENGTH_EVENT, &_TRACE_ALLWINNER_A10_SPI_TX_EVENT, &_TRACE_ALLWINNER_A10_SPI_RX_EVENT, &_TRACE_ALLWINNER_A10_SPI_READ_EVENT, &_TRACE_ALLWINNER_A10_SPI_WRITE_EVENT, NULL, }; static void trace_hw_ssi_register_events(void) { trace_event_register_group(hw_ssi_trace_events); } trace_init(trace_hw_ssi_register_events)