/* This file is autogenerated by tracetool, do not edit. */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "trace-hw_tpm.h"

uint16_t _TRACE_TPM_CRB_MMIO_READ_DSTATE;
uint16_t _TRACE_TPM_CRB_MMIO_WRITE_DSTATE;
uint16_t _TRACE_TPM_TIS_RAISE_IRQ_DSTATE;
uint16_t _TRACE_TPM_TIS_NEW_ACTIVE_LOCALITY_DSTATE;
uint16_t _TRACE_TPM_TIS_ABORT_DSTATE;
uint16_t _TRACE_TPM_TIS_DATA_READ_DSTATE;
uint16_t _TRACE_TPM_TIS_MMIO_READ_DSTATE;
uint16_t _TRACE_TPM_TIS_MMIO_WRITE_DSTATE;
uint16_t _TRACE_TPM_TIS_MMIO_WRITE_LOCTY4_DSTATE;
uint16_t _TRACE_TPM_TIS_MMIO_WRITE_RELEASE_LOCTY_DSTATE;
uint16_t _TRACE_TPM_TIS_MMIO_WRITE_LOCTY_REQ_USE_DSTATE;
uint16_t _TRACE_TPM_TIS_MMIO_WRITE_NEXT_LOCTY_DSTATE;
uint16_t _TRACE_TPM_TIS_MMIO_WRITE_LOCTY_SEIZED_DSTATE;
uint16_t _TRACE_TPM_TIS_MMIO_WRITE_INIT_ABORT_DSTATE;
uint16_t _TRACE_TPM_TIS_MMIO_WRITE_LOWERING_IRQ_DSTATE;
uint16_t _TRACE_TPM_TIS_MMIO_WRITE_DATA2SEND_DSTATE;
uint16_t _TRACE_TPM_TIS_PRE_SAVE_DSTATE;
uint16_t _TRACE_TPM_PPI_MEMSET_DSTATE;
uint16_t _TRACE_TPM_SPAPR_DO_CRQ_DSTATE;
uint16_t _TRACE_TPM_SPAPR_DO_CRQ_CRQ_RESULT_DSTATE;
uint16_t _TRACE_TPM_SPAPR_DO_CRQ_CRQ_COMPLETE_RESULT_DSTATE;
uint16_t _TRACE_TPM_SPAPR_DO_CRQ_TPM_COMMAND_DSTATE;
uint16_t _TRACE_TPM_SPAPR_DO_CRQ_TPM_GET_RTCE_BUFFER_SIZE_DSTATE;
uint16_t _TRACE_TPM_SPAPR_DO_CRQ_GET_VERSION_DSTATE;
uint16_t _TRACE_TPM_SPAPR_DO_CRQ_PREPARE_TO_SUSPEND_DSTATE;
uint16_t _TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_MSG_TYPE_DSTATE;
uint16_t _TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_CRQ_DSTATE;
uint16_t _TRACE_TPM_SPAPR_POST_LOAD_DSTATE;
uint16_t _TRACE_TPM_SPAPR_CAUGHT_RESPONSE_DSTATE;
uint16_t _TRACE_TPM_TIS_I2C_RECV_DSTATE;
uint16_t _TRACE_TPM_TIS_I2C_SEND_DSTATE;
uint16_t _TRACE_TPM_TIS_I2C_EVENT_DSTATE;
uint16_t _TRACE_TPM_TIS_I2C_SEND_REG_DSTATE;
TraceEvent _TRACE_TPM_CRB_MMIO_READ_EVENT = {
    .id = 0,
    .name = "tpm_crb_mmio_read",
    .sstate = TRACE_TPM_CRB_MMIO_READ_ENABLED,
    .dstate = &_TRACE_TPM_CRB_MMIO_READ_DSTATE 
};
TraceEvent _TRACE_TPM_CRB_MMIO_WRITE_EVENT = {
    .id = 0,
    .name = "tpm_crb_mmio_write",
    .sstate = TRACE_TPM_CRB_MMIO_WRITE_ENABLED,
    .dstate = &_TRACE_TPM_CRB_MMIO_WRITE_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_RAISE_IRQ_EVENT = {
    .id = 0,
    .name = "tpm_tis_raise_irq",
    .sstate = TRACE_TPM_TIS_RAISE_IRQ_ENABLED,
    .dstate = &_TRACE_TPM_TIS_RAISE_IRQ_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_NEW_ACTIVE_LOCALITY_EVENT = {
    .id = 0,
    .name = "tpm_tis_new_active_locality",
    .sstate = TRACE_TPM_TIS_NEW_ACTIVE_LOCALITY_ENABLED,
    .dstate = &_TRACE_TPM_TIS_NEW_ACTIVE_LOCALITY_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_ABORT_EVENT = {
    .id = 0,
    .name = "tpm_tis_abort",
    .sstate = TRACE_TPM_TIS_ABORT_ENABLED,
    .dstate = &_TRACE_TPM_TIS_ABORT_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_DATA_READ_EVENT = {
    .id = 0,
    .name = "tpm_tis_data_read",
    .sstate = TRACE_TPM_TIS_DATA_READ_ENABLED,
    .dstate = &_TRACE_TPM_TIS_DATA_READ_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_MMIO_READ_EVENT = {
    .id = 0,
    .name = "tpm_tis_mmio_read",
    .sstate = TRACE_TPM_TIS_MMIO_READ_ENABLED,
    .dstate = &_TRACE_TPM_TIS_MMIO_READ_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_EVENT = {
    .id = 0,
    .name = "tpm_tis_mmio_write",
    .sstate = TRACE_TPM_TIS_MMIO_WRITE_ENABLED,
    .dstate = &_TRACE_TPM_TIS_MMIO_WRITE_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_LOCTY4_EVENT = {
    .id = 0,
    .name = "tpm_tis_mmio_write_locty4",
    .sstate = TRACE_TPM_TIS_MMIO_WRITE_LOCTY4_ENABLED,
    .dstate = &_TRACE_TPM_TIS_MMIO_WRITE_LOCTY4_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_RELEASE_LOCTY_EVENT = {
    .id = 0,
    .name = "tpm_tis_mmio_write_release_locty",
    .sstate = TRACE_TPM_TIS_MMIO_WRITE_RELEASE_LOCTY_ENABLED,
    .dstate = &_TRACE_TPM_TIS_MMIO_WRITE_RELEASE_LOCTY_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_LOCTY_REQ_USE_EVENT = {
    .id = 0,
    .name = "tpm_tis_mmio_write_locty_req_use",
    .sstate = TRACE_TPM_TIS_MMIO_WRITE_LOCTY_REQ_USE_ENABLED,
    .dstate = &_TRACE_TPM_TIS_MMIO_WRITE_LOCTY_REQ_USE_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_NEXT_LOCTY_EVENT = {
    .id = 0,
    .name = "tpm_tis_mmio_write_next_locty",
    .sstate = TRACE_TPM_TIS_MMIO_WRITE_NEXT_LOCTY_ENABLED,
    .dstate = &_TRACE_TPM_TIS_MMIO_WRITE_NEXT_LOCTY_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_LOCTY_SEIZED_EVENT = {
    .id = 0,
    .name = "tpm_tis_mmio_write_locty_seized",
    .sstate = TRACE_TPM_TIS_MMIO_WRITE_LOCTY_SEIZED_ENABLED,
    .dstate = &_TRACE_TPM_TIS_MMIO_WRITE_LOCTY_SEIZED_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_INIT_ABORT_EVENT = {
    .id = 0,
    .name = "tpm_tis_mmio_write_init_abort",
    .sstate = TRACE_TPM_TIS_MMIO_WRITE_INIT_ABORT_ENABLED,
    .dstate = &_TRACE_TPM_TIS_MMIO_WRITE_INIT_ABORT_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_LOWERING_IRQ_EVENT = {
    .id = 0,
    .name = "tpm_tis_mmio_write_lowering_irq",
    .sstate = TRACE_TPM_TIS_MMIO_WRITE_LOWERING_IRQ_ENABLED,
    .dstate = &_TRACE_TPM_TIS_MMIO_WRITE_LOWERING_IRQ_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_MMIO_WRITE_DATA2SEND_EVENT = {
    .id = 0,
    .name = "tpm_tis_mmio_write_data2send",
    .sstate = TRACE_TPM_TIS_MMIO_WRITE_DATA2SEND_ENABLED,
    .dstate = &_TRACE_TPM_TIS_MMIO_WRITE_DATA2SEND_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_PRE_SAVE_EVENT = {
    .id = 0,
    .name = "tpm_tis_pre_save",
    .sstate = TRACE_TPM_TIS_PRE_SAVE_ENABLED,
    .dstate = &_TRACE_TPM_TIS_PRE_SAVE_DSTATE 
};
TraceEvent _TRACE_TPM_PPI_MEMSET_EVENT = {
    .id = 0,
    .name = "tpm_ppi_memset",
    .sstate = TRACE_TPM_PPI_MEMSET_ENABLED,
    .dstate = &_TRACE_TPM_PPI_MEMSET_DSTATE 
};
TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_EVENT = {
    .id = 0,
    .name = "tpm_spapr_do_crq",
    .sstate = TRACE_TPM_SPAPR_DO_CRQ_ENABLED,
    .dstate = &_TRACE_TPM_SPAPR_DO_CRQ_DSTATE 
};
TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_CRQ_RESULT_EVENT = {
    .id = 0,
    .name = "tpm_spapr_do_crq_crq_result",
    .sstate = TRACE_TPM_SPAPR_DO_CRQ_CRQ_RESULT_ENABLED,
    .dstate = &_TRACE_TPM_SPAPR_DO_CRQ_CRQ_RESULT_DSTATE 
};
TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_CRQ_COMPLETE_RESULT_EVENT = {
    .id = 0,
    .name = "tpm_spapr_do_crq_crq_complete_result",
    .sstate = TRACE_TPM_SPAPR_DO_CRQ_CRQ_COMPLETE_RESULT_ENABLED,
    .dstate = &_TRACE_TPM_SPAPR_DO_CRQ_CRQ_COMPLETE_RESULT_DSTATE 
};
TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_TPM_COMMAND_EVENT = {
    .id = 0,
    .name = "tpm_spapr_do_crq_tpm_command",
    .sstate = TRACE_TPM_SPAPR_DO_CRQ_TPM_COMMAND_ENABLED,
    .dstate = &_TRACE_TPM_SPAPR_DO_CRQ_TPM_COMMAND_DSTATE 
};
TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_TPM_GET_RTCE_BUFFER_SIZE_EVENT = {
    .id = 0,
    .name = "tpm_spapr_do_crq_tpm_get_rtce_buffer_size",
    .sstate = TRACE_TPM_SPAPR_DO_CRQ_TPM_GET_RTCE_BUFFER_SIZE_ENABLED,
    .dstate = &_TRACE_TPM_SPAPR_DO_CRQ_TPM_GET_RTCE_BUFFER_SIZE_DSTATE 
};
TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_GET_VERSION_EVENT = {
    .id = 0,
    .name = "tpm_spapr_do_crq_get_version",
    .sstate = TRACE_TPM_SPAPR_DO_CRQ_GET_VERSION_ENABLED,
    .dstate = &_TRACE_TPM_SPAPR_DO_CRQ_GET_VERSION_DSTATE 
};
TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_PREPARE_TO_SUSPEND_EVENT = {
    .id = 0,
    .name = "tpm_spapr_do_crq_prepare_to_suspend",
    .sstate = TRACE_TPM_SPAPR_DO_CRQ_PREPARE_TO_SUSPEND_ENABLED,
    .dstate = &_TRACE_TPM_SPAPR_DO_CRQ_PREPARE_TO_SUSPEND_DSTATE 
};
TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_MSG_TYPE_EVENT = {
    .id = 0,
    .name = "tpm_spapr_do_crq_unknown_msg_type",
    .sstate = TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_MSG_TYPE_ENABLED,
    .dstate = &_TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_MSG_TYPE_DSTATE 
};
TraceEvent _TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_CRQ_EVENT = {
    .id = 0,
    .name = "tpm_spapr_do_crq_unknown_crq",
    .sstate = TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_CRQ_ENABLED,
    .dstate = &_TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_CRQ_DSTATE 
};
TraceEvent _TRACE_TPM_SPAPR_POST_LOAD_EVENT = {
    .id = 0,
    .name = "tpm_spapr_post_load",
    .sstate = TRACE_TPM_SPAPR_POST_LOAD_ENABLED,
    .dstate = &_TRACE_TPM_SPAPR_POST_LOAD_DSTATE 
};
TraceEvent _TRACE_TPM_SPAPR_CAUGHT_RESPONSE_EVENT = {
    .id = 0,
    .name = "tpm_spapr_caught_response",
    .sstate = TRACE_TPM_SPAPR_CAUGHT_RESPONSE_ENABLED,
    .dstate = &_TRACE_TPM_SPAPR_CAUGHT_RESPONSE_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_I2C_RECV_EVENT = {
    .id = 0,
    .name = "tpm_tis_i2c_recv",
    .sstate = TRACE_TPM_TIS_I2C_RECV_ENABLED,
    .dstate = &_TRACE_TPM_TIS_I2C_RECV_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_I2C_SEND_EVENT = {
    .id = 0,
    .name = "tpm_tis_i2c_send",
    .sstate = TRACE_TPM_TIS_I2C_SEND_ENABLED,
    .dstate = &_TRACE_TPM_TIS_I2C_SEND_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_I2C_EVENT_EVENT = {
    .id = 0,
    .name = "tpm_tis_i2c_event",
    .sstate = TRACE_TPM_TIS_I2C_EVENT_ENABLED,
    .dstate = &_TRACE_TPM_TIS_I2C_EVENT_DSTATE 
};
TraceEvent _TRACE_TPM_TIS_I2C_SEND_REG_EVENT = {
    .id = 0,
    .name = "tpm_tis_i2c_send_reg",
    .sstate = TRACE_TPM_TIS_I2C_SEND_REG_ENABLED,
    .dstate = &_TRACE_TPM_TIS_I2C_SEND_REG_DSTATE 
};
TraceEvent *hw_tpm_trace_events[] = {
    &_TRACE_TPM_CRB_MMIO_READ_EVENT,
    &_TRACE_TPM_CRB_MMIO_WRITE_EVENT,
    &_TRACE_TPM_TIS_RAISE_IRQ_EVENT,
    &_TRACE_TPM_TIS_NEW_ACTIVE_LOCALITY_EVENT,
    &_TRACE_TPM_TIS_ABORT_EVENT,
    &_TRACE_TPM_TIS_DATA_READ_EVENT,
    &_TRACE_TPM_TIS_MMIO_READ_EVENT,
    &_TRACE_TPM_TIS_MMIO_WRITE_EVENT,
    &_TRACE_TPM_TIS_MMIO_WRITE_LOCTY4_EVENT,
    &_TRACE_TPM_TIS_MMIO_WRITE_RELEASE_LOCTY_EVENT,
    &_TRACE_TPM_TIS_MMIO_WRITE_LOCTY_REQ_USE_EVENT,
    &_TRACE_TPM_TIS_MMIO_WRITE_NEXT_LOCTY_EVENT,
    &_TRACE_TPM_TIS_MMIO_WRITE_LOCTY_SEIZED_EVENT,
    &_TRACE_TPM_TIS_MMIO_WRITE_INIT_ABORT_EVENT,
    &_TRACE_TPM_TIS_MMIO_WRITE_LOWERING_IRQ_EVENT,
    &_TRACE_TPM_TIS_MMIO_WRITE_DATA2SEND_EVENT,
    &_TRACE_TPM_TIS_PRE_SAVE_EVENT,
    &_TRACE_TPM_PPI_MEMSET_EVENT,
    &_TRACE_TPM_SPAPR_DO_CRQ_EVENT,
    &_TRACE_TPM_SPAPR_DO_CRQ_CRQ_RESULT_EVENT,
    &_TRACE_TPM_SPAPR_DO_CRQ_CRQ_COMPLETE_RESULT_EVENT,
    &_TRACE_TPM_SPAPR_DO_CRQ_TPM_COMMAND_EVENT,
    &_TRACE_TPM_SPAPR_DO_CRQ_TPM_GET_RTCE_BUFFER_SIZE_EVENT,
    &_TRACE_TPM_SPAPR_DO_CRQ_GET_VERSION_EVENT,
    &_TRACE_TPM_SPAPR_DO_CRQ_PREPARE_TO_SUSPEND_EVENT,
    &_TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_MSG_TYPE_EVENT,
    &_TRACE_TPM_SPAPR_DO_CRQ_UNKNOWN_CRQ_EVENT,
    &_TRACE_TPM_SPAPR_POST_LOAD_EVENT,
    &_TRACE_TPM_SPAPR_CAUGHT_RESPONSE_EVENT,
    &_TRACE_TPM_TIS_I2C_RECV_EVENT,
    &_TRACE_TPM_TIS_I2C_SEND_EVENT,
    &_TRACE_TPM_TIS_I2C_EVENT_EVENT,
    &_TRACE_TPM_TIS_I2C_SEND_REG_EVENT,
  NULL,
};

static void trace_hw_tpm_register_events(void)
{
    trace_event_register_group(hw_tpm_trace_events);
}
trace_init(trace_hw_tpm_register_events)