/* This file is autogenerated by tracetool, do not edit. */

#ifndef TRACE_TARGET_ARM_GENERATED_TRACERS_H
#define TRACE_TARGET_ARM_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_ARM_GT_RECALC_EVENT;
extern TraceEvent _TRACE_ARM_GT_RECALC_DISABLED_EVENT;
extern TraceEvent _TRACE_ARM_GT_CVAL_WRITE_EVENT;
extern TraceEvent _TRACE_ARM_GT_TVAL_WRITE_EVENT;
extern TraceEvent _TRACE_ARM_GT_CTL_WRITE_EVENT;
extern TraceEvent _TRACE_ARM_GT_IMASK_TOGGLE_EVENT;
extern TraceEvent _TRACE_ARM_GT_CNTVOFF_WRITE_EVENT;
extern TraceEvent _TRACE_ARM_GT_CNTPOFF_WRITE_EVENT;
extern TraceEvent _TRACE_ARM_GT_UPDATE_IRQ_EVENT;
extern TraceEvent _TRACE_KVM_ARM_FIXUP_MSI_ROUTE_EVENT;
extern uint16_t _TRACE_ARM_GT_RECALC_DSTATE;
extern uint16_t _TRACE_ARM_GT_RECALC_DISABLED_DSTATE;
extern uint16_t _TRACE_ARM_GT_CVAL_WRITE_DSTATE;
extern uint16_t _TRACE_ARM_GT_TVAL_WRITE_DSTATE;
extern uint16_t _TRACE_ARM_GT_CTL_WRITE_DSTATE;
extern uint16_t _TRACE_ARM_GT_IMASK_TOGGLE_DSTATE;
extern uint16_t _TRACE_ARM_GT_CNTVOFF_WRITE_DSTATE;
extern uint16_t _TRACE_ARM_GT_CNTPOFF_WRITE_DSTATE;
extern uint16_t _TRACE_ARM_GT_UPDATE_IRQ_DSTATE;
extern uint16_t _TRACE_KVM_ARM_FIXUP_MSI_ROUTE_DSTATE;
#define TRACE_ARM_GT_RECALC_ENABLED 1
#define TRACE_ARM_GT_RECALC_DISABLED_ENABLED 1
#define TRACE_ARM_GT_CVAL_WRITE_ENABLED 1
#define TRACE_ARM_GT_TVAL_WRITE_ENABLED 1
#define TRACE_ARM_GT_CTL_WRITE_ENABLED 1
#define TRACE_ARM_GT_IMASK_TOGGLE_ENABLED 1
#define TRACE_ARM_GT_CNTVOFF_WRITE_ENABLED 1
#define TRACE_ARM_GT_CNTPOFF_WRITE_ENABLED 1
#define TRACE_ARM_GT_UPDATE_IRQ_ENABLED 1
#define TRACE_KVM_ARM_FIXUP_MSI_ROUTE_ENABLED 1
#include "qemu/log-for-trace.h"
#include "qemu/error-report.h"


#define TRACE_ARM_GT_RECALC_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARM_GT_RECALC) || \
    false)

static inline void _nocheck__trace_arm_gt_recalc(int timer, uint64_t nexttick)
{
    if (trace_event_get_state(TRACE_ARM_GT_RECALC) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 4 "../target/arm/trace-events"
            qemu_log("%d@%zu.%06zu:arm_gt_recalc " "gt recalc: timer %d next tick 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , timer, nexttick);
#line 58 "trace/trace-target_arm.h"
        } else {
#line 4 "../target/arm/trace-events"
            qemu_log("arm_gt_recalc " "gt recalc: timer %d next tick 0x%" PRIx64 "\n", timer, nexttick);
#line 62 "trace/trace-target_arm.h"
        }
    }
}

static inline void trace_arm_gt_recalc(int timer, uint64_t nexttick)
{
    if (true) {
        _nocheck__trace_arm_gt_recalc(timer, nexttick);
    }
}

#define TRACE_ARM_GT_RECALC_DISABLED_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARM_GT_RECALC_DISABLED) || \
    false)

static inline void _nocheck__trace_arm_gt_recalc_disabled(int timer)
{
    if (trace_event_get_state(TRACE_ARM_GT_RECALC_DISABLED) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 5 "../target/arm/trace-events"
            qemu_log("%d@%zu.%06zu:arm_gt_recalc_disabled " "gt recalc: timer %d timer disabled" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , timer);
#line 89 "trace/trace-target_arm.h"
        } else {
#line 5 "../target/arm/trace-events"
            qemu_log("arm_gt_recalc_disabled " "gt recalc: timer %d timer disabled" "\n", timer);
#line 93 "trace/trace-target_arm.h"
        }
    }
}

static inline void trace_arm_gt_recalc_disabled(int timer)
{
    if (true) {
        _nocheck__trace_arm_gt_recalc_disabled(timer);
    }
}

#define TRACE_ARM_GT_CVAL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARM_GT_CVAL_WRITE) || \
    false)

static inline void _nocheck__trace_arm_gt_cval_write(int timer, uint64_t value)
{
    if (trace_event_get_state(TRACE_ARM_GT_CVAL_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 6 "../target/arm/trace-events"
            qemu_log("%d@%zu.%06zu:arm_gt_cval_write " "gt_cval_write: timer %d value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , timer, value);
#line 120 "trace/trace-target_arm.h"
        } else {
#line 6 "../target/arm/trace-events"
            qemu_log("arm_gt_cval_write " "gt_cval_write: timer %d value 0x%" PRIx64 "\n", timer, value);
#line 124 "trace/trace-target_arm.h"
        }
    }
}

static inline void trace_arm_gt_cval_write(int timer, uint64_t value)
{
    if (true) {
        _nocheck__trace_arm_gt_cval_write(timer, value);
    }
}

#define TRACE_ARM_GT_TVAL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARM_GT_TVAL_WRITE) || \
    false)

static inline void _nocheck__trace_arm_gt_tval_write(int timer, uint64_t value)
{
    if (trace_event_get_state(TRACE_ARM_GT_TVAL_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 7 "../target/arm/trace-events"
            qemu_log("%d@%zu.%06zu:arm_gt_tval_write " "gt_tval_write: timer %d value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , timer, value);
#line 151 "trace/trace-target_arm.h"
        } else {
#line 7 "../target/arm/trace-events"
            qemu_log("arm_gt_tval_write " "gt_tval_write: timer %d value 0x%" PRIx64 "\n", timer, value);
#line 155 "trace/trace-target_arm.h"
        }
    }
}

static inline void trace_arm_gt_tval_write(int timer, uint64_t value)
{
    if (true) {
        _nocheck__trace_arm_gt_tval_write(timer, value);
    }
}

#define TRACE_ARM_GT_CTL_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARM_GT_CTL_WRITE) || \
    false)

static inline void _nocheck__trace_arm_gt_ctl_write(int timer, uint64_t value)
{
    if (trace_event_get_state(TRACE_ARM_GT_CTL_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 8 "../target/arm/trace-events"
            qemu_log("%d@%zu.%06zu:arm_gt_ctl_write " "gt_ctl_write: timer %d value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , timer, value);
#line 182 "trace/trace-target_arm.h"
        } else {
#line 8 "../target/arm/trace-events"
            qemu_log("arm_gt_ctl_write " "gt_ctl_write: timer %d value 0x%" PRIx64 "\n", timer, value);
#line 186 "trace/trace-target_arm.h"
        }
    }
}

static inline void trace_arm_gt_ctl_write(int timer, uint64_t value)
{
    if (true) {
        _nocheck__trace_arm_gt_ctl_write(timer, value);
    }
}

#define TRACE_ARM_GT_IMASK_TOGGLE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARM_GT_IMASK_TOGGLE) || \
    false)

static inline void _nocheck__trace_arm_gt_imask_toggle(int timer)
{
    if (trace_event_get_state(TRACE_ARM_GT_IMASK_TOGGLE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 9 "../target/arm/trace-events"
            qemu_log("%d@%zu.%06zu:arm_gt_imask_toggle " "gt_ctl_write: timer %d IMASK toggle" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , timer);
#line 213 "trace/trace-target_arm.h"
        } else {
#line 9 "../target/arm/trace-events"
            qemu_log("arm_gt_imask_toggle " "gt_ctl_write: timer %d IMASK toggle" "\n", timer);
#line 217 "trace/trace-target_arm.h"
        }
    }
}

static inline void trace_arm_gt_imask_toggle(int timer)
{
    if (true) {
        _nocheck__trace_arm_gt_imask_toggle(timer);
    }
}

#define TRACE_ARM_GT_CNTVOFF_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARM_GT_CNTVOFF_WRITE) || \
    false)

static inline void _nocheck__trace_arm_gt_cntvoff_write(uint64_t value)
{
    if (trace_event_get_state(TRACE_ARM_GT_CNTVOFF_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 10 "../target/arm/trace-events"
            qemu_log("%d@%zu.%06zu:arm_gt_cntvoff_write " "gt_cntvoff_write: value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , value);
#line 244 "trace/trace-target_arm.h"
        } else {
#line 10 "../target/arm/trace-events"
            qemu_log("arm_gt_cntvoff_write " "gt_cntvoff_write: value 0x%" PRIx64 "\n", value);
#line 248 "trace/trace-target_arm.h"
        }
    }
}

static inline void trace_arm_gt_cntvoff_write(uint64_t value)
{
    if (true) {
        _nocheck__trace_arm_gt_cntvoff_write(value);
    }
}

#define TRACE_ARM_GT_CNTPOFF_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARM_GT_CNTPOFF_WRITE) || \
    false)

static inline void _nocheck__trace_arm_gt_cntpoff_write(uint64_t value)
{
    if (trace_event_get_state(TRACE_ARM_GT_CNTPOFF_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 11 "../target/arm/trace-events"
            qemu_log("%d@%zu.%06zu:arm_gt_cntpoff_write " "gt_cntpoff_write: value 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , value);
#line 275 "trace/trace-target_arm.h"
        } else {
#line 11 "../target/arm/trace-events"
            qemu_log("arm_gt_cntpoff_write " "gt_cntpoff_write: value 0x%" PRIx64 "\n", value);
#line 279 "trace/trace-target_arm.h"
        }
    }
}

static inline void trace_arm_gt_cntpoff_write(uint64_t value)
{
    if (true) {
        _nocheck__trace_arm_gt_cntpoff_write(value);
    }
}

#define TRACE_ARM_GT_UPDATE_IRQ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_ARM_GT_UPDATE_IRQ) || \
    false)

static inline void _nocheck__trace_arm_gt_update_irq(int timer, int irqstate)
{
    if (trace_event_get_state(TRACE_ARM_GT_UPDATE_IRQ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 12 "../target/arm/trace-events"
            qemu_log("%d@%zu.%06zu:arm_gt_update_irq " "gt_update_irq: timer %d irqstate %d" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , timer, irqstate);
#line 306 "trace/trace-target_arm.h"
        } else {
#line 12 "../target/arm/trace-events"
            qemu_log("arm_gt_update_irq " "gt_update_irq: timer %d irqstate %d" "\n", timer, irqstate);
#line 310 "trace/trace-target_arm.h"
        }
    }
}

static inline void trace_arm_gt_update_irq(int timer, int irqstate)
{
    if (true) {
        _nocheck__trace_arm_gt_update_irq(timer, irqstate);
    }
}

#define TRACE_KVM_ARM_FIXUP_MSI_ROUTE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_KVM_ARM_FIXUP_MSI_ROUTE) || \
    false)

static inline void _nocheck__trace_kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa)
{
    if (trace_event_get_state(TRACE_KVM_ARM_FIXUP_MSI_ROUTE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 15 "../target/arm/trace-events"
            qemu_log("%d@%zu.%06zu:kvm_arm_fixup_msi_route " "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , iova, gpa);
#line 337 "trace/trace-target_arm.h"
        } else {
#line 15 "../target/arm/trace-events"
            qemu_log("kvm_arm_fixup_msi_route " "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64 "\n", iova, gpa);
#line 341 "trace/trace-target_arm.h"
        }
    }
}

static inline void trace_kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa)
{
    if (true) {
        _nocheck__trace_kvm_arm_fixup_msi_route(iova, gpa);
    }
}
#endif /* TRACE_TARGET_ARM_GENERATED_TRACERS_H */