/* This file is autogenerated by tracetool, do not edit. */

#ifndef TRACE_TARGET_RISCV_GENERATED_TRACERS_H
#define TRACE_TARGET_RISCV_GENERATED_TRACERS_H

#include "trace/control.h"

extern TraceEvent _TRACE_RISCV_TRAP_EVENT;
extern TraceEvent _TRACE_PMPCFG_CSR_READ_EVENT;
extern TraceEvent _TRACE_PMPCFG_CSR_WRITE_EVENT;
extern TraceEvent _TRACE_PMPADDR_CSR_READ_EVENT;
extern TraceEvent _TRACE_PMPADDR_CSR_WRITE_EVENT;
extern TraceEvent _TRACE_MSECCFG_CSR_READ_EVENT;
extern TraceEvent _TRACE_MSECCFG_CSR_WRITE_EVENT;
extern uint16_t _TRACE_RISCV_TRAP_DSTATE;
extern uint16_t _TRACE_PMPCFG_CSR_READ_DSTATE;
extern uint16_t _TRACE_PMPCFG_CSR_WRITE_DSTATE;
extern uint16_t _TRACE_PMPADDR_CSR_READ_DSTATE;
extern uint16_t _TRACE_PMPADDR_CSR_WRITE_DSTATE;
extern uint16_t _TRACE_MSECCFG_CSR_READ_DSTATE;
extern uint16_t _TRACE_MSECCFG_CSR_WRITE_DSTATE;
#define TRACE_RISCV_TRAP_ENABLED 1
#define TRACE_PMPCFG_CSR_READ_ENABLED 1
#define TRACE_PMPCFG_CSR_WRITE_ENABLED 1
#define TRACE_PMPADDR_CSR_READ_ENABLED 1
#define TRACE_PMPADDR_CSR_WRITE_ENABLED 1
#define TRACE_MSECCFG_CSR_READ_ENABLED 1
#define TRACE_MSECCFG_CSR_WRITE_ENABLED 1
#include "qemu/log-for-trace.h"
#include "qemu/error-report.h"


#define TRACE_RISCV_TRAP_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_RISCV_TRAP) || \
    false)

static inline void _nocheck__trace_riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char * desc)
{
    if (trace_event_get_state(TRACE_RISCV_TRAP) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 2 "../target/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:riscv_trap " "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s" "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , hartid, async, cause, epc, tval, desc);
#line 49 "trace/trace-target_riscv.h"
        } else {
#line 2 "../target/riscv/trace-events"
            qemu_log("riscv_trap " "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s" "\n", hartid, async, cause, epc, tval, desc);
#line 53 "trace/trace-target_riscv.h"
        }
    }
}

static inline void trace_riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char * desc)
{
    if (true) {
        _nocheck__trace_riscv_trap(hartid, async, cause, epc, tval, desc);
    }
}

#define TRACE_PMPCFG_CSR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PMPCFG_CSR_READ) || \
    false)

static inline void _nocheck__trace_pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val)
{
    if (trace_event_get_state(TRACE_PMPCFG_CSR_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 5 "../target/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:pmpcfg_csr_read " "hart %" PRIu64 ": read reg%" PRIu32", val: 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , mhartid, reg_index, val);
#line 80 "trace/trace-target_riscv.h"
        } else {
#line 5 "../target/riscv/trace-events"
            qemu_log("pmpcfg_csr_read " "hart %" PRIu64 ": read reg%" PRIu32", val: 0x%" PRIx64 "\n", mhartid, reg_index, val);
#line 84 "trace/trace-target_riscv.h"
        }
    }
}

static inline void trace_pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val)
{
    if (true) {
        _nocheck__trace_pmpcfg_csr_read(mhartid, reg_index, val);
    }
}

#define TRACE_PMPCFG_CSR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PMPCFG_CSR_WRITE) || \
    false)

static inline void _nocheck__trace_pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val)
{
    if (trace_event_get_state(TRACE_PMPCFG_CSR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 6 "../target/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:pmpcfg_csr_write " "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , mhartid, reg_index, val);
#line 111 "trace/trace-target_riscv.h"
        } else {
#line 6 "../target/riscv/trace-events"
            qemu_log("pmpcfg_csr_write " "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64 "\n", mhartid, reg_index, val);
#line 115 "trace/trace-target_riscv.h"
        }
    }
}

static inline void trace_pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val)
{
    if (true) {
        _nocheck__trace_pmpcfg_csr_write(mhartid, reg_index, val);
    }
}

#define TRACE_PMPADDR_CSR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PMPADDR_CSR_READ) || \
    false)

static inline void _nocheck__trace_pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val)
{
    if (trace_event_get_state(TRACE_PMPADDR_CSR_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 7 "../target/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:pmpaddr_csr_read " "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , mhartid, addr_index, val);
#line 142 "trace/trace-target_riscv.h"
        } else {
#line 7 "../target/riscv/trace-events"
            qemu_log("pmpaddr_csr_read " "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64 "\n", mhartid, addr_index, val);
#line 146 "trace/trace-target_riscv.h"
        }
    }
}

static inline void trace_pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val)
{
    if (true) {
        _nocheck__trace_pmpaddr_csr_read(mhartid, addr_index, val);
    }
}

#define TRACE_PMPADDR_CSR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_PMPADDR_CSR_WRITE) || \
    false)

static inline void _nocheck__trace_pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val)
{
    if (trace_event_get_state(TRACE_PMPADDR_CSR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 8 "../target/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:pmpaddr_csr_write " "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , mhartid, addr_index, val);
#line 173 "trace/trace-target_riscv.h"
        } else {
#line 8 "../target/riscv/trace-events"
            qemu_log("pmpaddr_csr_write " "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64 "\n", mhartid, addr_index, val);
#line 177 "trace/trace-target_riscv.h"
        }
    }
}

static inline void trace_pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val)
{
    if (true) {
        _nocheck__trace_pmpaddr_csr_write(mhartid, addr_index, val);
    }
}

#define TRACE_MSECCFG_CSR_READ_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSECCFG_CSR_READ) || \
    false)

static inline void _nocheck__trace_mseccfg_csr_read(uint64_t mhartid, uint64_t val)
{
    if (trace_event_get_state(TRACE_MSECCFG_CSR_READ) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 10 "../target/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:mseccfg_csr_read " "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , mhartid, val);
#line 204 "trace/trace-target_riscv.h"
        } else {
#line 10 "../target/riscv/trace-events"
            qemu_log("mseccfg_csr_read " "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64 "\n", mhartid, val);
#line 208 "trace/trace-target_riscv.h"
        }
    }
}

static inline void trace_mseccfg_csr_read(uint64_t mhartid, uint64_t val)
{
    if (true) {
        _nocheck__trace_mseccfg_csr_read(mhartid, val);
    }
}

#define TRACE_MSECCFG_CSR_WRITE_BACKEND_DSTATE() ( \
    trace_event_get_state_dynamic_by_id(TRACE_MSECCFG_CSR_WRITE) || \
    false)

static inline void _nocheck__trace_mseccfg_csr_write(uint64_t mhartid, uint64_t val)
{
    if (trace_event_get_state(TRACE_MSECCFG_CSR_WRITE) && qemu_loglevel_mask(LOG_TRACE)) {
        if (message_with_timestamp) {
            struct timeval _now;
            gettimeofday(&_now, NULL);
#line 11 "../target/riscv/trace-events"
            qemu_log("%d@%zu.%06zu:mseccfg_csr_write " "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64 "\n",
                     qemu_get_thread_id(),
                     (size_t)_now.tv_sec, (size_t)_now.tv_usec
                     , mhartid, val);
#line 235 "trace/trace-target_riscv.h"
        } else {
#line 11 "../target/riscv/trace-events"
            qemu_log("mseccfg_csr_write " "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64 "\n", mhartid, val);
#line 239 "trace/trace-target_riscv.h"
        }
    }
}

static inline void trace_mseccfg_csr_write(uint64_t mhartid, uint64_t val)
{
    if (true) {
        _nocheck__trace_mseccfg_csr_write(mhartid, val);
    }
}
#endif /* TRACE_TARGET_RISCV_GENERATED_TRACERS_H */