Index of /~puru//courses/resources/old-virtio/qemu/subprojects/berkeley-softfloat-3/source

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[TXT]ui64_to_f128M.c2025-03-16 16:46 2.9K 
[TXT]ui64_to_f128.c2025-03-16 16:46 2.5K 
[TXT]ui64_to_f64.c2025-03-16 16:46 2.2K 
[TXT]ui64_to_f32.c2025-03-16 16:46 2.5K 
[TXT]ui64_to_f16.c2025-03-16 16:46 2.5K 
[TXT]ui64_to_extF80M.c2025-03-16 16:46 2.4K 
[TXT]ui64_to_extF80.c2025-03-16 16:46 2.2K 
[TXT]ui32_to_f128M.c2025-03-16 16:46 2.5K 
[TXT]ui32_to_f128.c2025-03-16 16:46 2.3K 
[TXT]ui32_to_f64.c2025-03-16 16:46 2.2K 
[TXT]ui32_to_f32.c2025-03-16 16:46 2.2K 
[TXT]ui32_to_f16.c2025-03-16 16:46 2.5K 
[TXT]ui32_to_extF80M.c2025-03-16 16:46 2.5K 
[TXT]ui32_to_extF80.c2025-03-16 16:46 2.3K 
[TXT]softfloat_state.c2025-03-16 16:46 2.2K 
[TXT]s_tryPropagateNaNF128M.c2025-03-16 16:46 2.2K 
[TXT]s_tryPropagateNaNExtF80M.c2025-03-16 16:46 2.4K 
[TXT]s_subMagsF128.c2025-03-16 16:46 4.6K 
[TXT]s_subMagsF64.c2025-03-16 16:46 5.4K 
[TXT]s_subMagsF32.c2025-03-16 16:46 5.4K 
[TXT]s_subMagsF16.c2025-03-16 16:46 6.9K 
[TXT]s_subMagsExtF80.c2025-03-16 16:46 5.6K 
[TXT]s_subM.c2025-03-16 16:46 2.4K 
[TXT]s_sub256M.c2025-03-16 16:46 2.3K 
[TXT]s_sub128.c2025-03-16 16:46 2.1K 
[TXT]s_sub1XM.c2025-03-16 16:46 2.2K 
[TXT]s_shortShiftRightM.c2025-03-16 16:46 2.5K 
[TXT]s_shortShiftRightJamM.c2025-03-16 16:46 2.6K 
[TXT]s_shortShiftRightJam128Extra.c2025-03-16 16:46 2.2K 
[TXT]s_shortShiftRightJam128.c2025-03-16 16:46 2.2K 
[TXT]s_shortShiftRightJam64Extra.c2025-03-16 16:46 2.1K 
[TXT]s_shortShiftRightJam64.c2025-03-16 16:46 2.0K 
[TXT]s_shortShiftRightExtendM.c2025-03-16 16:46 2.6K 
[TXT]s_shortShiftRight128.c2025-03-16 16:46 2.1K 
[TXT]s_shortShiftLeftM.c2025-03-16 16:46 2.5K 
[TXT]s_shortShiftLeft128.c2025-03-16 16:46 2.1K 
[TXT]s_shortShiftLeft64To96M.c2025-03-16 16:46 2.1K 
[TXT]s_shiftRightM.c2025-03-16 16:46 3.1K 
[TXT]s_shiftRightJamM.c2025-03-16 16:46 3.4K 
[TXT]s_shiftRightJam256M.c2025-03-16 16:46 3.9K 
[TXT]s_shiftRightJam128Extra.c2025-03-16 16:46 2.7K 
[TXT]s_shiftRightJam128.c2025-03-16 16:46 2.5K 
[TXT]s_shiftRightJam64Extra.c2025-03-16 16:46 2.2K 
[TXT]s_shiftRightJam64.c2025-03-16 16:46 2.0K 
[TXT]s_shiftRightJam32.c2025-03-16 16:46 2.0K 
[TXT]s_shiftNormSigF128M.c2025-03-16 16:46 2.9K 
[TXT]s_shiftLeftM.c2025-03-16 16:46 3.1K 
[TXT]s_roundToUI64.c2025-03-16 16:46 3.6K 
[TXT]s_roundToUI32.c2025-03-16 16:46 3.5K 
[TXT]s_roundToI64.c2025-03-16 16:46 3.7K 
[TXT]s_roundToI32.c2025-03-16 16:46 3.6K 
[TXT]s_roundPackToF128.c2025-03-16 16:46 6.6K 
[TXT]s_roundPackToF64.c2025-03-16 16:46 4.8K 
[TXT]s_roundPackToF32.c2025-03-16 16:46 4.7K 
[TXT]s_roundPackToF16.c2025-03-16 16:46 4.7K 
[TXT]s_roundPackToExtF80.c2025-03-16 16:46 9.8K 
[TXT]s_roundPackMToF128M.c2025-03-16 16:46 7.0K 
[TXT]s_roundPackMToExtF80M.c2025-03-16 16:46 9.9K 
[TXT]s_roundMToUI64.c2025-03-16 16:46 3.7K 
[TXT]s_roundMToI64.c2025-03-16 16:46 3.8K 
[TXT]s_remStepMBy32.c2025-03-16 16:46 3.1K 
[TXT]s_normSubnormalF128SigM.c2025-03-16 16:46 2.4K 
[TXT]s_normSubnormalF128Sig.c2025-03-16 16:46 2.5K 
[TXT]s_normSubnormalF64Sig.c2025-03-16 16:46 2.1K 
[TXT]s_normSubnormalF32Sig.c2025-03-16 16:46 2.1K 
[TXT]s_normSubnormalF16Sig.c2025-03-16 16:46 2.1K 
[TXT]s_normSubnormalExtF80Sig.c2025-03-16 16:46 2.1K 
[TXT]s_normRoundPackToF128.c2025-03-16 16:46 3.0K 
[TXT]s_normRoundPackToF64.c2025-03-16 16:46 2.3K 
[TXT]s_normRoundPackToF32.c2025-03-16 16:46 2.3K 
[TXT]s_normRoundPackToF16.c2025-03-16 16:46 2.3K 
[TXT]s_normRoundPackToExtF80.c2025-03-16 16:46 2.5K 
[TXT]s_normRoundPackMToF128M.c2025-03-16 16:46 2.7K 
[TXT]s_normRoundPackMToExtF80M.c2025-03-16 16:46 2.8K 
[TXT]s_normExtF80SigM.c2025-03-16 16:46 2.1K 
[TXT]s_negXM.c2025-03-16 16:46 2.3K 
[TXT]s_mulAddF128M.c2025-03-16 16:46 15K 
[TXT]s_mulAddF128.c2025-03-16 16:46 13K 
[TXT]s_mulAddF64.c2025-03-16 16:46 18K 
[TXT]s_mulAddF32.c2025-03-16 16:46 8.1K 
[TXT]s_mulAddF16.c2025-03-16 16:46 8.1K 
[TXT]s_mul128To256M.c2025-03-16 16:46 2.6K 
[TXT]s_mul128MTo256M.c2025-03-16 16:46 4.0K 
[TXT]s_mul128By32.c2025-03-16 16:46 2.2K 
[TXT]s_mul64To128M.c2025-03-16 16:46 2.4K 
[TXT]s_mul64To128.c2025-03-16 16:46 2.4K 
[TXT]s_mul64ByShifted32To128.c2025-03-16 16:46 2.2K 
[TXT]s_lt128.c2025-03-16 16:46 2.0K 
[TXT]s_le128.c2025-03-16 16:46 2.0K 
[TXT]s_isNaNF128M.c2025-03-16 16:46 2.4K 
[TXT]s_invalidF128M.c2025-03-16 16:46 2.2K 
[TXT]s_invalidExtF80M.c2025-03-16 16:46 2.0K 
[TXT]s_eq128.c2025-03-16 16:46 2.0K 
[TXT]s_countLeadingZeros64.c2025-03-16 16:46 2.6K 
[TXT]s_countLeadingZeros32.c2025-03-16 16:46 2.3K 
[TXT]s_countLeadingZeros16.c2025-03-16 16:46 2.2K 
[TXT]s_countLeadingZeros8.c2025-03-16 16:46 2.7K 
[TXT]s_compareNonnormExtF80M.c2025-03-16 16:46 4.2K 
[TXT]s_compare128M.c2025-03-16 16:46 2.3K 
[TXT]s_compare96M.c2025-03-16 16:46 2.3K 
[TXT]s_approxRecip_1Ks.c2025-03-16 16:46 2.2K 
[TXT]s_approxRecipSqrt_1Ks.c2025-03-16 16:46 2.2K 
[TXT]s_approxRecipSqrt32_1.c2025-03-16 16:46 2.9K 
[TXT]s_approxRecip32_1.c2025-03-16 16:46 2.6K 
[TXT]s_addMagsF128.c2025-03-16 16:46 4.9K 
[TXT]s_addMagsF64.c2025-03-16 16:46 4.7K 
[TXT]s_addMagsF32.c2025-03-16 16:46 4.6K 
[TXT]s_addMagsF16.c2025-03-16 16:46 6.6K 
[TXT]s_addMagsExtF80.c2025-03-16 16:46 5.5K 
[TXT]s_addM.c2025-03-16 16:46 2.4K 
[TXT]s_addF128M.c2025-03-16 16:46 7.9K 
[TXT]s_addExtF80M.c2025-03-16 16:46 7.0K 
[TXT]s_addComplCarryM.c2025-03-16 16:46 2.5K 
[TXT]s_addCarryM.c2025-03-16 16:46 2.5K 
[TXT]s_add256M.c2025-03-16 16:46 2.3K 
[TXT]s_add128.c2025-03-16 16:46 2.1K 
[DIR]include/2025-03-16 16:46 -  
[TXT]i64_to_f128M.c2025-03-16 16:46 3.1K 
[TXT]i64_to_f128.c2025-03-16 16:46 2.6K 
[TXT]i64_to_f64.c2025-03-16 16:46 2.2K 
[TXT]i64_to_f32.c2025-03-16 16:46 2.6K 
[TXT]i64_to_f16.c2025-03-16 16:46 2.6K 
[TXT]i64_to_extF80M.c2025-03-16 16:46 2.6K 
[TXT]i64_to_extF80.c2025-03-16 16:46 2.4K 
[TXT]i32_to_f128M.c2025-03-16 16:46 2.7K 
[TXT]i32_to_f128.c2025-03-16 16:46 2.4K 
[TXT]i32_to_f64.c2025-03-16 16:46 2.4K 
[TXT]i32_to_f32.c2025-03-16 16:46 2.2K 
[TXT]i32_to_f16.c2025-03-16 16:46 2.7K 
[TXT]i32_to_extF80M.c2025-03-16 16:46 2.6K 
[TXT]i32_to_extF80.c2025-03-16 16:46 2.4K 
[TXT]f128_to_ui64_r_minMag.c2025-03-16 16:46 4.3K 
[TXT]f128_to_ui64.c2025-03-16 16:46 4.0K 
[TXT]f128_to_ui32_r_minMag.c2025-03-16 16:46 3.6K 
[TXT]f128_to_ui32.c2025-03-16 16:46 3.4K 
[TXT]f128_to_i64_r_minMag.c2025-03-16 16:46 4.7K 
[TXT]f128_to_i64.c2025-03-16 16:46 4.0K 
[TXT]f128_to_i32_r_minMag.c2025-03-16 16:46 3.9K 
[TXT]f128_to_i32.c2025-03-16 16:46 3.4K 
[TXT]f128_to_f64.c2025-03-16 16:46 3.9K 
[TXT]f128_to_f32.c2025-03-16 16:46 3.8K 
[TXT]f128_to_f16.c2025-03-16 16:46 3.7K 
[TXT]f128_to_extF80.c2025-03-16 16:46 4.2K 
[TXT]f128_sub.c2025-03-16 16:46 2.8K 
[TXT]f128_sqrt.c2025-03-16 16:46 8.4K 
[TXT]f128_roundToInt.c2025-03-16 16:46 6.8K 
[TXT]f128_rem.c2025-03-16 16:46 7.3K 
[TXT]f128_mulAdd.c2025-03-16 16:46 2.3K 
[TXT]f128_mul.c2025-03-16 16:46 6.0K 
[TXT]f128_lt_quiet.c2025-03-16 16:46 2.9K 
[TXT]f128_lt.c2025-03-16 16:46 2.7K 
[TXT]f128_le_quiet.c2025-03-16 16:46 2.9K 
[TXT]f128_le.c2025-03-16 16:46 2.7K 
[TXT]f128_isSignalingNaN.c2025-03-16 16:46 2.0K 
[TXT]f128_eq_signaling.c2025-03-16 16:46 2.5K 
[TXT]f128_eq.c2025-03-16 16:46 2.6K 
[TXT]f128_div.c2025-03-16 16:46 7.6K 
[TXT]f128_add.c2025-03-16 16:46 2.8K 
[TXT]f128M_to_ui64_r_minMag.c2025-03-16 16:46 4.2K 
[TXT]f128M_to_ui64.c2025-03-16 16:46 3.8K 
[TXT]f128M_to_ui32_r_minMag.c2025-03-16 16:46 3.8K 
[TXT]f128M_to_ui32.c2025-03-16 16:46 3.7K 
[TXT]f128M_to_i64_r_minMag.c2025-03-16 16:46 4.5K 
[TXT]f128M_to_i64.c2025-03-16 16:46 3.8K 
[TXT]f128M_to_i32_r_minMag.c2025-03-16 16:46 4.0K 
[TXT]f128M_to_i32.c2025-03-16 16:46 3.6K 
[TXT]f128M_to_f64.c2025-03-16 16:46 4.1K 
[TXT]f128M_to_f32.c2025-03-16 16:46 4.0K 
[TXT]f128M_to_f16.c2025-03-16 16:46 4.1K 
[TXT]f128M_to_extF80M.c2025-03-16 16:46 3.8K 
[TXT]f128M_sub.c2025-03-16 16:46 3.2K 
[TXT]f128M_sqrt.c2025-03-16 16:46 8.8K 
[TXT]f128M_roundToInt.c2025-03-16 16:46 7.3K 
[TXT]f128M_rem.c2025-03-16 16:46 7.1K 
[TXT]f128M_mulAdd.c2025-03-16 16:46 2.9K 
[TXT]f128M_mul.c2025-03-16 16:46 5.8K 
[TXT]f128M_lt_quiet.c2025-03-16 16:46 3.3K 
[TXT]f128M_lt.c2025-03-16 16:46 3.2K 
[TXT]f128M_le_quiet.c2025-03-16 16:46 3.4K 
[TXT]f128M_le.c2025-03-16 16:46 3.2K 
[TXT]f128M_eq_signaling.c2025-03-16 16:46 3.2K 
[TXT]f128M_eq.c2025-03-16 16:46 3.5K 
[TXT]f128M_div.c2025-03-16 16:46 6.6K 
[TXT]f128M_add.c2025-03-16 16:46 3.2K 
[TXT]f64_to_ui64_r_minMag.c2025-03-16 16:46 3.6K 
[TXT]f64_to_ui64.c2025-03-16 16:46 3.9K 
[TXT]f64_to_ui32_r_minMag.c2025-03-16 16:46 3.5K 
[TXT]f64_to_ui32.c2025-03-16 16:46 3.3K 
[TXT]f64_to_i64_r_minMag.c2025-03-16 16:46 4.1K 
[TXT]f64_to_i64.c2025-03-16 16:46 3.9K 
[TXT]f64_to_i32_r_minMag.c2025-03-16 16:46 3.8K 
[TXT]f64_to_i32.c2025-03-16 16:46 3.3K 
[TXT]f64_to_f128M.c2025-03-16 16:46 4.2K 
[TXT]f64_to_f128.c2025-03-16 16:46 3.7K 
[TXT]f64_to_f32.c2025-03-16 16:46 3.4K 
[TXT]f64_to_f16.c2025-03-16 16:46 3.4K 
[TXT]f64_to_extF80M.c2025-03-16 16:46 3.9K 
[TXT]f64_to_extF80.c2025-03-16 16:46 3.8K 
[TXT]f64_sub.c2025-03-16 16:46 2.6K 
[TXT]f64_sqrt.c2025-03-16 16:46 5.1K 
[TXT]f64_roundToInt.c2025-03-16 16:46 4.6K 
[TXT]f64_rem.c2025-03-16 16:46 6.9K 
[TXT]f64_mulAdd.c2025-03-16 16:46 2.2K 
[TXT]f64_mul.c2025-03-16 16:46 5.4K 
[TXT]f64_lt_quiet.c2025-03-16 16:46 2.6K 
[TXT]f64_lt.c2025-03-16 16:46 2.4K 
[TXT]f64_le_quiet.c2025-03-16 16:46 2.6K 
[TXT]f64_le.c2025-03-16 16:46 2.4K 
[TXT]f64_isSignalingNaN.c2025-03-16 16:46 2.0K 
[TXT]f64_eq_signaling.c2025-03-16 16:46 2.3K 
[TXT]f64_eq.c2025-03-16 16:46 2.4K 
[TXT]f64_div.c2025-03-16 16:46 6.3K 
[TXT]f64_add.c2025-03-16 16:46 2.6K 
[TXT]f32_to_ui64_r_minMag.c2025-03-16 16:46 3.6K 
[TXT]f32_to_ui64.c2025-03-16 16:46 3.7K 
[TXT]f32_to_ui32_r_minMag.c2025-03-16 16:46 3.5K 
[TXT]f32_to_ui32.c2025-03-16 16:46 3.3K 
[TXT]f32_to_i64_r_minMag.c2025-03-16 16:46 3.7K 
[TXT]f32_to_i64.c2025-03-16 16:46 3.7K 
[TXT]f32_to_i32_r_minMag.c2025-03-16 16:46 3.6K 
[TXT]f32_to_i32.c2025-03-16 16:46 3.3K 
[TXT]f32_to_f128M.c2025-03-16 16:46 4.0K 
[TXT]f32_to_f128.c2025-03-16 16:46 3.6K 
[TXT]f32_to_f64.c2025-03-16 16:46 3.5K 
[TXT]f32_to_f16.c2025-03-16 16:46 3.4K 
[TXT]f32_to_extF80M.c2025-03-16 16:46 3.8K 
[TXT]f32_to_extF80.c2025-03-16 16:46 3.8K 
[TXT]f32_sub.c2025-03-16 16:46 2.5K 
[TXT]f32_sqrt.c2025-03-16 16:46 4.5K 
[TXT]f32_roundToInt.c2025-03-16 16:46 4.6K 
[TXT]f32_rem.c2025-03-16 16:46 6.2K 
[TXT]f32_mulAdd.c2025-03-16 16:46 2.2K 
[TXT]f32_mul.c2025-03-16 16:46 4.9K 
[TXT]f32_lt_quiet.c2025-03-16 16:46 2.6K 
[TXT]f32_lt.c2025-03-16 16:46 2.4K 
[TXT]f32_le_quiet.c2025-03-16 16:46 2.6K 
[TXT]f32_le.c2025-03-16 16:46 2.4K 
[TXT]f32_isSignalingNaN.c2025-03-16 16:46 2.0K 
[TXT]f32_eq_signaling.c2025-03-16 16:46 2.3K 
[TXT]f32_eq.c2025-03-16 16:46 2.4K 
[TXT]f32_div.c2025-03-16 16:46 6.2K 
[TXT]f32_add.c2025-03-16 16:46 2.5K 
[TXT]f16_to_ui64_r_minMag.c2025-03-16 16:46 3.5K 
[TXT]f16_to_ui64.c2025-03-16 16:46 3.6K 
[TXT]f16_to_ui32_r_minMag.c2025-03-16 16:46 3.5K 
[TXT]f16_to_ui32.c2025-03-16 16:46 3.3K 
[TXT]f16_to_i64_r_minMag.c2025-03-16 16:46 3.5K 
[TXT]f16_to_i64.c2025-03-16 16:46 3.3K 
[TXT]f16_to_i32_r_minMag.c2025-03-16 16:46 3.5K 
[TXT]f16_to_i32.c2025-03-16 16:46 3.3K 
[TXT]f16_to_f128M.c2025-03-16 16:46 3.9K 
[TXT]f16_to_f128.c2025-03-16 16:46 3.6K 
[TXT]f16_to_f64.c2025-03-16 16:46 3.5K 
[TXT]f16_to_f32.c2025-03-16 16:46 3.5K 
[TXT]f16_to_extF80M.c2025-03-16 16:46 3.8K 
[TXT]f16_to_extF80.c2025-03-16 16:46 3.8K 
[TXT]f16_sub.c2025-03-16 16:46 2.5K 
[TXT]f16_sqrt.c2025-03-16 16:46 5.1K 
[TXT]f16_roundToInt.c2025-03-16 16:46 4.6K 
[TXT]f16_rem.c2025-03-16 16:46 6.2K 
[TXT]f16_mulAdd.c2025-03-16 16:46 2.2K 
[TXT]f16_mul.c2025-03-16 16:46 5.0K 
[TXT]f16_lt_quiet.c2025-03-16 16:46 2.6K 
[TXT]f16_lt.c2025-03-16 16:46 2.4K 
[TXT]f16_le_quiet.c2025-03-16 16:46 2.6K 
[TXT]f16_le.c2025-03-16 16:46 2.4K 
[TXT]f16_isSignalingNaN.c2025-03-16 16:46 2.0K 
[TXT]f16_eq_signaling.c2025-03-16 16:46 2.3K 
[TXT]f16_eq.c2025-03-16 16:46 2.4K 
[TXT]f16_div.c2025-03-16 16:46 6.3K 
[TXT]f16_add.c2025-03-16 16:46 2.5K 
[TXT]extF80_to_ui64_r_minMag.c2025-03-16 16:46 3.5K 
[TXT]extF80_to_ui64.c2025-03-16 16:46 3.4K 
[TXT]extF80_to_ui32_r_minMag.c2025-03-16 16:46 3.6K 
[TXT]extF80_to_ui32.c2025-03-16 16:46 3.3K 
[TXT]extF80_to_i64_r_minMag.c2025-03-16 16:46 3.8K 
[TXT]extF80_to_i64.c2025-03-16 16:46 3.7K 
[TXT]extF80_to_i32_r_minMag.c2025-03-16 16:46 3.9K 
[TXT]extF80_to_i32.c2025-03-16 16:46 3.3K 
[TXT]extF80_to_f128.c2025-03-16 16:46 2.8K 
[TXT]extF80_to_f64.c2025-03-16 16:46 3.8K 
[TXT]extF80_to_f32.c2025-03-16 16:46 3.8K 
[TXT]extF80_to_f16.c2025-03-16 16:46 3.8K 
[TXT]extF80_sub.c2025-03-16 16:46 3.0K 
[TXT]extF80_sqrt.c2025-03-16 16:46 7.2K 
[TXT]extF80_roundToInt.c2025-03-16 16:46 5.5K 
[TXT]extF80_rem.c2025-03-16 16:46 8.6K 
[TXT]extF80_mul.c2025-03-16 16:46 5.8K 
[TXT]extF80_lt_quiet.c2025-03-16 16:46 2.9K 
[TXT]extF80_lt.c2025-03-16 16:46 2.8K 
[TXT]extF80_le_quiet.c2025-03-16 16:46 2.9K 
[TXT]extF80_le.c2025-03-16 16:46 2.8K 
[TXT]extF80_isSignalingNaN.c2025-03-16 16:46 2.1K 
[TXT]extF80_eq_signaling.c2025-03-16 16:46 2.5K 
[TXT]extF80_eq.c2025-03-16 16:46 2.7K 
[TXT]extF80_div.c2025-03-16 16:46 7.7K 
[TXT]extF80_add.c2025-03-16 16:46 3.0K 
[TXT]extF80M_to_ui64_r_minMag.c2025-03-16 16:46 4.0K 
[TXT]extF80M_to_ui64.c2025-03-16 16:46 3.6K 
[TXT]extF80M_to_ui32_r_minMag.c2025-03-16 16:46 4.1K 
[TXT]extF80M_to_ui32.c2025-03-16 16:46 3.6K 
[TXT]extF80M_to_i64_r_minMag.c2025-03-16 16:46 4.1K 
[TXT]extF80M_to_i64.c2025-03-16 16:46 3.6K 
[TXT]extF80M_to_i32_r_minMag.c2025-03-16 16:46 4.3K 
[TXT]extF80M_to_i32.c2025-03-16 16:46 3.6K 
[TXT]extF80M_to_f128M.c2025-03-16 16:46 4.6K 
[TXT]extF80M_to_f64.c2025-03-16 16:46 4.1K 
[TXT]extF80M_to_f32.c2025-03-16 16:46 4.2K 
[TXT]extF80M_to_f16.c2025-03-16 16:46 4.2K 
[TXT]extF80M_sub.c2025-03-16 16:46 3.3K 
[TXT]extF80M_sqrt.c2025-03-16 16:46 7.2K 
[TXT]extF80M_roundToInt.c2025-03-16 16:46 5.9K 
[TXT]extF80M_rem.c2025-03-16 16:46 7.6K 
[TXT]extF80M_mul.c2025-03-16 16:46 5.1K 
[TXT]extF80M_lt_quiet.c2025-03-16 16:46 4.3K 
[TXT]extF80M_lt.c2025-03-16 16:46 4.1K 
[TXT]extF80M_le_quiet.c2025-03-16 16:46 4.3K 
[TXT]extF80M_le.c2025-03-16 16:46 4.1K 
[TXT]extF80M_eq_signaling.c2025-03-16 16:46 3.5K 
[TXT]extF80M_eq.c2025-03-16 16:46 3.6K 
[TXT]extF80M_div.c2025-03-16 16:46 7.0K 
[TXT]extF80M_add.c2025-03-16 16:46 3.3K 
[DIR]RISCV/2025-03-16 16:46 -  
[DIR]ARM-VFPv2/2025-03-16 16:46 -  
[DIR]ARM-VFPv2-defaultNaN/2025-03-16 16:46 -  
[DIR]8086/2025-03-16 16:46 -  
[DIR]8086-SSE/2025-03-16 16:46 -  

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