Publications

I have around 30 Papers published in National and International Journals. The earlier ones are listed below:
  1. K.T.Oommen Tharakan, A.N.Chandorkar, S.S.S.P.Rao, K.Chandra Sekaran, "A GUI based software tool development for VLSI test pattern generation using Genetic Algorithms", International Journal on Software Practice and Experience". (to Appear).


  2. K.T.Oommen Tharakan, A.N.Chandorkar, S.S.S.P.Rao, K.Chandra Sekaran, "A novel approach for VLSI test pattern generation using Genetic Algorithms", IEEE Transactions on Evolutionary Computing" (Communicated).


  3. K.T.Oommen Tharakan, A.N.Chandorkar, S.S.S.P.Rao, K.Chandra Sekaran, "Development of a Parallel Genetic Algorithm for ATPG on a cluster of workstations", Journal of CSI. (to appear).


  4. K.T.Oommen Tharakan, A.N.Chandorkar, S.S.S.P.Rao, K.Chandra Sekaran, "A Hybrid Parallel Genetic Algorithm for VLSI test pattern generation", International Journal of Computational Engineering Science (UK) (Communicated).


  5. Oommen Tharakan, A.N.Chandorkar, S.S.S.P.Rao,and K.Chandrasekharan, Development of an abstract model for a non-volatile static random access memory, Defence Science Journal published by DESIDOC, Volume 54, April 2004, pp.183-188.


  6. Oommen Tharakan, S.S.S.P.Rao, A method of Generation of High Power Test Vector Set of Combinational VLSI Circuits, Special Issue of Defence Science Journal published by DESIDOC, Vol.52, No.4, October 2002, pp.351-356.


  7. Namit Kumar, Usha Priyadharshini, Milind Sohoni, S.S.S.P.Rao, A Reordering Algorithm for Data Compression for FPGA Configurations, IETE Technical Review, Vol.18, No.5 issue, Sept.-Oct.2001, pp-375-380. Also published in IETE Journal of Education, Vol.43., No.2,April-June 2002,pp.65-70.


  8. Usha Priyadarshini, S.S.S.P.Rao, Tomorrow's Personal Computing Devices, accepted for publication in CSI Journal of Computer Science and Informatics, Vol.31,No.1,March 2001, pp.8-12. .


  9. Ameet Kumar Jain, S.S.S.P.Rao, Reconfigurable Computing: An Innovative Approach to System Design, CSI Journal of Computer Science and Informatics, Vol.30, No.3, Sept.2000, pp.19-29.


  10. Simon Sakaria, Sachin B. Patkar, S.S.S.P.Rao, Performance enhancements using register windows on UltraSPARC, CSI Journal of Computer Science and Informatics, Vol 30, No.1, March 2000.


  11. Mangalam, G.N., S. S. S. P. Rao, G.Sivakumar, Software Pipelining for UltraSPARC, CSI Journal of Computer Science and Informatics, vol 30,No.2, June 2000, pp.9-15


  12. Syam S. Pannala, Sachin Chitnis, S.S.S.P.Rao, Intra-Basic Block Optimisation: Revisited for UltraSPARC Architecture,CSI Journal of Computer Science and Informatics, Vol 29, No.3, 2000, pp 71-77


  13. Rajul Maheswari, S.S.S.P.Rao, P.G.Poonacha, FPGA Implementation of Median Filter, Proceedings of International Conference on VLSI Design'97, Jan.4-7, 1997, pp. 523-524.


  14. C.R.Venugopal & S.S.S.P.Rao, IMPACT of Delays in Parallel I/O System, CSI Journal, Vol.26, No.2, June 1996, pp. 43-55.


  15. S.M.Bhandari, K.V.V.Murthy, S.S.S.P.Rao, "New Approach to the Associative Memory Design using Neural Networks", IASTED Journal of Computers & Control Vol 20, No.2, 1992, pp.34-38.


  16. Y.Z.Lashkari, S.S.S.P.Rao, V.Y.Mhaskar, A.C.Shelat, "PIX: A Proposal to Implement a General Broad-casting Facility in a Distributed Environment Running X Windows", Computer Graphics Vol.16, No.2., July 1992, pp.143-149.


  17. S.S.S.P.Rao, Personal Computers: An Overview Introduction", Electronics Today, Vol-17,No.9,Sept.84, pp.59-60."


  18. S.S.S.P.Rao, "Microprocessors & Microcomputers : An Introduction", Electronics Today, Vol-17,No.9,Sept.84, pp.41-52


  19. S.M.Bhandari, Murthy, K.V.V., Rao, S.S.S.P., "Design of artificial Neural Network chip for Image Processing Applications", AMSE Review, Vol.11 No.2, 1991, pp.43-51.


  20. S.S.S.P.Rao, J.R.Isaac, "Interface Optimization: An Algorithm for the Detection of Data Path Redundancy and Reconfigurability Towards Obtaining Minimal Bus Interface, IEEE Transactions on Computers, Vol.38, No.11, Nov. 1989, pp. 1577-1579.


  21. S.S.S.P.Rao, Vin, H.M., "Graphics Controllers: An Overview", IETE Technical Review, Vol.4, No.10, Oct.87 pp.371-377.


  22. S.S.S.P.Rao, R. Nemani, "Modular Approach to Colour graphics system Design : Hardware Aspects", Microprocessors and Microsystem, Vol.11,No.2, March 1987,PP.89-93.


  23. S.S.S.P.Rao, S.Pardikar, M.Vaidya, "G.K.S.Implementation : A case study", Computers & Graphics, Vol.11, No.2, 1986, pp.75-78.


  24. S.S.S.P.Rao, J.R.Isaac, "Micro-store width optimization through bit steering" Microprocessing and Microprogramming, Vol.16,No.1, Aug.1985 PP.17-30.


  25. S.S.S.P.Rao, V.Ramesh, "Microstore Optimization based on Micro- operation utilization profile" Microprocessing and Microprogramming, Vol.13,No.2, Feb.1984, PP.115-120.


  26. S.S.S.P.Rao, D.N.Deokar, S.A.Chitale, "A floppy system inter- face to the EC-1030 Computer", Journal of the IETE Vol.29, No.9 1983,PP.449-452.


  27. S.S.S.P.Rao, L.S.Radha Krishna, V.Shukla, "Performance monitor- ing of the EC-1030 system by a Microprocessor based Systems", Microprocessor and Microsystem, Vol.6, No.4, May 1982, PP.183-188.


  28. S.S.S.P.Rao, T.Pradhan, "A microprogrammable Peripheral controller", Microprocessors and Microsystem, Vol.6, No.3, April 1982, PP.107-116.


  29. S.S.S.P. Rao, Dorab Patell, "Microprogrammable architecture:An implementation on the EC-2030", CSI Communication, October 1980,PP.3-9


  30. S.S.S.P. Rao, V.K. Agarwal, "A microprocessor based tea dryer controller", ACM SIGSMALL NEWS LETTER, Vol.6.NO.2, Sept. 1980,pp.137-147.