The course material is freely usable for educational and non-commercial research purpose, with due attribution. Any commercial use requires prior written permission from the author. If you are the owner of any of the content included (eg. images), and feel that it has been unfairly used, kindly let me know and I will either attribute it to you as you specify or take it off, depending on your request.
ACKs Many of the slides are adapted and modified versions of some of the excellent Digital logic and computer architecture courses taught by Joel Emer, Arvind, Yale Patt, Nima Honarmand, Hal Perkins, John Kubiatowicz, Onur Mutlu, Shankar Balachandran, Krste Asanovic, David Black-Schaffer, Rajeev Balasubramonian, and Mainak Chaudhuri.
| Week | Lectures slides and videos | Reading | Assignment | Tests |
| August 2 |
Lec-1: Course Introduction [slides] |
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| August 4 |
Lec-2: Digital Logic gates [slides] |
Textbook reading: Harris & Harris, Section 2.1 to 2.7 |
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August 9 |
Lec-3: Combinational circuits [slides] |
Textbook reading: Harris & Harris, Section 2.8 |
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August 16 |
Lec-4: Sequential circuits [slides] |
Textbook reading: Harris & Harris, Section 3.4 |
Problem-set-1 (solution released) |
SAFE Quiz-I |
August 18 |
Lec-5: Sequential circuits-II [slides] |
Textbook reading: Harris & Harris, Section 3.4 |
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August 23 |
Lec-6: ISA and MIPS Instructions-I [slides] |
Textbook reading: P & H, Chapter 2 |
Problem Set 2 (solution released) |
SAFE Quiz-II |
August 25 |
Lec-7: MIPS Instructions-II [slides] |
Textbook reading: P & H, Chapter 2 |
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August 30 |
Lec-8: MIPS Instructions-III [slides] |
Textbook reading: P & H, Chapter 2 |
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Sept 1 |
Lec-9: Instruction decoding and addressing modes [slides] |
Textbook reading: P & H, Chapter 2 |
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Sept 6 |
Lec-10: ISA+Microarch. [slides] |
Textbook reading: P & H, Chapter 2 |
Problem-set-3 (solution released) |
SAFE Quiz-III |
Sept 8 |
Lec-11: Single Cycle CPU [slides] |
Textbook reading: P & H, Chapter 4 |
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Sept 13 |
Lec-12: Instruction pipelining [slides] |
Textbook reading: P & H, Chapter 4 |
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Sept 27 |
Lec-13: Data/Control Hazards [slides] |
Textbook reading: P & H, Chapter 4 |
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Sept 29 |
Lec-14: Mitigating Control Hazards [slides] |
Textbook reading: P & H, Chapter 4 |
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October 4 |
Lec-15: Branch Prediction and Interrupt handling [slides] |
Textbook reading: P & H, Chapter 4 |
Problem sets and Quizzes during labs |
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October 6 |
Lec-16: O3 + Superscalar + Performance [slides] |
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October 11 |
Lec-17: Memory Hierarchy [slides] |
Textbook reading: P & H, Chapter 4 |
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October 13 |
Lec-18: Caches [slides] |
Textbook reading: P & H, Chapter 4 |
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October 18 |
Lec-19: Caches-II [slides] |
Textbook reading: P & H, Chapter 4 |
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October 20 |
Lec-20: Caches-III [slides] |
Textbook reading: P & H, Chapter 4 |
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October 25 |
Lec-21: Multicore caches [slides] |
Textbook reading: P & H, Chapter 4 |
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November 3 |
Lec-22: DRAM Organization [slides] |
Textbook reading: P & H, Chapter 4 |
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November 7 |
Lec-23: Cache Coherence [slides] |
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November 8 |
Lec-24: Out-of-order processor [slides] |
Textbook reading: H & P, Chapter 3 |
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