Nomoshkar ! 
Hellooooo, I'm a masters student at IIT Bombay in the CSE Department.
Finally decided to use my talent of breaking things to try break micro-architectural security and hopefully live to tell the tale.
I am working under Prof. Sayandeep Saha and Prof. Biswabandan Panda.
Gate Score : 899
Gate Score : 896
Whiled away my time fixing bugs in Parsers and RTL synthesizers, accidentally drank too much coffee, tripped over a few cables and somehow developed/maintained a few CAD related tools on SystemVerilog for some EDA and consumer Electronics (wink ;) ;) iykyk) companies.
Skills Gained (and then Lost): C++, SystemVerilog, GDB, Valgrind. VIM, Makefile and Appearing to look busy, doing absolutely nothing useful.
Responsibilities (Whoever thought this was a good idea, God Bless their soul) : Test-plan generation, Q/A Testing, Linting, Product Development, Customer Support and Finishing the snacks in the common fridge.
Worked on a new feature product on RTL Synthesis leveraging Verific’s exisiting industry standard C++ parser suite for SystemVerilog, VHDL and Mixed Language Designs.
Skills Gained : C++, Object Oriented Programming Design, SystemVerilog, VHDL, CVS, and Delusions of Grandeur.
Responsibilities : Just show up and try not to break production and bankrupt the company.
Bachelor Thesis : Community Detection in Dynamic Networks
