Professor, Department of Computer Science & Engg., IIT
Bombay
External Interaction
I worked as a Chief Scientist with Tata Research Design and
Development Center (TCS), Pune from Aug 2014 to Apr 2015. My
other external interactions are as under.
Compiler Construction:
From Practice to Theory (with Prof. Amitabha
Sanyal). Faculty Development Program conducted by
TCS, Pune. (February 2009).
Compiler Construction:
From Practice to Theory (with Prof. Amitabha
Sanyal). Training program for college teachers
held at IIITDM, Jabalpur. (December
2008).
Compiler Construction: From Practice to Theory
(with Prof.
Amitabha Sanyal). TEQIP course for college teachers
held at College of Engineering, Pune.
(September 2007)
Automatic Construction of Scannners and Parsers
Blue Star Infotech Ltd. (Mumbai).
(February 2007).
Data Flow Analysis to Tata Infotech Ltd. (December 1999).
Language Processing to Tata Infotech Ltd. (December 1998).
Design and Implementation of Low Level Language
Processing Tools to Cirrus Logic Software (I) Pvt.
Ltd. (November 1998).
Have provided consultancy to Mastek, Pune for
developing a compiler for their proprietary software
specification language (called MERIT) for large
applications in Enterprise Resource Planning. The work
also involved helping them evaluate their language for a
subsequent redesign in future
(December 1996 to May 1997).
Bidirectional Data Flow Analysis to Tata
Research Design and Development Center
(May 1996 to July 1996).
Was the chief designer of VxC being designed and
implemented by Tata Infotech Ltd. VxC is a variant of C for
embedded systems applications.
(September 2000 to November 2001).
Tuning of lcc for better code generation for UMS
chip of Cradle Technologies Ltd.
(December 2000 to May 2001).
Was the principal architect of an optimising compiler for
VxC being designed and implemented by Tata Infotech Ltd. for
a DSP chip of VxTel (an Intel Company).
Some details about this compiler can be found here. (September 2000 to November 2001).
Precise and scalable pointer analysis. Science and
Engineering Research Board, DST. (Nov
2019 onwards).
Scalable and Precise Program Analysis. Tata Consultancy
Services. (Sep 2013 to Aug 2016).
Parallel Computing Research Prospects. Intel Technology
India Pvt. Ltd. (Jan 2011 March
2013).
GCC Resource
Center. Sponsored by Department of Information
Technology, Ministry of Communication and Information
Technology, Government of India. (May 2009 to April 2013).
Improving garbage collection through static analysis.
Sponsored by Synopsys India (Pvt.) Ltd., Bangalore (May 2003 to Dec 2003).
Have carried out a
feasibility study for the design and implementation of
an optimising compiler for a DSP chip on behalf of Tata Infotech Ltd. (June 2000).
Have carried out a
feasibility study on rapid software development for DSP
chips for Cirrus Logic Software (I) Pvt. Ltd. (May 1998 to June 1998).
Retargeting of GNU C/C++ compiler and assorted tools
for ARC100 and ARC200 RISC cores designed by ARCUS
Technologies Pvt. Ltd., Bangalore (May
1994 to November 1994).
Have supervised the development of an optimising
FORTRAN compiler in the capacity of a Senior Project
Engineer for a brief period at IIT Bombay before joining
Ph.D. This project was sponsored by DoE
(March 1989 to July 1989).