Ashutosh Trivedi: Courses/CS254

Instructor: Ashutosh Trivedi (trivedi@cse)
Teaching Assistants (course) :
- Mohit Gupta (mohit12071994@gmail),
- Srikanti Praneeth (svpraneethnaidu@cse),
- Nilesh Kulkarni (nileshsatishkulkarni@gmail),
- Nishit Bhandari (nishitb@cse),
- Vivek Agarwal (vivekcse@cse),
- Darsh Shash (darshs@cse),
- Devdevdeep Ujjal Ray (devdeep@cse),
- Divyan Bansal (Divyambansal93@gmail)
Teaching Assistants (Lab) :
- Prateek Chopra (prateekjain035@gmail),
- varun shah (varunshah_1990@yahoo), and
- Aniruddha Kushwaha (anikush88@yahoo)
Prerequisites None
Lectures:
- Tuesday (6:35pm—8:00pm)
- Friday (6:35pm—8:00pm)
Lab:
- Wednesday (2:00pm—5:00pm)
Office hours:
- Ashutosh Trivedi (Friday 2:00pm—3:00pm), SIA 08, KReSIT Bldg.
Venue :
- Lectures: SMA206 (Class Room : IC 4)
- Lab: TBA
- Office hours: SIA 108, 1st floor, 'A' Block, KReSIT building
- Piazza page: https://piazza.com/iitb.ac.in/autumn2015/cs226/home.

Main Reference

M. Morris Mano and Michael Ciletti. Digital Design
Low priced paperback edition published by Pearson Education.
Stephen Brown and Zvonko Vranesic. Digital Logic with VHDL Design
McGraw Hill Education. Indian Edition.

Lab Reference

Digital Systems and Binary Numbers
- Binary Systems
- Conversions
- Octal, Hex, Complements
- Signed Binary, Codes, Logic
Boolean Algebra and Logic Gates
- Axioms, Theorems,
- Boolean Functions
- Canonical forms, operators, gates
Gate-level Minimization
- Truth table, K Map
- 2, 3 variable map
- 4 variable map
- SOP, POS, NAND, NOR
- XOR and minimization
Combinational Logic
- Combinational circuits
- Analysis, design, binary adder
- Subtractor, decimal adder, multipler
- Decoder, Encoder, Multiplexer
[Mid-semester Exams]
Synchronous Sequential Logic
- Sequential ckts
- Latches
- Flip flops
- JK and T FF
- State Machines
- State machine
- State machine reduction
- State machine examples
Registers and Counters
- Registers
- Shift Registers
- Ripple Counters, Sync counters
Memory and Programmable Logic
- Memory-RAM
- TCAM, QDR, DDR
- Encoding, Decording
Design at the RTL Level
- RTL Notation
- State machine exampls
Special Topics
- Asynchronous Sequential Logic
- Digital Circuit Verification
- Class Projects

#	Date	Description	Textbook References
1	Jan 13	Introduction to Digital Logic Design [Slides ]
2	Jan 16	Digital Systems and Binary Numbers [Slides ]	Morris Mano and Clietti: Chapter 1
3	Jan 20	Binary Arithmetic (Contd.) [Slides ]	Morrid Mano and Clietti: Chapter 1
4	Jan 23	Introduction to Logic Circuits	Morris Mano and Clietti: Chapter 2, Brown and Vranesic: Chapter 2

This term we will be using Piazza for class discussion. The system is highly catered to getting you help fast and efficiently from classmates, the TA, and myself. Rather than emailing questions to the teaching staff, I encourage you to post your questions on Piazza. If you have any problems or feedback for the developers, email team@piazza.com.
Find our class page at: https://piazza.com/iitb.ac.in/autumn2015/cs226/home.