PLACID 2024

Sriram Rajamani

President and Managing Director, Microsoft Research

Programming and Machine Learning

Sriram Rajamani is Corporate Vice President and Managing Director of Microsoft Research India. Sriram is an ACM fellow, INAE fellow, and winner of the Computer Aided Verification Award. His work has impacted both academic and industrial practice in programming languages, systems, security, and formal verification. He is currently working on reimagining the future of programming and software engineering with LLMs to improve productivity, agility and user experience while preserving reliability and security. Sriram did his PhD in Computer Science at UC Berkeley.

Pritam Gharat

Senior Researcher at Microsoft Research

LLMs for Code Generation, Static Analysis, Verification

Pritam is a Senior Researcher at Microsoft Research (MSR) where she is working on leveraging Large Language Models (LLMs) for static analysis. Prior to this, she was a Postdoctoral Researcher at Imperial College, London where she worked on static analysis and dynamic symbolic execution for efficient bug detection. She has done her masters and doctoral degrees in Computer Science from IIT Bombay. Her Ph.D. thesis focused on Pointer Analysis and proposed a new form of representation for procedure summaries that can be used for scalable flow- and context-sensitive points-to analysis.

Ramana Radhakrishnan

Director CPU Compilers, NVIDIA

Compilers, Software tools and Toolchains

Ramana has worked in the field of compilers since 2002 and has worked on building out GNU Toolchain for a variety of CPU architectures including some very popular ones such as AArch64. He is involved with GCC as a steering committee member and as a maintainer for the AArch32 port. While GNU Toolchain has been his mainstay, he has also dabbled in the field of machine learning compilers building out a team. He currently leads a team doing OSS CPU Compilers for Grace, NVIDIA's data centre CPU , Grace and is very interested in compiler optimisations for GCC and LLVM designed for these CPUs.

Shekhar Divekar

Principal Compiler Engineer, NVIDIA

Shekhar is a compiler engineer with 20+ years of experience in the area of compilers. He has worked on compilers for different types of architectures like RISC/DSP/GPUs. He has experience in mid and low level optimizations including register allocation, instruction scheduling etc. Currently he manages the GPU compiler backend team in NVIDIA. His team work on mid and low level optimizations for GPUs. The focus of the team is supporting new GPU architectures and tuning the code generation for graphics (gaming) and compute (CUDA) workloads. The compiler handles all types of programing APIs supported by the GPU.

Girish Bharambe

Senior System SW Manager, NVIDIA

PTX Compiler for NVIDIA GPUs

Girish works as Senior System SW Manager for GPU Compilers in NVIDIA. He manages PTX Compiler group and assembler/disassembler tools group at NVIDIA. He has experience in working on GPU programming languages design, compiler front end implementation and linkers, ABI for GPUs. He has worked on all NVIDIA GPUs since Fermi generation and has contributed to lot of features in CUDA and PTX since then. He has several patents in areas of abstraction for GPU programs, linkers and runtime. His areas of interest are programming language design, ABI and linkers.

Sameer Sahasrabuddhe

Sameer is Principal MTS (PMTS) at AMD in the AI GPU Software Group (working on the GPU compiler). He has done his PhD in Computer Science from IIT Bombay.

Compilers for AMD GPUs

Sameer is Principal MTS (PMTS) at AMD in the AI GPU Software Group (working on the GPU compiler). He has done his PhD in Computer Science from IIT Bombay.

Saiyedul Islam

Principal Member of Technical Staff (MTS), AMD

Compilers, HPC, GPU Programming

Saiyed is Senior MTS at AMD in the AI Group working on GPU Compilers. He is also an Adjunct Faculty at BITS Pilani's WILP Division. He has been working on GPUs since 2009. He designed a Domain Specific Language for Clustering and its parallelizing compiler targeting distributed systems during his PhD at BITS Pilani. His primary interests are HPC, Data Clustering, Programming Languages, and Compiler Design.

Gireesh Punathil

Master inventor and Senior Technical Staff Member, IBM

Programming and Machine Learning

Gireesh is an IBM master inventor and Senior Technical Staff Member part of IBM Runtimes team that develops and supports Java, Node.js and Eclipse SDK. He is an Eclipse committer and Node.js TSC member. In 22 years of his career, he has been porting, developing and debugging web servers, virtual machines, compilers and cloud platform frameworks. He has spoken at several Node.js, Java and Eclipse conferences and has authored a book on Node.js enterprise application development.

Makarand Kulkarni

Software-Wireless & Networking, Saankhya labs

DSLs for Radio Access Networks (RAN)

Makarand leads the wireless innovation efforts at Saankhya labs with focus on improving the operational and development efficiencies of RAN solutions. He is an active member of O-RAN standardization forum where he represents Saankhya in WG6.He has extensive experience in building and deploying wireless infrastructure products and is a known SME in the field. Prior to Saankhya, Makarand has been part of several leading edge startups like UbiNetics (now Viavi), well known for the TM500 series of test platforms and then Navini networks, a pioneer in industry leading beamforming solutions.

Sameera Deshpande

Principal Compiler Engineer, Quadric Inc

Graph Compiler and LLVM

Sameera is Principal Compiler Engineer at Quadric Inc, managing team of 6 compiler Engineers globally. Their team at Quadric Inc work on Graph compiler and LLVM for our Chimera architecture.

Arun Rangasamy

Senior Staff Engineer, Qualcomm

Compiler & Tools for Snapdragon Chipsets

Arun Rangasamy is a Senior Staff Engineer at Qualcomm, Hyderabad. He has over 14 years of industry experience in developing compilers for CPUs, GPUs and DSPs, simulators and firmware. His doctoral thesis at IISc, Bangalore focused on compiler-based energy optimization

Ravishankar Kolachana

Director Engineering, Qualcomm

Compiler & Tools for Snapdragon Chipsets

Ravishankar is Director Engineering at Qualcomm. Since he graduated from IIT Guwahati, Ravi has been passionate about Computer Systems in general and Compilers in particular. He is also passionate about Program Analysis and code hygiene tools. He has been working in the Wireless semiconductor industry for almost 22 years now. For the past 7 years he has been mainly working Compilers, linkers, loaders, simulators, debuggers and IDEs.

R Venkatesh

Chief Scientist at TCS Research

Tools for analysis and synthesis of programs

With over 30 years of experience in TCS Research, Venkatesh specializes in developing tools for program analysis and synthesis. His journey began with formal verification tools and has evolved to specialize in program synthesis, continually advancing software development capabilities.