CS226: Digital Logic Design
CS254: Digital Logic Design Lab
(Spring 2018)

  • Please subscribe to moodle and Piazza to stay updated about the course. The code for joining the class on piazza has been announced in class. If you missed it, please contact the instructor.
  • Practice problem set 1 has been posted.

Teaching Staff

Instructor Supratik Chakraborty
Friendly Theory TAs Swati Anand Kantikumar Anil Lahoti Vaishali Jhalani Himadri Sekhar Bandyopadhyay Ashish Mithole Mohammed Kaleem
Friendly Lab TAs Shubham Goel Kartik Singhal Shriram S. B. Utsav Anand Manjunath K Anup Kori


What When Where
Thurs 15:30 - 17:00
Fri 15:30 - 17:00
LA 301, Lecture Hall Complex
CC 103, New CSE Building
Tues 14:00 - 17:00
LH 302, Lecture Hall Complex
Office hour
Thurs 18:00-19:00
(by prior email appointment)
Room 314 (New CSE Building)
Problem solving session


CS226 CS254
Midterm 30%
Endterm 40%
Quizes 30%
In-semester lab evaluation 30%
Final project 70%

Ground Rules

Online discussions

We will use Piazza as the primary mode of online discussion for this course. Please visit the course page and sign up as a student using the access code announced in class. Rather than emailing questions to the teaching staff, I encourage you to post your questions on Piazza.

Reading Material

Software needed for lab work

You will need to download and install the following software on your laptops for the lab assignments and for your final project.

Practice Questions and Exams

Please see last two years' (2016, 2017) course pages for old problem sets (practice and exam).
Questions Posted on Graded/Ungraded
Practice Question Set 1 Jan 13, 2018 Ungraded

Lecture Schedule

Jan 5 Introduction, course logistics, motivation for turning algorithms to circuits, basic logic gates, truth-tables and designing circuits from them, introduction to Karnaugh maps (K-maps)
Jan 11 More on K-maps and optimizing inputs of AND/OR gates in two-level AND-OR circuits, design of some basic building blocks: half-adder, full-adder, n-bit ripple-carry adder, Discussion of nominal delays through ripple carry adder.
Jan 12 More on adders, design of n-bit carry lookahead adders and nominal delay analysis, design of n-bit comparators and multiplexors. Converting simple programs to circuits using the datapath blocks (adders, comparators, multiplexors) learnt so far.

Lab Schedule

Jan 4 Introduction, lab logistics, a quick introduction to VHDL (Aniruddha's slides on VHDL)
Xilinx ISE related links: download local copy, Xilinx official installation/licensing doc, quick guide to installing/licensing ISE, getting started with ISE
Jan 9 More on VHDL, use of Xilinx ISE for design entry in VHDL, compilation and simulation using testbenches. Processes and sensitivity lists. Design of a simple, hierarchical design using processes. Simulation cycle of VHDL, and the notion of delta delays in simulation.
Files used in class: design, test harness
Jan 16 Implementing a Wallace Tree Multiplier for multiplying two 3-bit numbers using a hierarchical design style
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