Textbooks: Computer Organization and Design by P&H and Computer Architecture: A Quantitative Approach by H&P.
The course material is freely usable for educational and non-commercial research purpose, with due attribution. Any commercial use requires prior written permission from the author. If you are the owner of any of the content included (eg. images), and feel that it has been unfairly used, kindly let me know and I will either attribute it to you as you specify or take it off, depending on your request.
ACKs Many of the slides are adapted and modified versions of some of the excellent computer architecture courses taught by Joel Emer, Arvind, Yale Patt, Nima Honarmand, Hal Perkins, John Kubiatowicz, Onur Mutlu, Krste Asanovic, David Black-Schaffer, Rajeev Balasubramonian, and Mainak Chaudhuri.
| Week | Lectures slides and videos | Reading | Assignment | Tests |
| July 26 |
Lec-0: Course Introduction [slides] [video] Lec-1: MIPS Instructions-I (arithmetic/logical) [slides] [video] Lec-2: MIPS Instructions-II (stored program concept) [slides] [video] |
Chapter 2 of P&H (5th edition) : Section 2.1 to 2.3, and 2.6 Turing Lecture |
Assignment-0: Bonjour CS305!! |
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| August 2 |
Lec-3: MIPS Instructions-III (branch) [slides] [video] Lec-4: MIPS Instructions-IV (JAL and RA) [slides] [video] Lec-4.1: MIPS Instructions-IV.1 (JAL:PC+8) [slides] [video] Lec-5: MIPS Instructions-V (Register spilling) [slides] [video] Lec-6: MIPS Instructions-VI (Stack/frame pointers) [slides] [video] |
Chapter 2 of P&H: Section 2.7 to 2.9 |
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| August 9 |
Lec-7: Instruction decoding [slides] [video] Lec-8: Addressing modes [slides] [video] Lec-9: ISA [slides] [video] Lec-10: x86/ARM ISAs [slides] [video] Lec-11: Endianness and Alignment [slides] [video] |
Chapter 2 of P&H: Section 2.10, 2.17 to 2.19 (x86 and ARM), and page no 69 RISC-ISCA81 paper RISC-V |
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Mini Quiz-I |
| August 16 |
Lec-12: Single Cycle CPU-I [slides] [video] Lec-13: Single Cycle CPU-II [slides] [video] Lec-14: The Iron Law [slides] [video] |
Chapter 4 of P&H: Section 4.1 to 4.4 and Chapter 1: Section 1.6 |
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| August 23 |
Lec-15: Empirical Evaluation-I [slides] [video] Lec-16: Empirical Evaluation-II [slides] [video] Lec-17: Empirical Evaluation-III [slides] [video] Lec-18: Multi-cycle CPU [slides] [video] Lec-19: Instruction Pipelining [slides] [video] |
Chapter 1: Section 1.7 to 1.10 |
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Mini Quiz-II |
| August 30 |
Lec-20: Instruction Pipelining-II [slides] [video] Lec-21: Instruction Pipelining-III [slides] [video] |
Chapter 4: Section 4.5 and 4.6 |
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| Sept. 6 |
Lec-22: Pipeline Hazards [slides] [video] Lec-23: Hazard Mitigations [slides] [video] Lec-24: Branch Delay Slots [slides] [video] Lec-25: Branch Prediction [slides] [video] |
Chapter 4: Section 4.7 and 4.8 |
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| Sept. 13 |
No lectures: Mid-term week |
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| Sept. 20 |
Lec-26: Branch Prediction -II [slides] [video] Lec-27: Interrupt/Exception handling [slides] [video] Lec-28: Superscalar and Out-of-order processor [slides] [video] |
Chapter 4: Section 4.9 and 4.10 |
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| Sept. 27 |
Lec-29: Memory Hierarchy [slides] [video] Lec-30: Caches-I [slides] [video] Lec-31: Caches-II [slides] [video] |
Chapter 5: Section 5.1 to 5.3 |
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| Oct. 4 |
Lec-32: Caches-III [slides] [video] Lec-33: Caches-IV [slides] [video] Lec-34: Caches-V [slides] [video] |
Chapter 5 P&H: Section 5.4 and 5.8 Chapter 2 H&P: Section 2.3 |
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| Oct. 11 |
Lec-35: Hardware Prefetching [slides] [video] Lec-36: Virtual Caches [slides] [video] Lec-37: Cache Coherence [slides] [video] |
Chapter 5 P&H: Section 5.7 Chapter 2 H&P: Figure 2.25, Chapter 5:Section 5.2 |
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| Oct. 18 |
Lec-38: DRAM Organization [slides] [video] Lec-39: DRAM Timing Constraints [slides] [video] Lec-40: Storage/IO [slides] [video] |
Chapter 5 P&H: Section 5.2 |
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| Oct. 25 |
Lec-41: Dynamic Instruction Scheduling [slides] [video] Lec-42: Speculative Execution [slides] [video] Lec-43: Spectre and Meltdown [slides] [video] |
Chapter 3 H&P: Section 3.4 and 3.6 |
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| Nov. 1 |
Lec-44: SMT (Hyperthreading) [slides] [video] Lec-45: Trends in Computer Architecture [slides] [video] |
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